<s>
The	O
control	B-General_Concept
unit	I-General_Concept
(	O
CU	O
)	O
is	O
a	O
component	O
of	O
a	O
computer	O
's	O
central	B-General_Concept
processing	I-General_Concept
unit	I-General_Concept
(	O
CPU	B-General_Concept
)	O
that	O
directs	O
the	O
operation	O
of	O
the	O
processor	O
.	O
</s>
<s>
A	O
CU	O
typically	O
uses	O
a	O
binary	O
decoder	O
to	O
convert	O
coded	O
instructions	O
into	O
timing	O
and	O
control	O
signals	O
that	O
direct	O
the	O
operation	O
of	O
the	O
other	O
units	O
(	O
memory	O
,	O
arithmetic	B-General_Concept
logic	I-General_Concept
unit	I-General_Concept
and	O
input	O
and	O
output	O
devices	O
,	O
etc	O
.	O
</s>
<s>
It	O
directs	O
the	O
flow	O
of	O
data	O
between	O
the	O
CPU	B-General_Concept
and	O
the	O
other	O
devices	O
.	O
</s>
<s>
John	O
von	O
Neumann	O
included	O
the	O
control	B-General_Concept
unit	I-General_Concept
as	O
part	O
of	O
the	O
Von	B-Architecture
Neumann	I-Architecture
architecture	I-Architecture
.	O
</s>
<s>
In	O
modern	O
computer	B-General_Concept
designs	I-General_Concept
,	O
the	O
control	B-General_Concept
unit	I-General_Concept
is	O
typically	O
an	O
internal	O
part	O
of	O
the	O
CPU	B-General_Concept
with	O
its	O
overall	O
role	O
and	O
operation	O
unchanged	O
since	O
its	O
introduction	O
.	O
</s>
<s>
In	O
a	O
computer	O
,	O
the	O
control	B-General_Concept
unit	I-General_Concept
often	O
steps	O
through	O
the	O
instruction	B-General_Concept
cycle	I-General_Concept
successively	O
.	O
</s>
<s>
When	O
the	O
next	O
instruction	O
is	O
placed	O
in	O
the	O
control	B-General_Concept
unit	I-General_Concept
,	O
it	O
changes	O
the	O
behavior	O
of	O
the	O
control	B-General_Concept
unit	I-General_Concept
to	O
complete	O
the	O
instruction	O
correctly	O
.	O
</s>
<s>
So	O
,	O
the	O
bits	O
of	O
the	O
instruction	O
directly	O
control	O
the	O
control	B-General_Concept
unit	I-General_Concept
,	O
which	O
in	O
turn	O
controls	O
the	O
computer	O
.	O
</s>
<s>
The	O
control	B-General_Concept
unit	I-General_Concept
may	O
include	O
a	O
binary	O
counter	O
to	O
tell	O
the	O
control	B-General_Concept
unit	I-General_Concept
's	O
logic	O
what	O
step	O
it	O
should	O
do	O
.	O
</s>
<s>
Multicycle	O
control	B-General_Concept
units	I-General_Concept
typically	O
use	O
both	O
the	O
rising	O
and	O
falling	O
edges	O
of	O
their	O
square-wave	O
timing	O
clock	O
.	O
</s>
<s>
An	O
interrupt	B-Application
occurs	O
because	O
some	O
type	O
of	O
input	O
or	O
output	O
needs	O
software	O
attention	O
in	O
order	O
to	O
operate	O
correctly	O
.	O
</s>
<s>
An	O
exception	B-General_Concept
is	O
caused	O
by	O
the	O
computer	O
's	O
operation	O
.	O
</s>
<s>
One	O
crucial	O
difference	O
is	O
that	O
the	O
timing	O
of	O
an	O
interrupt	B-Application
cannot	O
be	O
predicted	O
.	O
</s>
<s>
a	O
memory-not-available	O
exception	B-General_Concept
)	O
can	O
be	O
caused	O
by	O
an	O
instruction	O
that	O
needs	O
to	O
be	O
restarted	O
.	O
</s>
<s>
Control	B-General_Concept
units	I-General_Concept
can	O
be	O
designed	O
to	O
handle	O
interrupts	B-Application
in	O
one	O
of	O
two	O
typical	O
ways	O
.	O
</s>
<s>
If	O
a	O
quick	O
response	O
is	O
most	O
important	O
,	O
a	O
control	B-General_Concept
unit	I-General_Concept
is	O
designed	O
to	O
abandon	O
work	O
to	O
handle	O
the	O
interrupt	B-Application
.	O
</s>
<s>
If	O
the	O
computer	O
is	O
to	O
be	O
very	O
inexpensive	O
,	O
very	O
simple	O
,	O
very	O
reliable	O
,	O
or	O
to	O
get	O
more	O
work	O
done	O
,	O
the	O
control	B-General_Concept
unit	I-General_Concept
will	O
finish	O
the	O
work	O
in	O
process	O
before	O
handling	O
the	O
interrupt	B-Application
.	O
</s>
<s>
Exceptions	O
can	O
be	O
made	O
to	O
operate	O
like	O
interrupts	B-Application
in	O
very	O
simple	O
computers	O
.	O
</s>
<s>
If	O
virtual	B-Architecture
memory	I-Architecture
is	O
required	O
,	O
then	O
a	O
memory-not-available	O
exception	B-General_Concept
must	O
retry	O
the	O
failing	O
instruction	O
.	O
</s>
<s>
In	O
a	O
pipelined	O
computer	O
,	O
the	O
control	B-General_Concept
unit	I-General_Concept
arranges	O
for	O
the	O
flow	O
to	O
start	O
,	O
continue	O
,	O
and	O
stop	O
as	O
a	O
program	O
commands	O
.	O
</s>
<s>
The	O
control	B-General_Concept
unit	I-General_Concept
also	O
assures	O
that	O
the	O
instruction	O
in	O
each	O
stage	O
does	O
not	O
harm	O
the	O
operation	O
of	O
instructions	O
in	O
other	O
stages	O
.	O
</s>
<s>
When	O
two	O
instructions	O
could	O
interfere	O
,	O
sometimes	O
the	O
control	B-General_Concept
unit	I-General_Concept
must	O
stop	O
processing	O
a	O
later	O
instruction	O
until	O
an	O
earlier	O
instruction	O
completes	O
.	O
</s>
<s>
Interrupts	B-Application
and	O
unexpected	O
exceptions	O
also	O
stall	O
the	O
pipeline	O
.	O
</s>
<s>
If	O
a	O
pipelined	O
computer	O
abandons	O
work	O
for	O
an	O
interrupt	B-Application
,	O
more	O
work	O
is	O
lost	O
than	O
in	O
a	O
multicycle	O
computer	O
.	O
</s>
<s>
For	O
example	O
,	O
if	O
an	O
exception	B-General_Concept
instruction	O
is	O
used	O
to	O
enter	O
the	O
operating	O
system	O
,	O
it	O
does	O
not	O
cause	O
a	O
stall	O
.	O
</s>
<s>
It	O
typically	O
has	O
more	O
logic	O
gates	O
,	O
registers	O
and	O
a	O
more	O
complex	O
control	B-General_Concept
unit	I-General_Concept
.	O
</s>
<s>
Control	B-General_Concept
units	I-General_Concept
use	O
many	O
methods	O
to	O
keep	O
a	O
pipeline	O
full	O
and	O
avoid	O
stalls	O
.	O
</s>
<s>
For	O
example	O
,	O
even	O
simple	O
control	B-General_Concept
units	I-General_Concept
can	O
assume	O
that	O
a	O
backwards	O
branch	O
,	O
to	O
a	O
lower-numbered	O
,	O
earlier	O
instruction	O
,	O
is	O
a	O
loop	O
,	O
and	O
will	O
be	O
repeated	O
.	O
</s>
<s>
So	O
,	O
a	O
control	B-General_Concept
unit	I-General_Concept
with	O
this	O
design	O
will	O
always	O
fill	O
the	O
pipeline	O
with	O
the	O
backwards	O
branch	O
path	O
.	O
</s>
<s>
If	O
a	O
compiler	B-Language
can	O
detect	O
the	O
most	O
frequently-taken	O
direction	O
of	O
a	O
branch	O
,	O
the	O
compiler	B-Language
can	O
just	O
produce	O
instructions	O
so	O
that	O
the	O
most	O
frequently	O
taken	O
branch	O
is	O
the	O
preferred	O
direction	O
of	O
branch	O
.	O
</s>
<s>
In	O
a	O
like	O
way	O
,	O
a	O
control	B-General_Concept
unit	I-General_Concept
might	O
get	O
hints	O
from	O
the	O
compiler	B-Language
:	O
Some	O
computers	O
have	O
instructions	O
that	O
can	O
encode	O
hints	O
from	O
the	O
compiler	B-Language
about	O
the	O
direction	O
of	O
branch	O
.	O
</s>
<s>
Some	O
control	B-General_Concept
units	I-General_Concept
do	O
branch	B-General_Concept
prediction	I-General_Concept
:	O
A	O
control	B-General_Concept
unit	I-General_Concept
keeps	O
an	O
electronic	O
list	O
of	O
the	O
recent	O
branches	O
,	O
encoded	O
by	O
the	O
address	O
of	O
the	O
branch	O
instruction	O
.	O
</s>
<s>
Some	O
control	B-General_Concept
units	I-General_Concept
can	O
do	O
speculative	B-General_Concept
execution	I-General_Concept
,	O
in	O
which	O
a	O
computer	O
might	O
have	O
two	O
or	O
more	O
pipelines	O
,	O
calculate	O
both	O
directions	O
of	O
a	O
branch	O
,	O
and	O
then	O
discard	O
the	O
calculations	O
of	O
the	O
unused	O
direction	O
.	O
</s>
<s>
Results	O
from	O
memory	O
can	O
become	O
available	O
at	O
unpredictable	O
times	O
because	O
very	O
fast	O
computers	O
cache	B-General_Concept
memory	I-General_Concept
.	O
</s>
<s>
The	O
CPU	B-General_Concept
must	O
be	O
designed	O
to	O
process	O
at	O
the	O
very	O
fast	O
speed	O
of	O
the	O
cache	B-General_Concept
memory	I-General_Concept
.	O
</s>
<s>
Therefore	O
,	O
the	O
CPU	B-General_Concept
might	O
stall	O
when	O
it	O
must	O
access	O
main	O
memory	O
directly	O
.	O
</s>
<s>
In	O
modern	O
PCs	O
,	O
main	O
memory	O
is	O
as	O
much	O
as	O
three	O
hundred	O
times	O
slower	O
than	O
cache	B-General_Concept
.	O
</s>
<s>
To	O
help	O
this	O
,	O
out-of-order	O
CPUs	O
and	O
control	B-General_Concept
units	I-General_Concept
were	O
developed	O
to	O
process	O
data	O
as	O
it	O
becomes	O
available	O
.	O
</s>
<s>
But	O
what	O
if	O
all	O
the	O
calculations	O
are	O
complete	O
,	O
but	O
the	O
CPU	B-General_Concept
is	O
still	O
stalled	O
,	O
waiting	O
for	O
main	O
memory	O
?	O
</s>
<s>
Then	O
,	O
a	O
control	B-General_Concept
unit	I-General_Concept
can	O
switch	O
to	O
an	O
alternative	B-Operating_System
thread	I-Operating_System
of	I-Operating_System
execution	I-Operating_System
whose	O
data	O
has	O
been	O
fetched	O
while	O
the	O
thread	B-Operating_System
was	O
idle	O
.	O
</s>
<s>
A	O
thread	B-Operating_System
has	O
its	O
own	O
program	O
counter	O
,	O
a	O
stream	O
of	O
instructions	O
and	O
a	O
separate	O
set	O
of	O
registers	O
.	O
</s>
<s>
Designers	O
vary	O
the	O
number	O
of	O
threads	B-Operating_System
depending	O
on	O
current	O
memory	O
technologies	O
and	O
the	O
type	O
of	O
computer	O
.	O
</s>
<s>
Typical	O
computers	O
such	O
as	O
PCs	O
and	O
smart	O
phones	O
usually	O
have	O
control	B-General_Concept
units	I-General_Concept
with	O
a	O
few	O
threads	B-Operating_System
,	O
just	O
enough	O
to	O
keep	O
busy	O
with	O
affordable	O
memory	O
systems	O
.	O
</s>
<s>
Database	O
computers	O
often	O
have	O
about	O
twice	O
as	O
many	O
threads	B-Operating_System
,	O
to	O
keep	O
their	O
much	O
larger	O
memories	O
busy	O
.	O
</s>
<s>
Graphic	O
processing	O
units	O
(	O
GPUs	O
)	O
usually	O
have	O
hundreds	O
or	O
thousands	O
of	O
threads	B-Operating_System
,	O
because	O
they	O
have	O
hundreds	O
or	O
thousands	O
of	O
execution	O
units	O
doing	O
repetitive	O
graphic	O
calculations	O
.	O
</s>
<s>
When	O
a	O
control	B-General_Concept
unit	I-General_Concept
permits	O
threads	B-Operating_System
,	O
the	O
software	O
also	O
has	O
to	O
be	O
designed	O
to	O
handle	O
them	O
.	O
</s>
<s>
In	O
general-purpose	O
CPUs	O
like	O
PCs	O
and	O
smartphones	O
,	O
the	O
threads	B-Operating_System
are	O
usually	O
made	O
to	O
look	O
very	O
like	O
normal	O
time-sliced	O
processes	O
.	O
</s>
<s>
In	O
GPUs	O
,	O
the	O
thread	B-Operating_System
scheduling	O
usually	O
cannot	O
be	O
hidden	O
from	O
the	O
application	O
software	O
,	O
and	O
is	O
often	O
controlled	O
with	O
a	O
specialized	O
subroutine	O
library	O
.	O
</s>
<s>
A	O
control	B-General_Concept
unit	I-General_Concept
can	O
be	O
designed	O
to	O
finish	O
what	O
it	O
can	O
.	O
</s>
<s>
If	O
several	O
instructions	O
can	O
be	O
completed	O
at	O
the	O
same	O
time	O
,	O
the	O
control	B-General_Concept
unit	I-General_Concept
will	O
arrange	O
it	O
.	O
</s>
<s>
The	O
exact	O
organization	O
of	O
this	O
type	O
of	O
control	B-General_Concept
unit	I-General_Concept
depends	O
on	O
the	O
slowest	O
part	O
of	O
the	O
computer	O
.	O
</s>
<s>
One	O
kind	O
of	O
control	B-General_Concept
unit	I-General_Concept
for	O
issuing	O
uses	O
an	O
array	O
of	O
electronic	O
logic	O
,	O
a	O
"	O
scoreboard	O
""	O
that	O
detects	O
when	O
an	O
instruction	O
can	O
be	O
issued	O
.	O
</s>
<s>
An	O
alternative	O
style	O
of	O
issuing	O
control	B-General_Concept
unit	I-General_Concept
implements	O
the	O
Tomasulo	B-General_Concept
algorithm	I-General_Concept
,	O
which	O
reorders	O
a	O
hardware	O
queue	O
of	O
instructions	O
.	O
</s>
<s>
With	O
some	O
additional	O
logic	O
,	O
a	O
scoreboard	O
can	O
compactly	O
combine	O
execution	O
reordering	O
,	O
register	O
renaming	O
and	O
precise	O
exceptions	O
and	O
interrupts	B-Application
.	O
</s>
<s>
Further	O
it	O
can	O
do	O
this	O
without	O
the	O
power-hungry	O
,	O
complex	O
content-addressable	O
memory	O
used	O
by	O
the	O
Tomasulo	B-General_Concept
algorithm	I-General_Concept
.	O
</s>
<s>
Retiring	O
logic	O
can	O
also	O
be	O
designed	O
into	O
an	O
issuing	O
scoreboard	O
or	O
a	O
Tomasulo	B-General_Concept
queue	O
,	O
by	O
including	O
memory	O
or	O
register	O
access	O
in	O
the	O
issuing	O
logic	O
.	O
</s>
<s>
Out	O
of	O
order	O
controllers	O
require	O
special	O
design	O
features	O
to	O
handle	O
interrupts	B-Application
.	O
</s>
<s>
When	O
there	O
are	O
several	O
instructions	O
in	O
progress	O
,	O
it	O
is	O
not	O
clear	O
where	O
in	O
the	O
instruction	O
stream	O
an	O
interrupt	B-Application
occurs	O
.	O
</s>
<s>
For	O
input	O
and	O
output	O
interrupts	B-Application
,	O
almost	O
any	O
solution	O
works	O
.	O
</s>
<s>
However	O
,	O
when	O
a	O
computer	O
has	O
virtual	B-Architecture
memory	I-Architecture
,	O
an	O
interrupt	B-Application
occurs	O
to	O
indicate	O
that	O
a	O
memory	O
access	O
failed	O
.	O
</s>
<s>
This	O
memory	O
access	O
must	O
be	O
associated	O
with	O
an	O
exact	O
instruction	O
and	O
an	O
exact	O
processor	O
state	O
,	O
so	O
that	O
the	O
processor	O
's	O
state	O
can	O
be	O
saved	O
and	O
restored	O
by	O
the	O
interrupt	B-Application
.	O
</s>
<s>
So	O
,	O
these	O
control	B-General_Concept
units	I-General_Concept
might	O
use	O
all	O
of	O
the	O
solutions	O
used	O
by	O
pipelined	O
processors	O
.	O
</s>
<s>
x86	B-Operating_System
Intel	O
CPUs	O
since	O
the	O
Pentium	B-Device
Pro	I-Device
translate	O
complex	O
CISC	O
x86	B-Operating_System
instructions	O
to	O
more	O
RISC-like	O
internal	O
micro-operations	O
.	O
</s>
<s>
In	O
these	O
,	O
the	O
"	O
front	O
"	O
of	O
the	O
control	B-General_Concept
unit	I-General_Concept
manages	O
the	O
translation	O
of	O
instructions	O
.	O
</s>
<s>
The	O
"	O
back	O
"	O
of	O
the	O
CU	O
is	O
an	O
out-of-order	O
CPU	B-General_Concept
that	O
issues	O
the	O
micro-operations	O
and	O
operands	O
to	O
the	O
execution	O
units	O
and	O
data	O
paths	O
.	O
</s>
<s>
Most	O
modern	O
computers	O
use	O
CMOS	B-Device
logic	O
.	O
</s>
<s>
CMOS	B-Device
wastes	O
power	O
in	O
two	O
common	O
ways	O
:	O
By	O
changing	O
state	O
,	O
i.e.	O
</s>
<s>
The	O
usual	O
method	O
reduces	O
the	O
CPU	B-General_Concept
's	O
clock	O
rate	O
.	O
</s>
<s>
It	O
is	O
common	O
for	O
a	O
CPU	B-General_Concept
to	O
idle	O
during	O
the	O
transition	O
to	O
avoid	O
side-effects	O
from	O
the	O
changing	O
clock	O
.	O
</s>
<s>
This	O
was	O
invented	O
to	O
stop	O
non-interrupt	O
code	O
so	O
that	O
interrupt	B-Application
code	O
has	O
reliable	O
timing	O
.	O
</s>
<s>
However	O
,	O
designers	O
soon	O
noticed	O
that	O
a	O
halt	O
instruction	O
was	O
also	O
a	O
good	O
time	O
to	O
turn	O
off	O
a	O
CPU	B-General_Concept
's	O
clock	O
completely	O
,	O
reducing	O
the	O
CPU	B-General_Concept
's	O
active	O
power	O
to	O
zero	O
.	O
</s>
<s>
The	O
interrupt	B-Application
controller	O
might	O
continue	O
to	O
need	O
a	O
clock	O
,	O
but	O
that	O
usually	O
uses	O
much	O
less	O
power	O
than	O
the	O
CPU	B-General_Concept
.	O
</s>
<s>
Many	O
modern	O
low-power	O
CMOS	B-Device
CPUs	O
stop	O
and	O
start	O
specialized	O
execution	O
units	O
and	O
bus	O
interfaces	O
depending	O
on	O
the	O
needed	O
instruction	O
.	O
</s>
<s>
Some	O
computers	O
even	O
arrange	O
the	O
CPU	B-General_Concept
's	O
microarchitecture	O
to	O
use	O
transfer-triggered	O
multiplexers	O
so	O
that	O
each	O
instruction	O
only	O
utilises	O
the	O
exact	O
pieces	O
of	O
logic	O
needed	O
.	O
</s>
<s>
Also	O
it	O
then	O
is	O
the	O
only	O
CPU	B-General_Concept
that	O
requires	O
special	O
low-power	O
features	O
.	O
</s>
<s>
A	O
similar	O
method	O
is	O
used	O
in	O
most	O
PCs	O
,	O
which	O
usually	O
have	O
an	O
auxiliary	O
embedded	O
CPU	B-General_Concept
that	O
manages	O
the	O
power	O
system	O
.	O
</s>
<s>
However	O
,	O
in	O
PCs	O
,	O
the	O
software	O
is	O
usually	O
in	O
the	O
BIOS	B-Operating_System
,	O
not	O
the	O
operating	O
system	O
.	O
</s>
<s>
When	O
the	O
CPU	B-General_Concept
enters	O
a	O
power	O
saving	O
mode	O
(	O
e.g.	O
</s>
<s>
because	O
of	O
a	O
halt	O
that	O
waits	O
for	O
an	O
interrupt	B-Application
)	O
,	O
data	O
is	O
transferred	O
to	O
the	O
low-leakage	O
cells	O
,	O
and	O
the	O
others	O
are	O
turned	O
off	O
.	O
</s>
<s>
When	O
the	O
CPU	B-General_Concept
leaves	O
a	O
low-leakage	O
mode	O
(	O
e.g.	O
</s>
<s>
because	O
of	O
an	O
interrupt	B-Application
)	O
,	O
the	O
process	O
is	O
reversed	O
.	O
</s>
<s>
Older	O
designs	O
would	O
copy	O
the	O
CPU	B-General_Concept
state	O
to	O
memory	O
,	O
or	O
even	O
disk	O
,	O
sometimes	O
with	O
specialized	O
software	O
.	O
</s>
<s>
All	O
modern	O
CPUs	O
have	O
control	O
logic	O
to	O
attach	O
the	O
CPU	B-General_Concept
to	O
the	O
rest	O
of	O
the	O
computer	O
.	O
</s>
<s>
When	O
an	O
instruction	O
reads	O
or	O
writes	O
memory	O
,	O
the	O
control	B-General_Concept
unit	I-General_Concept
either	O
controls	O
the	O
bus	O
directly	O
,	O
or	O
controls	O
a	O
bus	O
controller	O
.	O
</s>
<s>
x86	B-Operating_System
PCs	O
use	O
an	O
older	O
method	O
,	O
a	O
separate	O
I/O	O
bus	O
accessed	O
by	O
I/O	O
instructions	O
.	O
</s>
<s>
A	O
modern	O
CPU	B-General_Concept
also	O
tends	O
to	O
include	O
an	O
interrupt	B-Application
controller	O
.	O
</s>
<s>
It	O
handles	O
interrupt	B-Application
signals	O
from	O
the	O
system	O
bus	O
.	O
</s>
<s>
The	O
control	B-General_Concept
unit	I-General_Concept
is	O
the	O
part	O
of	O
the	O
computer	O
that	O
responds	O
to	O
the	O
interrupts	B-Application
.	O
</s>
<s>
There	O
is	O
often	O
a	O
cache	B-General_Concept
controller	O
to	O
cache	B-General_Concept
memory	I-General_Concept
.	O
</s>
<s>
The	O
cache	B-General_Concept
controller	O
and	O
the	O
associated	O
cache	B-General_Concept
memory	I-General_Concept
is	O
often	O
the	O
largest	O
physical	O
part	O
of	O
a	O
modern	O
,	O
higher-performance	O
CPU	B-General_Concept
.	O
</s>
<s>
When	O
the	O
memory	O
,	O
bus	O
or	O
cache	B-General_Concept
is	O
shared	O
with	O
other	O
CPUs	O
,	O
the	O
control	O
logic	O
must	O
communicate	O
with	O
them	O
to	O
assure	O
that	O
no	O
computer	O
ever	O
gets	O
out-of-date	O
old	O
data	O
.	O
</s>
<s>
Many	O
historic	O
computers	O
built	O
some	O
type	O
of	O
input	O
and	O
output	O
directly	O
into	O
the	O
control	B-General_Concept
unit	I-General_Concept
.	O
</s>
<s>
For	O
example	O
,	O
many	O
historic	O
computers	O
had	O
a	O
front	O
panel	O
with	O
switches	O
and	O
lights	O
directly	O
controlled	O
by	O
the	O
control	B-General_Concept
unit	I-General_Concept
.	O
</s>
<s>
In	O
later	O
production	O
computers	O
,	O
the	O
most	O
common	O
use	O
of	O
a	O
front	O
panel	O
was	O
to	O
enter	O
a	O
small	O
bootstrap	B-Operating_System
program	I-Operating_System
to	O
read	O
the	O
operating	O
system	O
from	O
disk	O
.	O
</s>
<s>
Most	O
PDP-8	B-Device
models	O
had	O
a	O
data	O
bus	O
designed	O
to	O
let	O
I/O	O
devices	O
borrow	O
the	O
control	B-General_Concept
unit	I-General_Concept
's	O
memory	O
read	O
and	O
write	O
logic	O
.	O
</s>
<s>
The	O
Xerox	B-Device
Alto	I-Device
had	O
a	O
multitasking	O
microprogrammable	O
control	B-General_Concept
unit	I-General_Concept
that	O
performed	O
almost	O
all	O
I/O	O
.	O
</s>
<s>
The	O
dual-thread	O
computer	O
was	O
run	O
by	O
the	O
two	O
lowest-priority	O
microthreads	O
.	O
</s>
<s>
To	O
handle	O
outside	O
events	O
,	O
the	O
microcontroller	O
had	O
microinterrupts	O
to	O
switch	O
threads	B-Operating_System
at	O
the	O
end	O
of	O
a	O
thread	B-Operating_System
's	O
cycle	O
,	O
e.g.	O
</s>
<s>
Thus	O
a	O
program	O
of	O
instructions	O
in	O
memory	O
will	O
cause	O
the	O
CU	O
to	O
configure	O
a	O
CPU	B-General_Concept
's	O
data	O
flows	O
to	O
manipulate	O
the	O
data	O
correctly	O
between	O
instructions	O
.	O
</s>
<s>
Hardwired	O
control	B-General_Concept
units	I-General_Concept
are	O
implemented	O
through	O
use	O
of	O
combinational	O
logic	O
units	O
,	O
featuring	O
a	O
finite	O
number	O
of	O
gates	O
that	O
can	O
generate	O
specific	O
results	O
based	O
on	O
the	O
instructions	O
that	O
were	O
used	O
to	O
invoke	O
those	O
responses	O
.	O
</s>
<s>
Hardwired	O
control	B-General_Concept
units	I-General_Concept
are	O
generally	O
faster	O
than	O
the	O
microprogrammed	O
designs	O
.	O
</s>
<s>
This	O
design	O
uses	O
a	O
fixed	O
architectureit	O
requires	O
changes	O
in	O
the	O
wiring	O
if	O
the	O
instruction	B-General_Concept
set	I-General_Concept
is	O
modified	O
or	O
changed	O
.	O
</s>
<s>
A	O
complex	O
instruction	B-General_Concept
set	I-General_Concept
can	O
overwhelm	O
a	O
designer	O
who	O
uses	O
ad	O
hoc	O
logic	O
design	O
.	O
</s>
<s>
Previously	O
,	O
control	B-General_Concept
units	I-General_Concept
for	O
CPUs	O
used	O
ad	O
hoc	O
logic	O
,	O
and	O
they	O
were	O
difficult	O
to	O
design	O
.	O
</s>
<s>
The	O
idea	O
of	O
microprogramming	O
was	O
introduced	O
by	O
Maurice	O
Wilkes	O
in	O
1951	O
as	O
an	O
intermediate	O
level	O
to	O
execute	O
computer	B-Application
program	I-Application
instructions	O
.	O
</s>
<s>
The	O
algorithm	O
for	O
the	O
microprogram	O
control	B-General_Concept
unit	I-General_Concept
,	O
unlike	O
the	O
hardwired	O
control	B-General_Concept
unit	I-General_Concept
,	O
is	O
usually	O
specified	O
by	O
flowchart	B-Language
description	O
.	O
</s>
<s>
The	O
main	O
advantage	O
of	O
a	O
microprogrammed	O
control	B-General_Concept
unit	I-General_Concept
is	O
the	O
simplicity	O
of	O
its	O
structure	O
.	O
</s>
<s>
This	O
is	O
a	O
logical	O
truth	O
table	O
,	O
that	O
translates	O
a	O
microcode	O
address	O
into	O
the	O
control	B-General_Concept
unit	I-General_Concept
outputs	O
.	O
</s>
<s>
This	O
truth	O
table	O
can	O
be	O
fed	O
to	O
a	O
computer	B-Application
program	I-Application
that	O
produces	O
optimized	O
electronic	O
logic	O
.	O
</s>
<s>
The	O
resulting	O
control	B-General_Concept
unit	I-General_Concept
is	O
almost	O
as	O
easy	O
to	O
design	O
as	O
microprogramming	O
,	O
but	O
it	O
has	O
the	O
fast	O
speed	O
and	O
low	O
number	O
of	O
logic	O
elements	O
of	O
a	O
hard	O
wired	O
control	B-General_Concept
unit	I-General_Concept
.	O
</s>
<s>
The	O
practical	O
result	O
resembles	O
a	O
Mealy	B-General_Concept
machine	I-General_Concept
or	O
Richards	B-Application
controller	I-Application
.	O
</s>
