<s>
In	O
computer	B-General_Concept
architecture	I-General_Concept
,	O
</s>
<s>
a	O
control	B-Architecture
bus	I-Architecture
is	O
part	O
of	O
the	O
system	B-Architecture
bus	I-Architecture
and	O
is	O
used	O
by	O
CPUs	O
for	O
communicating	O
with	O
other	O
devices	O
within	O
the	O
computer	O
.	O
</s>
<s>
While	O
the	O
address	B-Architecture
bus	I-Architecture
carries	O
the	O
information	O
about	O
the	O
device	O
with	O
which	O
the	O
CPU	B-General_Concept
is	O
communicating	O
and	O
the	O
data	B-General_Concept
bus	I-General_Concept
carries	O
the	O
actual	O
data	O
being	O
processed	O
,	O
the	O
control	B-Architecture
bus	I-Architecture
carries	O
commands	O
from	O
the	O
CPU	B-General_Concept
and	O
returns	O
status	O
signals	O
from	O
the	O
devices	O
.	O
</s>
<s>
The	O
number	O
and	O
type	O
of	O
lines	O
in	O
a	O
control	B-Architecture
bus	I-Architecture
varies	O
but	O
there	O
are	O
basic	O
lines	O
common	O
to	O
all	O
microprocessors	O
,	O
such	O
as	O
:	O
</s>
<s>
A	O
single	O
line	O
that	O
when	O
active	O
(	O
logic	O
zero	O
)	O
indicates	O
the	O
device	O
is	O
being	O
read	O
by	O
the	O
CPU	B-General_Concept
.	O
</s>
<s>
A	O
single	O
line	O
that	O
when	O
active	O
(	O
logic	O
zero	O
)	O
indicates	O
the	O
device	O
is	O
being	O
written	O
by	O
the	O
CPU	B-General_Concept
.	O
</s>
<s>
The	O
RD	O
and	O
WR	O
signals	O
of	O
the	O
control	B-Architecture
bus	I-Architecture
control	O
the	O
reading	O
or	O
writing	O
of	O
RAM	O
,	O
avoiding	O
bus	B-Architecture
contention	I-Architecture
on	O
the	O
data	B-General_Concept
bus	I-General_Concept
.	O
</s>
<s>
Transfer	O
ACK	B-Protocol
(	O
"	O
acknowledgement	B-Protocol
"	O
)	O
.	O
</s>
<s>
Indicates	O
the	O
CPU	B-General_Concept
has	O
granted	O
access	O
to	O
the	O
bus	O
.	O
</s>
<s>
Interrupt	B-Application
request	O
(	O
IRQ	O
)	O
.	O
</s>
<s>
A	O
device	O
with	O
lower	O
priority	O
is	O
requesting	O
access	O
to	O
the	O
CPU	B-General_Concept
.	O
</s>
<s>
The	O
signal	O
on	O
this	O
line	O
is	O
used	O
to	O
synchronize	O
data	O
between	O
the	O
CPU	B-General_Concept
and	O
a	O
device	O
.	O
</s>
<s>
Reset	B-General_Concept
.	O
</s>
<s>
If	O
this	O
line	O
is	O
active	O
,	O
the	O
CPU	B-General_Concept
will	O
perform	O
a	O
hard	O
reboot	O
.	O
</s>
<s>
Systems	O
that	O
have	O
more	O
than	O
one	O
bus	B-Architecture
master	I-Architecture
have	O
additional	O
control	B-Architecture
bus	I-Architecture
signals	O
that	O
control	O
which	O
bus	B-Architecture
master	I-Architecture
drives	O
the	O
address	B-Architecture
bus	I-Architecture
,	O
avoiding	O
bus	B-Architecture
contention	I-Architecture
on	O
the	O
address	B-Architecture
bus	I-Architecture
.	O
</s>
