<s>
Software/Configware	O
Co-Compilation	O
is	O
used	O
for	O
reconfigurable	B-Architecture
computing	I-Architecture
to	O
generate	O
the	O
code	O
for	O
both	O
,	O
an	O
instruction-stream-based	O
microprocessor	B-Architecture
and	O
a	O
reconfigurable	O
accelerator	O
interfaced	O
to	O
it	O
.	O
</s>
<s>
Such	O
a	O
co-compiler	O
(	O
see	O
figure	O
)	O
has	O
a	O
partitioner	O
which	O
accepts	O
input	O
from	O
a	O
high	O
level	O
language	O
source	O
,	O
such	O
as	O
,	O
for	O
instance	O
a	O
programming	O
language	O
,	O
or	O
the	O
output	O
from	O
tools	O
like	O
MATLAB	B-Language
,	O
and	O
automatically	O
partitions	O
it	O
into	O
parallelizable	O
parts	O
suitable	O
for	O
the	O
reconfigurable	O
accelerator	O
and	O
the	O
rest	O
for	O
running	O
on	O
the	O
microprocessor	B-Architecture
.	O
</s>
<s>
By	O
loop	O
transformations	O
the	O
partitioner	O
converts	O
the	O
parallelizable	O
parts	O
into	O
a	O
configware	O
source	O
,	O
which	O
is	O
compiled	O
by	O
a	O
Configware	O
Compiler	O
generating	O
configware	O
code	O
for	O
the	O
configuration	O
of	O
the	O
reconfigurable	O
accelerator	O
like	O
,	O
for	O
instance	O
an	O
FPGA	O
,	O
or	O
a	O
coarse-grained	B-Operating_System
reconfigurable	O
array	O
,	O
and	O
flowware	O
code	O
for	O
organizing	O
the	O
data	O
streams	O
going	O
from	O
and	O
to	O
the	O
accelerator	O
.	O
</s>
