<s>
In	O
computer	O
engineering	O
,	O
computer	B-General_Concept
architecture	I-General_Concept
is	O
a	O
description	O
of	O
the	O
structure	O
of	O
a	O
computer	O
system	O
made	O
from	O
component	O
parts	O
.	O
</s>
<s>
At	O
a	O
more	O
detailed	O
level	O
,	O
the	O
description	O
may	O
include	O
the	O
instruction	B-General_Concept
set	I-General_Concept
architecture	I-General_Concept
design	O
,	O
microarchitecture	B-General_Concept
design	O
,	O
logic	O
design	O
,	O
and	O
implementation	O
.	O
</s>
<s>
The	O
first	O
documented	O
computer	B-General_Concept
architecture	I-General_Concept
was	O
in	O
the	O
correspondence	O
between	O
Charles	O
Babbage	O
and	O
Ada	B-General_Concept
Lovelace	I-General_Concept
,	O
describing	O
the	B-Device
analytical	I-Device
engine	I-Device
.	O
</s>
<s>
While	O
building	O
the	O
computer	O
Z1	B-Device
in	O
1936	O
,	O
Konrad	O
Zuse	O
described	O
in	O
two	O
patent	O
applications	O
for	O
his	O
future	O
projects	O
that	O
machine	B-Language
instructions	I-Language
could	O
be	O
stored	O
in	O
the	O
same	O
storage	O
used	O
for	O
data	O
,	O
i.e.	O
,	O
the	O
stored-program	O
concept	O
.	O
</s>
<s>
Alan	O
Turing	O
's	O
more	O
detailed	O
Proposed	O
Electronic	O
Calculator	O
for	O
the	O
Automatic	B-Device
Computing	I-Device
Engine	I-Device
,	O
also	O
1945	O
and	O
which	O
cited	O
John	O
von	O
Neumann	O
's	O
paper	O
.	O
</s>
<s>
Johnson	O
had	O
the	O
opportunity	O
to	O
write	O
a	O
proprietary	O
research	O
communication	O
about	O
the	O
Stretch	B-Device
,	O
an	O
IBM-developed	O
supercomputer	B-Architecture
for	O
Los	O
Alamos	O
National	O
Laboratory	O
(	O
at	O
the	O
time	O
known	O
as	O
Los	O
Alamos	O
Scientific	O
Laboratory	O
)	O
.	O
</s>
<s>
To	O
describe	O
the	O
level	O
of	O
detail	O
for	O
discussing	O
the	O
luxuriously	O
embellished	O
computer	O
,	O
he	O
noted	O
that	O
his	O
description	O
of	O
formats	O
,	O
instruction	O
types	O
,	O
hardware	B-Architecture
parameters	O
,	O
and	O
speed	O
enhancements	O
were	O
at	O
the	O
level	O
of	O
"	O
system	O
architecture	O
"	O
,	O
a	O
term	O
that	O
seemed	O
more	O
useful	O
than	O
"	O
machine	O
organization	O
"	O
.	O
</s>
<s>
Subsequently	O
,	O
Brooks	O
,	O
a	O
Stretch	B-Device
designer	O
,	O
opened	O
Chapter	O
2	O
of	O
a	O
book	O
called	O
Planning	O
a	O
Computer	O
System	O
:	O
Project	O
Stretch	B-Device
by	O
stating	O
,	O
"	O
Computer	B-General_Concept
architecture	I-General_Concept
,	O
like	O
other	O
architecture	O
,	O
is	O
the	O
art	O
of	O
determining	O
the	O
needs	O
of	O
the	O
user	O
of	O
a	O
structure	O
and	O
then	O
designing	O
to	O
meet	O
those	O
needs	O
as	O
effectively	O
as	O
possible	O
within	O
economic	O
and	O
technological	O
constraints.	O
"	O
</s>
<s>
Brooks	O
went	O
on	O
to	O
help	O
develop	O
the	O
IBM	B-Application
System/360	I-Application
(	O
now	O
called	O
the	O
IBM	O
zSeries	O
)	O
line	O
of	O
computers	O
,	O
in	O
which	O
"	O
architecture	O
"	O
became	O
a	O
noun	O
defining	O
"	O
what	O
the	O
user	O
needs	O
to	O
know	O
"	O
.	O
</s>
<s>
The	O
earliest	O
computer	B-General_Concept
architectures	I-General_Concept
were	O
designed	O
on	O
paper	O
and	O
then	O
directly	O
built	O
into	O
the	O
final	O
hardware	B-Architecture
form	O
.	O
</s>
<s>
Later	O
,	O
computer	B-General_Concept
architecture	I-General_Concept
prototypes	O
were	O
physically	O
built	O
in	O
the	O
form	O
of	O
a	O
transistor	B-General_Concept
–	I-General_Concept
transistor	I-General_Concept
logic	I-General_Concept
(	O
TTL	B-General_Concept
)	O
computer	O
—	O
such	O
as	O
the	O
prototypes	O
of	O
the	O
6800	O
and	O
the	O
PA-RISC	B-Device
—	O
tested	O
,	O
and	O
tweaked	O
,	O
before	O
committing	O
to	O
the	O
final	O
hardware	B-Architecture
form	O
.	O
</s>
<s>
As	O
of	O
the	O
1990s	O
,	O
new	O
computer	B-General_Concept
architectures	I-General_Concept
are	O
typically	O
"	O
built	O
"	O
,	O
tested	O
,	O
and	O
tweaked	O
—	O
inside	O
some	O
other	O
computer	B-General_Concept
architecture	I-General_Concept
in	O
a	O
computer	B-Application
architecture	I-Application
simulator	I-Application
;	O
or	O
inside	O
a	O
FPGA	B-Architecture
as	O
a	O
soft	B-Device
microprocessor	I-Device
;	O
or	O
both	O
—	O
before	O
committing	O
to	O
the	O
final	O
hardware	B-Architecture
form	O
.	O
</s>
<s>
The	O
discipline	O
of	O
computer	B-General_Concept
architecture	I-General_Concept
has	O
three	O
main	O
subcategories	O
:	O
</s>
<s>
Instruction	B-General_Concept
set	I-General_Concept
architecture	I-General_Concept
(	O
ISA	O
)	O
:	O
defines	O
the	O
machine	B-Language
code	I-Language
that	O
a	O
processor	B-General_Concept
reads	O
and	O
acts	O
upon	O
as	O
well	O
as	O
the	O
word	O
size	O
,	O
memory	B-Language
address	I-Language
modes	I-Language
,	O
processor	B-General_Concept
registers	I-General_Concept
,	O
and	O
data	O
type	O
.	O
</s>
<s>
Microarchitecture	B-General_Concept
:	O
also	O
known	O
as	O
"	O
computer	B-General_Concept
organization	I-General_Concept
"	O
,	O
this	O
describes	O
how	O
a	O
particular	O
processor	B-General_Concept
will	O
implement	O
the	O
ISA	O
.	O
</s>
<s>
The	O
size	O
of	O
a	O
computer	O
's	O
CPU	B-General_Concept
cache	I-General_Concept
for	O
instance	O
,	O
is	O
an	O
issue	O
that	O
generally	O
has	O
nothing	O
to	O
do	O
with	O
the	O
ISA	O
.	O
</s>
<s>
Systems	O
design	O
:	O
includes	O
all	O
of	O
the	O
other	O
hardware	B-Architecture
components	O
within	O
a	O
computing	O
system	O
,	O
such	O
as	O
data	O
processing	O
other	O
than	O
the	O
CPU	B-General_Concept
(	O
e.g.	O
,	O
direct	B-General_Concept
memory	I-General_Concept
access	I-General_Concept
)	O
,	O
virtualization	B-General_Concept
,	O
and	O
multiprocessing	B-Operating_System
.	O
</s>
<s>
There	O
are	O
other	O
technologies	O
in	O
computer	B-General_Concept
architecture	I-General_Concept
.	O
</s>
<s>
The	O
following	O
technologies	O
are	O
used	O
in	O
bigger	O
companies	O
like	O
Intel	O
,	O
and	O
were	O
estimated	O
in	O
2002	O
to	O
count	O
for	O
1%	O
of	O
all	O
of	O
computer	B-General_Concept
architecture	I-General_Concept
:	O
</s>
<s>
Assembly	O
instruction	B-General_Concept
set	I-General_Concept
architecture	I-General_Concept
:	O
A	O
smart	O
assembler	B-Language
may	O
convert	O
an	O
abstract	O
assembly	B-Language
language	I-Language
common	O
to	O
a	O
group	O
of	O
machines	O
into	O
slightly	O
different	O
machine	B-Language
language	I-Language
for	O
different	O
implementations	O
.	O
</s>
<s>
Programmer-visible	O
macroarchitecture	O
:	O
higher-level	O
language	O
tools	O
such	O
as	O
compilers	B-Language
may	O
define	O
a	O
consistent	O
interface	O
or	O
contract	O
to	O
programmers	B-Application
using	O
them	O
,	O
abstracting	O
differences	O
between	O
underlying	O
ISA	O
,	O
UISA	O
,	O
and	O
microarchitectures	B-General_Concept
.	O
</s>
<s>
For	O
example	O
,	O
the	O
C	B-Language
,	O
C++	B-Language
,	O
or	O
Java	B-Language
standards	O
define	O
different	O
programmer-visible	O
macroarchitectures	O
.	O
</s>
<s>
Microcode	B-Device
:	O
microcode	B-Device
is	O
software	O
that	O
translates	O
instructions	O
to	O
run	O
on	O
a	O
chip	O
.	O
</s>
<s>
It	O
acts	O
like	O
a	O
wrapper	O
around	O
the	O
hardware	B-Architecture
,	O
presenting	O
a	O
preferred	O
version	O
of	O
the	O
hardware	B-Architecture
's	O
instruction	B-General_Concept
set	I-General_Concept
interface	O
.	O
</s>
<s>
A	O
new	O
improved	O
version	O
of	O
the	O
chip	O
can	O
use	O
microcode	B-Device
to	O
present	O
the	O
exact	O
same	O
instruction	B-General_Concept
set	I-General_Concept
as	O
the	O
old	O
chip	O
version	O
,	O
so	O
all	O
software	O
targeting	O
that	O
instruction	B-General_Concept
set	I-General_Concept
will	O
run	O
on	O
the	O
new	O
chip	O
without	O
needing	O
changes	O
.	O
</s>
<s>
Microcode	B-Device
can	O
present	O
a	O
variety	O
of	O
instruction	B-General_Concept
sets	I-General_Concept
for	O
the	O
same	O
underlying	O
chip	O
,	O
allowing	O
it	O
to	O
run	O
a	O
wider	O
variety	O
of	O
software	O
.	O
</s>
<s>
UISA	O
:	O
User	O
Instruction	B-General_Concept
Set	I-General_Concept
Architecture	I-General_Concept
,	O
refers	O
to	O
one	O
of	O
three	O
subsets	O
of	O
the	O
RISC	B-Architecture
CPU	B-Language
instructions	I-Language
provided	O
by	O
PowerPC	B-Architecture
RISC	B-Architecture
Processors	I-Architecture
.	O
</s>
<s>
The	O
UISA	O
subset	O
,	O
are	O
those	O
RISC	B-Architecture
instructions	O
of	O
interest	O
to	O
application	B-Application
developers	I-Application
.	O
</s>
<s>
The	O
other	O
two	O
subsets	O
are	O
VEA	O
(	O
Virtual	O
Environment	O
Architecture	O
)	O
instructions	O
used	O
by	O
virtualization	B-General_Concept
system	O
developers	B-Application
,	O
and	O
OEA	O
(	O
Operating	O
Environment	O
Architecture	O
)	O
used	O
by	O
Operation	O
System	O
developers	B-Application
.	O
</s>
<s>
Pin	O
architecture	O
:	O
The	O
hardware	B-Architecture
functions	O
that	O
a	O
microprocessor	B-Architecture
should	O
provide	O
to	O
a	O
hardware	B-Architecture
platform	O
,	O
e.g.	O
,	O
the	O
x86	B-Operating_System
pins	O
A20M	O
,	O
FERR/IGNNE	O
or	O
FLUSH	O
.	O
</s>
<s>
Also	O
,	O
messages	O
that	O
the	O
processor	B-General_Concept
should	O
emit	O
so	O
that	O
external	O
caches	B-General_Concept
can	O
be	O
invalidated	O
(	O
emptied	O
)	O
.	O
</s>
<s>
Pin	O
architecture	O
functions	O
are	O
more	O
flexible	O
than	O
ISA	O
functions	O
because	O
external	O
hardware	B-Architecture
can	O
adapt	O
to	O
new	O
encodings	O
,	O
or	O
change	O
from	O
a	O
pin	O
to	O
a	O
message	O
.	O
</s>
<s>
Computer	B-General_Concept
architecture	I-General_Concept
is	O
concerned	O
with	O
balancing	O
the	O
performance	O
,	O
efficiency	O
,	O
cost	O
,	O
and	O
reliability	O
of	O
a	O
computer	O
system	O
.	O
</s>
<s>
The	O
case	O
of	O
instruction	B-General_Concept
set	I-General_Concept
architecture	I-General_Concept
can	O
be	O
used	O
to	O
illustrate	O
the	O
balance	O
of	O
these	O
competing	O
factors	O
.	O
</s>
<s>
More	O
complex	O
instruction	B-General_Concept
sets	I-General_Concept
enable	O
programmers	B-Application
to	O
write	O
more	O
space	O
efficient	O
programs	O
,	O
since	O
a	O
single	O
instruction	O
can	O
encode	O
some	O
higher-level	O
abstraction	O
(	O
such	O
as	O
the	O
x86	B-Operating_System
Loop	O
instruction	O
)	O
.	O
</s>
<s>
However	O
,	O
longer	O
and	O
more	O
complex	O
instructions	O
take	O
longer	O
for	O
the	O
processor	B-General_Concept
to	O
decode	O
and	O
can	O
be	O
more	O
costly	O
to	O
implement	O
effectively	O
.	O
</s>
<s>
The	O
increased	O
complexity	O
from	O
a	O
large	O
instruction	B-General_Concept
set	I-General_Concept
also	O
creates	O
more	O
room	O
for	O
unreliability	O
when	O
instructions	O
interact	O
in	O
unexpected	O
ways	O
.	O
</s>
<s>
Optimization	O
of	O
the	O
design	O
requires	O
familiarity	O
with	O
compilers	B-Language
,	O
operating	O
systems	O
to	O
logic	O
design	O
,	O
and	O
packaging	O
.	O
</s>
<s>
An	O
instruction	B-General_Concept
set	I-General_Concept
architecture	I-General_Concept
(	O
ISA	O
)	O
is	O
the	O
interface	O
between	O
the	O
computer	O
's	O
software	O
and	O
hardware	B-Architecture
and	O
also	O
can	O
be	O
viewed	O
as	O
the	O
programmer	B-Application
's	O
view	O
of	O
the	O
machine	O
.	O
</s>
<s>
Computers	O
do	O
not	O
understand	O
high-level	B-Language
programming	I-Language
languages	I-Language
such	O
as	O
Java	B-Language
,	O
C++	B-Language
,	O
or	O
most	O
programming	O
languages	O
used	O
.	O
</s>
<s>
A	O
processor	B-General_Concept
only	O
understands	O
instructions	O
encoded	O
in	O
some	O
numerical	O
fashion	O
,	O
usually	O
as	O
binary	O
numbers	O
.	O
</s>
<s>
Software	O
tools	O
,	O
such	O
as	O
compilers	B-Language
,	O
translate	O
those	O
high	B-Language
level	I-Language
languages	I-Language
into	O
instructions	O
that	O
the	O
processor	B-General_Concept
can	O
understand	O
.	O
</s>
<s>
Besides	O
instructions	O
,	O
the	O
ISA	O
defines	O
items	O
in	O
the	O
computer	O
that	O
are	O
available	O
to	O
a	O
programe.g.	O
,	O
data	O
types	O
,	O
registers	B-General_Concept
,	O
addressing	B-Language
modes	I-Language
,	O
and	O
memory	O
.	O
</s>
<s>
Instructions	O
locate	O
these	O
available	O
items	O
with	O
register	O
indexes	O
(	O
or	O
names	O
)	O
and	O
memory	O
addressing	B-Language
modes	I-Language
.	O
</s>
<s>
The	O
names	O
can	O
be	O
recognized	O
by	O
a	O
software	O
development	O
tool	O
called	O
an	O
assembler	B-Language
.	O
</s>
<s>
An	O
assembler	B-Language
is	O
a	O
computer	O
program	O
that	O
translates	O
a	O
human-readable	O
form	O
of	O
the	O
ISA	O
into	O
a	O
computer-readable	O
form	O
.	O
</s>
<s>
Disassemblers	O
are	O
also	O
widely	O
available	O
,	O
usually	O
in	O
debuggers	B-Application
and	O
software	O
programs	O
to	O
isolate	O
and	O
correct	O
malfunctions	O
in	O
binary	O
computer	O
programs	O
.	O
</s>
<s>
A	O
good	O
ISA	O
compromises	O
between	O
programmer	B-Application
convenience	O
(	O
how	O
easy	O
the	O
code	O
is	O
to	O
understand	O
)	O
,	O
size	O
of	O
the	O
code	O
(	O
how	O
much	O
code	O
is	O
required	O
to	O
do	O
a	O
specific	O
action	O
)	O
,	O
cost	O
of	O
the	O
computer	O
to	O
interpret	O
the	O
instructions	O
(	O
more	O
complexity	O
means	O
more	O
hardware	B-Architecture
needed	O
to	O
decode	O
and	O
execute	O
the	O
instructions	O
)	O
,	O
and	O
speed	O
of	O
the	O
computer	O
(	O
with	O
more	O
complex	O
decoding	O
hardware	B-Architecture
comes	O
longer	O
decode	O
time	O
)	O
.	O
</s>
<s>
During	O
design	O
emulation	B-Application
,	O
emulators	B-Application
can	O
run	O
programs	O
written	O
in	O
a	O
proposed	O
instruction	B-General_Concept
set	I-General_Concept
.	O
</s>
<s>
Modern	O
emulators	B-Application
can	O
measure	O
size	O
,	O
cost	O
,	O
and	O
speed	O
to	O
determine	O
whether	O
a	O
particular	O
ISA	O
is	O
meeting	O
its	O
goals	O
.	O
</s>
<s>
Computer	B-General_Concept
organization	I-General_Concept
helps	O
optimize	O
performance-based	O
products	O
.	O
</s>
<s>
Computer	B-General_Concept
organization	I-General_Concept
also	O
helps	O
plan	O
the	O
selection	O
of	O
a	O
processor	B-General_Concept
for	O
a	O
particular	O
project	O
.	O
</s>
<s>
For	O
example	O
,	O
a	O
computer	O
capable	O
of	O
running	O
a	O
virtual	O
machine	O
needs	O
virtual	B-Architecture
memory	I-Architecture
hardware	B-Architecture
so	O
that	O
the	O
memory	O
of	O
different	O
virtual	O
computers	O
can	O
be	O
kept	O
separated	O
.	O
</s>
<s>
Computer	B-General_Concept
organization	I-General_Concept
and	O
features	O
also	O
affect	O
power	O
consumption	O
and	O
processor	B-General_Concept
cost	O
.	O
</s>
<s>
Once	O
an	O
instruction	B-General_Concept
set	I-General_Concept
and	O
micro-architecture	B-General_Concept
have	O
been	O
designed	O
,	O
a	O
practical	O
machine	O
must	O
be	O
developed	O
.	O
</s>
<s>
Implementation	O
is	O
usually	O
not	O
considered	O
architectural	O
design	O
,	O
but	O
rather	O
hardware	B-General_Concept
design	I-General_Concept
engineering	O
.	O
</s>
<s>
Circuit	O
implementation	O
does	O
transistor-level	O
designs	O
of	O
basic	O
elements	O
(	O
e.g.	O
,	O
gates	O
,	O
multiplexers	B-Protocol
,	O
latches	B-General_Concept
)	O
as	O
well	O
as	O
of	O
some	O
larger	O
blocks	O
(	O
ALUs	O
,	O
caches	B-General_Concept
etc	O
.	O
)	O
</s>
<s>
Once	O
the	O
design	O
validation	O
process	O
starts	O
,	O
the	O
design	O
at	O
the	O
logic	O
level	O
are	O
tested	O
using	O
logic	O
emulators	B-Application
.	O
</s>
<s>
So	O
,	O
after	O
making	O
corrections	O
based	O
on	O
the	O
first	O
test	O
,	O
prototypes	O
are	O
constructed	O
using	O
Field-Programmable	O
Gate-Arrays	O
(	O
FPGAs	B-Architecture
)	O
.	O
</s>
<s>
For	O
CPUs	O
,	O
the	O
entire	O
implementation	O
process	O
is	O
organized	O
differently	O
and	O
is	O
often	O
referred	O
to	O
as	O
CPU	B-General_Concept
design	I-General_Concept
.	O
</s>
<s>
Computer	B-General_Concept
architectures	I-General_Concept
usually	O
trade	O
off	O
standards	O
,	O
power	O
versus	O
performance	O
,	O
cost	O
,	O
memory	O
capacity	O
,	O
latency	O
(	O
latency	O
is	O
the	O
amount	O
of	O
time	O
that	O
it	O
takes	O
for	O
information	O
from	O
one	O
node	O
to	O
travel	O
to	O
the	O
source	O
)	O
and	O
throughput	O
.	O
</s>
<s>
Superscalar	B-General_Concept
processors	I-General_Concept
may	O
reach	O
three	O
to	O
five	O
IPC	O
by	O
executing	O
several	O
instructions	O
per	O
clock	O
cycle	O
.	O
</s>
<s>
The	O
"	O
instruction	O
"	O
in	O
the	O
standard	O
measurements	O
is	O
not	O
a	O
count	O
of	O
the	O
ISA	O
's	O
machine-language	O
instructions	O
,	O
but	O
a	O
unit	O
of	O
measurement	O
,	O
usually	O
based	O
on	O
the	O
speed	O
of	O
the	O
VAX	B-Device
computer	B-General_Concept
architecture	I-General_Concept
.	O
</s>
<s>
This	O
refers	O
to	O
the	O
cycles	O
per	O
second	O
of	O
the	O
main	O
clock	O
of	O
the	O
CPU	B-General_Concept
.	O
</s>
<s>
Other	O
factors	O
influence	O
speed	O
,	O
such	O
as	O
the	O
mix	O
of	O
functional	B-General_Concept
units	I-General_Concept
,	O
bus	B-General_Concept
speeds	O
,	O
available	O
memory	O
,	O
and	O
the	O
type	O
and	O
order	O
of	O
instructions	O
in	O
the	O
programs	O
.	O
</s>
<s>
Interrupt	B-General_Concept
latency	I-General_Concept
is	O
the	O
guaranteed	O
maximum	O
response	O
time	O
of	O
the	O
system	O
to	O
an	O
electronic	O
event	O
(	O
like	O
when	O
the	O
disk	O
drive	O
finishes	O
moving	O
some	O
data	O
)	O
.	O
</s>
<s>
Performance	O
is	O
affected	O
by	O
a	O
very	O
wide	O
range	O
of	O
design	O
choices	O
—	O
for	O
example	O
,	O
pipelining	B-General_Concept
a	O
processor	B-General_Concept
usually	O
makes	O
latency	O
worse	O
,	O
but	O
makes	O
throughput	O
better	O
.	O
</s>
<s>
Computers	O
that	O
control	O
machinery	O
usually	O
need	O
low	O
interrupt	B-General_Concept
latencies	I-General_Concept
.	O
</s>
<s>
These	O
computers	O
operate	O
in	O
a	O
real-time	B-General_Concept
environment	O
and	O
fail	O
if	O
an	O
operation	O
is	O
not	O
completed	O
in	O
a	O
specified	O
amount	O
of	O
time	O
.	O
</s>
<s>
Furthermore	O
,	O
designers	O
may	O
target	O
and	O
add	O
special	O
features	O
to	O
their	O
products	O
,	O
through	O
hardware	B-Architecture
or	O
software	O
,	O
that	O
permit	O
a	O
specific	O
benchmark	O
to	O
execute	O
quickly	O
but	O
do	O
not	O
offer	O
similar	O
advantages	O
to	O
general	O
tasks	O
.	O
</s>
<s>
The	O
typical	O
measurement	O
when	O
referring	O
to	O
power	O
consumption	O
in	O
computer	B-General_Concept
architecture	I-General_Concept
is	O
MIPS/W	O
(	O
millions	O
of	O
instructions	O
per	O
second	O
per	O
watt	O
)	O
.	O
</s>
<s>
Modern	O
circuits	O
have	O
less	O
power	O
required	O
per	O
transistor	B-Application
as	O
the	O
number	O
of	O
transistors	B-Application
per	O
chip	O
grows	O
.	O
</s>
<s>
This	O
is	O
because	O
each	O
transistor	B-Application
that	O
is	O
put	O
in	O
a	O
new	O
chip	O
requires	O
its	O
own	O
power	O
supply	O
and	O
requires	O
new	O
pathways	O
to	O
be	O
built	O
to	O
power	O
it	O
.	O
</s>
<s>
However	O
,	O
the	O
number	O
of	O
transistors	B-Application
per	O
chip	O
is	O
starting	O
to	O
increase	O
at	O
a	O
slower	O
rate	O
.	O
</s>
<s>
Therefore	O
,	O
power	O
efficiency	O
is	O
starting	O
to	O
become	O
as	O
important	O
,	O
if	O
not	O
more	O
important	O
than	O
fitting	O
more	O
and	O
more	O
transistors	B-Application
into	O
a	O
single	O
chip	O
.	O
</s>
<s>
Recent	O
processor	B-General_Concept
designs	I-General_Concept
have	O
shown	O
this	O
emphasis	O
as	O
they	O
put	O
more	O
focus	O
on	O
power	O
efficiency	O
rather	O
than	O
cramming	O
as	O
many	O
transistors	B-Application
into	O
a	O
single	O
chip	O
as	O
possible	O
.	O
</s>
<s>
This	O
change	O
in	O
focus	O
from	O
higher	O
clock	O
rates	O
to	O
power	O
consumption	O
and	O
miniaturization	O
can	O
be	O
shown	O
by	O
the	O
significant	O
reductions	O
in	O
power	O
consumption	O
,	O
as	O
much	O
as	O
50%	O
,	O
that	O
were	O
reported	O
by	O
Intel	O
in	O
their	O
release	O
of	O
the	O
Haswell	B-Device
microarchitecture	I-Device
;	O
where	O
they	O
dropped	O
their	O
power	O
consumption	O
benchmark	O
from	O
30	O
to	O
40	O
watts	O
down	O
to	O
10-20	O
watts	O
.	O
</s>
