<s>
Computational	B-Architecture
RAM	I-Architecture
(	O
C-RAM	O
)	O
is	O
random-access	B-Architecture
memory	I-Architecture
with	O
processing	B-General_Concept
elements	I-General_Concept
integrated	O
on	O
the	O
same	O
chip	O
.	O
</s>
<s>
This	O
enables	O
C-RAM	O
to	O
be	O
used	O
as	O
a	O
SIMD	B-Device
computer	O
.	O
</s>
<s>
It	O
also	O
can	O
be	O
used	O
to	O
more	O
efficiently	O
use	O
memory	B-General_Concept
bandwidth	O
within	O
a	O
memory	B-General_Concept
chip	O
.	O
</s>
<s>
The	O
most	O
influential	O
implementations	O
of	O
computational	B-Architecture
RAM	I-Architecture
came	O
from	O
The	B-Architecture
Berkeley	I-Architecture
IRAM	I-Architecture
Project	I-Architecture
.	O
</s>
<s>
Vector	O
IRAM	O
(	O
V-IRAM	O
)	O
combines	O
DRAM	O
with	O
a	O
vector	B-Operating_System
processor	I-Operating_System
integrated	O
on	O
the	O
same	O
chip	O
.	O
</s>
<s>
Reconfigurable	O
Architecture	O
DRAM	O
(	O
RADram	O
)	O
is	O
DRAM	O
with	O
reconfigurable	B-Architecture
computing	I-Architecture
FPGA	B-Architecture
logic	O
elements	O
integrated	O
on	O
the	O
same	O
chip	O
.	O
</s>
<s>
Some	O
embarrassingly	B-Operating_System
parallel	I-Operating_System
computational	O
problems	O
are	O
already	O
limited	O
by	O
the	O
von	O
Neumann	O
bottleneck	O
between	O
the	O
CPU	B-Device
and	O
the	O
DRAM	O
.	O
</s>
<s>
Some	O
researchers	O
expect	O
that	O
,	O
for	O
the	O
same	O
total	O
cost	O
,	O
a	O
machine	O
built	O
from	O
computational	B-Architecture
RAM	I-Architecture
will	O
run	O
orders	O
of	O
magnitude	O
faster	O
than	O
a	O
traditional	O
general-purpose	O
computer	O
on	O
these	O
kinds	O
of	O
problems	O
.	O
</s>
<s>
As	O
of	O
2011	O
,	O
the	O
"	O
DRAM	O
process	O
"	O
(	O
few	O
layers	O
;	O
optimized	O
for	O
high	O
capacitance	O
)	O
and	O
the	O
"	O
CPU	B-Device
process	O
"	O
(	O
optimized	O
for	O
high	O
frequency	O
;	O
typically	O
twice	O
as	O
many	O
BEOL	B-Algorithm
layers	O
as	O
DRAM	O
;	O
since	O
each	O
additional	O
layer	O
reduces	O
yield	O
and	O
increases	O
manufacturing	O
cost	O
,	O
such	O
chips	O
are	O
relatively	O
expensive	O
per	O
square	O
millimeter	O
compared	O
to	O
DRAM	O
)	O
is	O
distinct	O
enough	O
that	O
there	O
are	O
three	O
approaches	O
to	O
computational	B-Architecture
RAM	I-Architecture
:	O
</s>
<s>
starting	O
with	O
a	O
CPU-optimized	O
process	O
and	O
a	O
device	O
that	O
uses	O
much	O
embedded	O
SRAM	O
,	O
add	O
an	O
additional	O
process	O
step	O
(	O
making	O
it	O
even	O
more	O
expensive	O
per	O
square	O
millimeter	O
)	O
to	O
allow	O
replacing	O
the	O
embedded	O
SRAM	O
with	O
embedded	O
DRAM	O
(	O
eDRAM	O
)	O
,	O
giving	O
≈3x	O
area	O
savings	O
on	O
the	O
SRAM	O
areas	O
(	O
and	O
so	O
lowering	O
net	O
cost	O
per	O
chip	O
)	O
.	O
</s>
<s>
starting	O
with	O
a	O
system	O
with	O
a	O
separate	O
CPU	B-Device
chip	O
and	O
DRAM	O
chip(s )	O
,	O
add	O
small	O
amounts	O
of	O
"	O
coprocessor	O
"	O
computational	O
ability	O
to	O
the	O
DRAM	O
,	O
working	O
within	O
the	O
limits	O
of	O
the	O
DRAM	O
process	O
and	O
adding	O
only	O
small	O
amounts	O
of	O
area	O
to	O
the	O
DRAM	O
,	O
to	O
do	O
things	O
that	O
would	O
otherwise	O
be	O
slowed	O
down	O
by	O
the	O
narrow	O
bottleneck	O
between	O
CPU	B-Device
and	O
DRAM	O
:	O
zero-fill	O
selected	O
areas	O
of	O
memory	B-General_Concept
,	O
copy	O
large	O
blocks	O
of	O
data	O
from	O
one	O
location	O
to	O
another	O
,	O
find	O
where	O
(	O
if	O
anywhere	O
)	O
a	O
given	O
byte	O
occurs	O
in	O
some	O
block	O
of	O
data	O
,	O
etc	O
.	O
</s>
<s>
The	O
resulting	O
system	O
—	O
the	O
unchanged	O
CPU	B-Device
chip	O
,	O
and	O
"	O
smart	O
DRAM	O
"	O
chip(s )	O
—	O
is	O
at	O
least	O
as	O
fast	O
as	O
the	O
original	O
system	O
,	O
and	O
potentially	O
slightly	O
lower	O
in	O
cost	O
.	O
</s>
<s>
starting	O
with	O
a	O
DRAM-optimized	O
process	O
,	O
tweak	O
the	O
process	O
to	O
make	O
it	O
slightly	O
more	O
like	O
the	O
"	O
CPU	B-Device
process	O
"	O
,	O
and	O
build	O
a	O
(	O
relatively	O
low-frequency	O
,	O
but	O
low-power	O
and	O
very	O
high	O
bandwidth	O
)	O
general-purpose	O
CPU	B-Device
within	O
the	O
limits	O
of	O
that	O
process	O
.	O
</s>
<s>
and	O
the	O
AT&T	B-General_Concept
DSP1	I-General_Concept
.	O
</s>
<s>
Because	O
a	O
memory	B-General_Concept
bus	O
to	O
off-chip	O
memory	B-General_Concept
has	O
many	O
times	O
the	O
capacitance	O
of	O
an	O
on-chip	O
memory	B-General_Concept
bus	O
,	O
a	O
system	O
with	O
separate	O
DRAM	O
and	O
CPU	B-Device
chips	O
can	O
have	O
several	O
times	O
the	O
energy	O
consumption	O
of	O
an	O
IRAM	O
system	O
with	O
the	O
same	O
computer	O
performance	O
.	O
</s>
<s>
computational	O
DRAM	O
is	O
expected	O
to	O
require	O
more	O
frequent	O
DRAM	B-General_Concept
refresh	I-General_Concept
.	O
</s>
<s>
A	O
processor-in-/near	O
-memory	O
(	O
PINM	O
)	O
refers	O
to	O
a	O
computer	B-Device
processor	I-Device
(	O
CPU	B-Device
)	O
tightly	O
coupled	O
to	O
memory	B-General_Concept
,	O
generally	O
on	O
the	O
same	O
silicon	O
chip	O
.	O
</s>
<s>
The	O
chief	O
goal	O
of	O
merging	O
the	O
processing	O
and	O
memory	B-General_Concept
components	O
in	O
this	O
way	O
is	O
to	O
reduce	O
memory	B-General_Concept
latency	I-General_Concept
and	O
increase	O
bandwidth	O
.	O
</s>
<s>
Much	O
of	O
the	O
complexity	O
(	O
and	O
hence	O
power	O
consumption	O
)	O
in	O
current	O
processors	O
stems	O
from	O
strategies	O
to	O
deal	O
with	O
avoiding	O
memory	B-General_Concept
stalls	O
.	O
</s>
<s>
In	O
the	O
1980s	O
,	O
a	O
tiny	O
CPU	B-Device
that	O
executed	O
FORTH	O
was	O
fabricated	O
into	O
a	O
DRAM	O
chip	O
to	O
improve	O
PUSH	O
and	O
POP	O
.	O
</s>
<s>
FORTH	O
is	O
a	O
stack-oriented	B-Language
programming	I-Language
language	I-Language
and	O
this	O
improved	O
its	O
efficiency	O
.	O
</s>
<s>
The	O
transputer	B-General_Concept
also	O
had	O
large	O
on	O
chip	O
memory	B-General_Concept
given	O
that	O
it	O
was	O
made	O
in	O
the	O
early	O
1980s	O
making	O
it	O
essentially	O
a	O
processor-in-memory	B-Architecture
.	O
</s>
<s>
Notable	O
PIM	O
projects	O
include	O
the	B-Architecture
Berkeley	I-Architecture
IRAM	I-Architecture
project	I-Architecture
(	O
IRAM	O
)	O
at	O
the	O
University	O
of	O
California	O
,	O
Berkeley	O
project	O
and	O
the	O
University	O
of	O
Notre	O
Dame	O
PIM	O
effort	O
.	O
</s>
<s>
DRAM-based	O
near-memory	O
and	O
in-memory	O
designs	O
can	O
be	O
categorized	O
into	O
four	O
groups	O
:	O
</s>
<s>
DIMM-level	O
approaches	O
place	O
the	O
processing	O
units	O
near	O
memory	B-General_Concept
chips	O
.	O
</s>
<s>
Bank-level	O
approaches	O
place	O
processing	O
units	O
inside	O
the	O
memory	B-General_Concept
layers	O
,	O
near	O
each	O
bank	O
.	O
</s>
