<s>
A	O
compressed	B-Architecture
instruction	I-Architecture
set	I-Architecture
,	O
or	O
simply	O
compressed	B-Architecture
instructions	I-Architecture
,	O
are	O
a	O
variation	O
on	O
a	O
microprocessor	B-Architecture
's	O
instruction	B-General_Concept
set	I-General_Concept
architecture	I-General_Concept
(	O
ISA	O
)	O
that	O
allows	O
instructions	O
to	O
be	O
represented	O
in	O
a	O
more	O
compact	O
format	O
.	O
</s>
<s>
In	O
most	O
real-world	O
examples	O
,	O
compressed	B-Architecture
instructions	I-Architecture
are	O
16	O
bits	O
long	O
in	O
a	O
processor	O
that	O
would	O
otherwise	O
use	O
32-bit	O
instructions	O
.	O
</s>
<s>
The	O
16-bit	O
ISA	O
is	O
a	O
subset	O
of	O
the	O
full	O
32-bit	O
ISA	O
,	O
not	O
a	O
separate	O
instruction	B-General_Concept
set	I-General_Concept
.	O
</s>
<s>
The	O
smaller	O
format	O
requires	O
some	O
tradeoffs	O
:	O
generally	O
,	O
there	O
are	O
fewer	O
instructions	O
available	O
,	O
and	O
fewer	O
processor	B-General_Concept
registers	I-General_Concept
can	O
be	O
used	O
.	O
</s>
<s>
The	O
concept	O
was	O
originally	O
introduced	O
by	O
Hitachi	O
as	O
a	O
way	O
to	O
improve	O
the	O
code	O
density	O
of	O
their	O
SuperH	O
RISC	B-Architecture
processor	I-Architecture
design	O
as	O
it	O
moved	O
from	O
16-bit	O
to	O
32-bit	O
instructions	O
in	O
the	O
SH-5	O
version	O
.	O
</s>
<s>
The	O
new	O
design	O
had	O
two	O
instruction	B-General_Concept
sets	I-General_Concept
,	O
one	O
giving	O
access	O
to	O
the	O
entire	O
ISA	O
of	O
the	O
new	O
design	O
,	O
and	O
a	O
smaller	O
16-bit	O
set	O
known	O
as	O
SHcompact	O
that	O
allowed	O
programs	O
to	O
run	O
in	O
smaller	O
amounts	O
of	O
main	O
memory	O
.	O
</s>
<s>
Today	O
the	O
advantage	O
is	O
that	O
it	O
reduces	O
the	O
number	O
of	O
accesses	O
to	O
main	O
memory	O
and	O
thereby	O
reduces	O
energy	O
use	O
in	O
mobile	B-Application
devices	I-Application
.	O
</s>
<s>
Similar	O
systems	O
are	O
found	O
in	O
MIPS16e	O
and	O
PowerPC	B-Architecture
VLE	O
.	O
</s>
<s>
The	O
original	O
patents	O
have	O
expired	O
and	O
the	O
concept	O
can	O
be	O
found	O
in	O
a	O
number	O
of	O
modern	O
designs	O
,	O
including	O
RISC-V	B-Device
,	O
which	O
was	O
designed	O
from	O
the	O
outset	O
to	O
use	O
it	O
.	O
</s>
<s>
The	O
introduction	O
of	O
64-bit	B-Device
computing	I-Device
has	O
led	O
to	O
the	O
term	O
no	O
longer	O
being	O
as	O
widely	O
used	O
;	O
these	O
processors	O
generally	O
use	O
32-bit	O
instructions	O
and	O
are	O
technically	O
a	O
form	O
of	O
compressed	O
ISA	O
,	O
but	O
as	O
they	O
are	O
mostly	O
modified	O
versions	O
of	O
an	O
older	O
ISA	O
from	O
a	O
32-bit	O
version	O
of	O
the	O
same	O
processor	O
family	O
;	O
there	O
is	O
no	O
real	O
compression	O
.	O
</s>
<s>
Microprocessors	B-Architecture
encode	O
their	O
instructions	O
as	O
a	O
series	O
of	O
bits	O
,	O
normally	O
divided	O
into	O
a	O
number	O
of	O
8-bit	O
bytes	B-Application
.	O
</s>
<s>
For	O
instance	O
,	O
in	O
the	O
MOS	B-General_Concept
6502	I-General_Concept
,	O
the	O
instruction	O
performs	O
binary	O
addition	O
between	O
an	O
operand	O
value	O
and	O
the	O
value	O
already	O
stored	O
in	O
the	O
accumulator	B-General_Concept
.	O
</s>
<s>
There	O
are	O
a	O
variety	O
of	O
places	O
the	O
processor	O
might	O
find	O
the	O
operand	O
;	O
it	O
might	O
be	O
located	O
in	O
main	O
memory	O
,	O
or	O
in	O
the	O
special	O
zero	B-General_Concept
page	I-General_Concept
,	O
or	O
be	O
an	O
explicit	O
constant	O
like	O
"	O
10	O
"	O
.	O
</s>
<s>
Each	O
of	O
these	O
variations	O
used	O
a	O
different	O
8-bit	O
instruction	O
,	O
or	O
opcode	B-Language
;	O
if	O
one	O
wanted	O
to	O
add	O
the	O
constant	O
10	O
to	O
the	O
accumulator	B-General_Concept
the	O
instruction	O
would	O
be	O
encoded	O
in	O
memory	O
as	O
,	O
with	O
$0A	O
being	O
hexadecimal	O
for	O
the	O
decimal	O
value	O
10	O
.	O
</s>
<s>
Note	O
that	O
the	O
second	O
instruction	O
requires	O
three	O
bytes	B-Application
because	O
the	O
memory	O
address	O
is	O
16	O
bits	O
long	O
.	O
</s>
<s>
Depending	O
on	O
the	O
instruction	O
,	O
it	O
might	O
use	O
one	O
,	O
two	O
,	O
or	O
three	O
bytes	B-Application
.	O
</s>
<s>
This	O
is	O
now	O
known	O
as	O
a	O
variable	O
length	O
instruction	B-General_Concept
set	I-General_Concept
,	O
although	O
that	O
term	O
was	O
not	O
common	O
at	O
the	O
time	O
as	O
most	O
processors	O
,	O
including	O
mainframes	B-Architecture
and	O
minicomputers	B-Architecture
,	O
normally	O
used	O
some	O
variation	O
of	O
this	O
concept	O
.	O
</s>
<s>
Even	O
in	O
the	O
late	O
1970s	O
,	O
as	O
microprocessors	B-Architecture
began	O
to	O
move	O
from	O
8-bit	O
formats	O
to	O
16	O
,	O
this	O
concept	O
remained	O
common	O
;	O
the	O
Intel	B-Device
8088	I-Device
continued	O
to	O
use	O
8-bit	O
opcodes	B-Language
which	O
could	O
be	O
followed	O
by	O
zero	O
to	O
six	O
additional	O
bytes	B-Application
depending	O
on	O
the	O
addressing	B-Language
mode	I-Language
.	O
</s>
<s>
It	O
was	O
during	O
the	O
move	O
to	O
32-bit	O
systems	O
,	O
and	O
especially	O
as	O
the	O
RISC	B-Architecture
concept	O
began	O
to	O
take	O
over	O
processor	O
design	O
,	O
that	O
variable	O
length	O
instructions	O
began	O
to	O
go	O
away	O
.	O
</s>
<s>
In	O
the	O
MIPS	B-Device
architecture	I-Device
,	O
for	O
instance	O
,	O
all	O
instructions	O
are	O
a	O
single	O
32-bit	O
value	O
,	O
with	O
a	O
6-bit	O
opcode	B-Language
in	O
the	O
most	O
significant	O
bits	O
and	O
the	O
remaining	O
26	O
bits	O
used	O
in	O
various	O
ways	O
representing	O
its	O
limited	O
set	O
of	O
addressing	B-Language
modes	I-Language
.	O
</s>
<s>
Most	O
RISC	B-Architecture
designs	O
are	O
similar	O
.	O
</s>
<s>
Moving	O
to	O
a	O
fixed-length	O
instruction	O
format	O
was	O
one	O
of	O
the	O
key	O
design	O
concepts	O
behind	O
the	O
performance	O
of	O
early	O
RISC	B-Architecture
designs	O
;	O
in	O
earlier	O
systems	O
the	O
instruction	O
might	O
take	O
one	O
to	O
six	O
memory	O
cycles	O
to	O
read	O
,	O
requiring	O
wiring	O
between	O
various	O
parts	O
of	O
the	O
logic	O
to	O
ensure	O
the	O
processor	O
did	O
n't	O
attempt	O
to	O
perform	O
the	O
instruction	O
before	O
the	O
data	O
was	O
ready	O
.	O
</s>
<s>
In	O
RISC	B-Architecture
designs	O
,	O
operations	O
normally	O
take	O
one	O
cycle	O
,	O
greatly	O
simplifying	O
the	O
decoding	O
.	O
</s>
<s>
The	O
savings	O
in	O
these	O
interlocking	O
circuits	O
is	O
instead	O
applied	O
to	O
additional	O
logic	O
or	O
adding	O
processor	B-General_Concept
registers	I-General_Concept
,	O
which	O
have	O
a	O
direct	O
impact	O
on	O
performance	O
.	O
</s>
<s>
The	O
downside	O
to	O
the	O
RISC	B-Architecture
approach	O
is	O
that	O
many	O
instructions	O
simply	O
do	O
not	O
require	O
four	O
bytes	B-Application
.	O
</s>
<s>
In	O
the	O
6502	B-General_Concept
,	O
which	O
has	O
only	O
a	O
single	O
arithmetic	O
register	O
A	O
,	O
this	O
instruction	O
can	O
be	O
represented	O
entirely	O
by	O
its	O
8-bit	O
opcode	B-Language
.	O
</s>
<s>
On	O
processors	O
with	O
more	O
registers	O
,	O
all	O
that	O
is	O
needed	O
is	O
the	O
opcode	B-Language
and	O
register	O
number	O
,	O
another	O
4	O
or	O
5	O
bits	O
.	O
</s>
<s>
On	O
MIPS	O
,	O
for	O
instance	O
,	O
the	O
instruction	O
needs	O
only	O
a	O
6-bit	O
opcode	B-Language
and	O
a	O
5-bit	O
register	O
number	O
.	O
</s>
<s>
But	O
as	O
is	O
the	O
case	O
for	O
most	O
RISC	B-Architecture
designs	O
,	O
the	O
instruction	O
still	O
takes	O
up	O
a	O
full	O
32	O
bits	O
.	O
</s>
<s>
As	O
these	O
sorts	O
of	O
instructions	O
are	O
relatively	O
common	O
,	O
RISC	B-Architecture
programs	O
generally	O
take	O
up	O
more	O
memory	O
than	O
the	O
same	O
program	O
on	O
a	O
variable	O
length	O
processor	O
.	O
</s>
<s>
In	O
the	O
1980s	O
,	O
when	O
the	O
RISC	B-Architecture
concept	O
was	O
first	O
emerging	O
,	O
this	O
was	O
a	O
common	O
point	O
of	O
complaint	O
.	O
</s>
<s>
Extensive	O
benchmarking	O
eventually	O
demonstrated	O
RISC	B-Architecture
was	O
faster	O
in	O
almost	O
all	O
cases	O
,	O
and	O
this	O
argument	O
faded	O
.	O
</s>
<s>
The	O
resulting	O
instruction	B-General_Concept
set	I-General_Concept
has	O
real-world	O
limitations	O
;	O
for	O
instance	O
,	O
it	O
can	O
only	O
perform	O
two-operand	O
math	O
of	O
the	O
form	O
,	O
whereas	O
most	O
processors	O
of	O
the	O
era	O
used	O
the	O
three-operand	O
format	O
,	O
.	O
</s>
<s>
A	O
significant	O
advantage	O
of	O
the	O
16-bit	O
format	O
is	O
that	O
the	O
instruction	O
cache	O
now	O
holds	O
twice	O
as	O
many	O
instructions	O
for	O
any	O
given	O
amount	O
of	O
SRAM	B-Architecture
.	O
</s>
<s>
In	O
order	O
to	O
provide	O
backward	B-General_Concept
compatibility	I-General_Concept
with	O
their	O
earlier	O
designs	O
,	O
they	O
included	O
a	O
second	O
instruction	B-General_Concept
set	I-General_Concept
,	O
SHcompact	O
.	O
</s>
<s>
SHcompact	O
mapped	O
the	O
original	O
16-bit	O
instructions	O
one-way	O
onto	O
the	O
internal	O
32-bit	O
instruction	O
;	O
it	O
did	O
not	O
perform	O
multiple	O
instructions	O
as	O
would	O
be	O
the	O
case	O
in	O
earlier	O
microcoded	B-Device
processors	O
,	O
it	O
was	O
simply	O
a	O
smaller	O
format	O
for	O
the	O
same	O
instruction	O
.	O
</s>
<s>
ARM	O
processors	O
with	O
a	O
"	O
T	O
"	O
in	O
the	O
name	O
included	O
this	O
instruction	B-General_Concept
set	I-General_Concept
in	O
addition	O
to	O
their	O
original	O
32-bit	O
versions	O
,	O
and	O
could	O
be	O
switched	O
from	O
32	O
-	O
to	O
16-bit	O
mode	O
on	O
the	O
fly	O
using	O
the	O
command	O
.	O
</s>
<s>
The	O
MIPS	B-Device
architecture	I-Device
also	O
added	O
a	O
similar	O
compressed	O
set	O
in	O
their	O
MIPS16e	O
,	O
which	O
is	O
very	O
similar	O
to	O
Thumb	O
.	O
</s>
<s>
It	O
too	O
allows	O
only	O
eight	O
registers	O
to	O
be	O
used	O
,	O
although	O
these	O
are	O
not	O
simply	O
the	O
first	O
eight	O
;	O
the	O
MIPS	O
design	O
uses	O
register	O
0	O
as	O
the	O
zero	B-Architecture
register	I-Architecture
,	O
so	O
registers	O
0	O
and	O
1	O
in	O
16-bit	O
mode	O
are	O
instead	O
mapped	O
onto	O
MIPS32	O
registers	O
16	O
and	O
17	O
.	O
</s>
<s>
Likewise	O
,	O
the	O
latest	O
version	O
of	O
the	O
Power	B-Architecture
ISA	I-Architecture
,	O
formerly	O
PowerPC	B-Architecture
,	O
include	O
the	O
"	O
VLE	O
"	O
instructions	O
which	O
are	O
essentially	O
identical	O
.	O
</s>
<s>
Starting	O
around	O
2015	O
,	O
many	O
processors	O
have	O
moved	O
to	O
a	O
64-bit	B-Device
format	O
.	O
</s>
<s>
These	O
generally	O
retained	O
a	O
32-bit	O
instruction	O
format	O
,	O
while	O
expanding	O
the	O
internal	O
registers	O
to	O
a	O
64-bit	B-Device
format	O
.	O
</s>
<s>
By	O
the	O
original	O
definition	O
,	O
these	O
are	O
compressed	B-Architecture
instructions	I-Architecture
,	O
as	O
they	O
are	O
smaller	O
than	O
the	O
basic	O
data	O
word	O
size	O
.	O
</s>
<s>
However	O
,	O
this	O
term	O
is	O
not	O
used	O
in	O
this	O
context	O
;	O
references	O
to	O
compressed	B-Architecture
instructions	I-Architecture
invariably	O
refer	O
to	O
16-bit	O
versions	O
.	O
</s>
