<s>
A	O
complex	B-General_Concept
programmable	I-General_Concept
logic	I-General_Concept
device	I-General_Concept
(	O
CPLD	B-General_Concept
)	O
is	O
a	O
programmable	O
logic	O
device	O
with	O
complexity	O
between	O
that	O
of	O
PALs	O
and	O
FPGAs	B-Architecture
,	O
and	O
architectural	O
features	O
of	O
both	O
.	O
</s>
<s>
The	O
main	O
building	O
block	O
of	O
the	O
CPLD	B-General_Concept
is	O
a	O
macrocell	O
,	O
which	O
contains	O
logic	O
implementing	O
disjunctive	B-Application
normal	I-Application
form	I-Application
expressions	O
and	O
more	O
specialized	O
logic	O
operations	O
.	O
</s>
<s>
Some	O
of	O
the	O
CPLD	B-General_Concept
features	O
are	O
in	O
common	O
with	O
PALs	O
:	O
</s>
<s>
Unlike	O
many	O
FPGAs	B-Architecture
,	O
an	O
external	O
configuration	O
ROM	B-Device
is	O
n't	O
required	O
,	O
and	O
the	O
CPLD	B-General_Concept
can	O
function	O
immediately	O
on	O
system	O
start-up	O
.	O
</s>
<s>
For	O
many	O
legacy	O
CPLD	B-General_Concept
devices	O
,	O
routing	O
constrains	O
most	O
logic	O
blocks	O
to	O
have	O
input	O
and	O
output	O
signals	O
connected	O
to	O
external	O
pins	O
,	O
reducing	O
opportunities	O
for	O
internal	O
state	O
storage	O
and	O
deeply	O
layered	O
logic	O
.	O
</s>
<s>
This	O
is	O
usually	O
not	O
a	O
factor	O
for	O
larger	O
CPLDs	B-General_Concept
and	O
newer	O
CPLD	B-General_Concept
product	O
families	O
.	O
</s>
<s>
Other	O
features	O
are	O
in	O
common	O
with	O
FPGAs	B-Architecture
:	O
</s>
<s>
CPLDs	B-General_Concept
typically	O
have	O
the	O
equivalent	O
of	O
thousands	O
to	O
tens	O
of	O
thousands	O
of	O
logic	O
gates	O
,	O
allowing	O
implementation	O
of	O
moderately	O
complicated	O
data	O
processing	O
devices	O
.	O
</s>
<s>
PALs	O
typically	O
have	O
a	O
few	O
hundred	O
gate	O
equivalents	O
at	O
most	O
,	O
while	O
FPGAs	B-Architecture
typically	O
range	O
from	O
tens	O
of	O
thousands	O
to	O
several	O
million	O
.	O
</s>
<s>
Some	O
provisions	O
for	O
logic	O
more	O
flexible	O
than	O
sum-of-product	B-Application
expressions	O
,	O
including	O
complicated	O
feedback	O
paths	O
between	O
macro	O
cells	O
,	O
and	O
specialized	O
logic	O
for	O
implementing	O
various	O
commonly	O
used	O
functions	O
,	O
such	O
as	O
integer	O
arithmetic	O
.	O
</s>
<s>
The	O
most	O
noticeable	O
difference	O
between	O
a	O
large	O
CPLD	B-General_Concept
and	O
a	O
small	O
FPGA	B-Architecture
is	O
the	O
presence	O
of	O
on-chip	O
non-volatile	O
memory	O
in	O
the	O
CPLD	B-General_Concept
,	O
which	O
allows	O
CPLDs	B-General_Concept
to	O
be	O
used	O
for	O
"	O
boot	B-Application
loader	I-Application
"	O
functions	O
,	O
before	O
handing	O
over	O
control	O
to	O
other	O
devices	O
not	O
having	O
their	O
own	O
permanent	O
program	O
storage	O
.	O
</s>
<s>
A	O
good	O
example	O
is	O
where	O
a	O
CPLD	B-General_Concept
is	O
used	O
to	O
load	O
configuration	O
data	O
for	O
an	O
FPGA	B-Architecture
from	O
non-volatile	O
memory	O
.	O
</s>
<s>
CPLDs	B-General_Concept
were	O
an	O
evolutionary	O
step	O
from	O
even	O
smaller	O
devices	O
that	O
preceded	O
them	O
,	O
PLAs	O
(	O
first	O
shipped	O
by	O
Signetics	O
)	O
,	O
and	O
PALs	O
.	O
</s>
<s>
These	O
in	O
turn	O
were	O
preceded	O
by	O
standard	B-General_Concept
logic	I-General_Concept
products	O
,	O
that	O
offered	O
no	O
programmability	O
and	O
were	O
used	O
to	O
build	O
logic	O
functions	O
by	O
physically	O
wiring	O
several	O
standard	B-General_Concept
logic	I-General_Concept
chips	O
(	O
or	O
hundreds	O
of	O
them	O
)	O
together	O
(	O
usually	O
with	O
wiring	O
on	O
a	O
printed	O
circuit	O
board	O
or	O
boards	O
,	O
but	O
sometimes	O
,	O
especially	O
for	O
prototyping	O
,	O
using	O
wire	O
wrap	O
wiring	O
)	O
.	O
</s>
<s>
The	O
main	O
distinction	O
between	O
FPGA	B-Architecture
and	O
CPLD	B-General_Concept
device	O
architectures	O
is	O
that	O
CPLDs	B-General_Concept
are	O
internally	O
based	O
on	O
a	O
collection	O
of	O
PLDs	O
,	O
accompanied	O
by	O
a	O
programmable	O
interconnection	O
structure	O
while	O
FPGAs	B-Architecture
use	O
logic	O
blocks	O
.	O
</s>
