<s>
A	O
complex	B-Architecture
instruction	I-Architecture
set	I-Architecture
computer	I-Architecture
(	O
CISC	O
)	O
is	O
a	O
computer	B-General_Concept
architecture	I-General_Concept
in	O
which	O
single	O
instructions	O
can	O
execute	O
several	O
low-level	O
operations	O
(	O
such	O
as	O
a	O
load	O
from	O
memory	B-General_Concept
,	O
an	O
arithmetic	O
operation	O
,	O
and	O
a	O
memory	B-General_Concept
store	I-General_Concept
)	O
or	O
are	O
capable	O
of	O
multi-step	O
operations	O
or	O
addressing	B-Language
modes	I-Language
within	O
single	O
instructions	O
.	O
</s>
<s>
The	O
term	O
was	O
retroactively	O
coined	O
in	O
contrast	O
to	O
reduced	B-Architecture
instruction	I-Architecture
set	I-Architecture
computer	I-Architecture
(	O
RISC	B-Architecture
)	O
and	O
has	O
therefore	O
become	O
something	O
of	O
an	O
umbrella	O
term	O
for	O
everything	O
that	O
is	O
not	O
RISC	B-Architecture
,	O
where	O
the	O
typical	O
differentiating	O
characteristic	O
is	O
that	O
most	O
RISC	B-Architecture
designs	O
use	O
uniform	O
instruction	B-General_Concept
length	O
for	O
almost	O
all	O
instructions	O
,	O
and	O
employ	O
strictly	O
separate	O
load	B-General_Concept
and	I-General_Concept
store	I-General_Concept
instructions	I-General_Concept
.	O
</s>
<s>
Examples	O
of	O
CISC	B-Architecture
architectures	I-Architecture
include	O
complex	O
mainframe	B-Architecture
computers	I-Architecture
to	O
simplistic	O
microcontrollers	B-Architecture
where	O
memory	B-General_Concept
load	O
and	O
store	O
operations	O
are	O
not	O
separated	O
from	O
arithmetic	O
instructions	O
.	O
</s>
<s>
Specific	O
instruction	B-General_Concept
set	I-General_Concept
architectures	I-General_Concept
that	O
have	O
been	O
retroactively	O
labeled	O
CISC	O
are	O
System/360	B-Application
through	O
z/Architecture	B-Device
,	O
the	O
PDP-11	B-Device
and	O
VAX	B-Device
architectures	O
,	O
and	O
many	O
others	O
.	O
</s>
<s>
Well	O
known	O
microprocessors	O
and	O
microcontrollers	B-Architecture
that	O
have	O
also	O
been	O
labeled	O
CISC	O
in	O
many	O
academic	O
publications	O
include	O
the	O
Motorola	B-Device
6800	I-Device
,	O
6809	B-Device
and	O
68000-families	O
;	O
the	O
Intel	B-General_Concept
8080	I-General_Concept
,	O
iAPX432	B-Device
and	O
x86-family	O
;	O
the	O
Zilog	B-General_Concept
Z80	I-General_Concept
,	O
Z8	B-Device
and	O
Z8000-families	O
;	O
the	O
National	B-Device
Semiconductor	I-Device
32016	I-Device
and	O
NS320xx-line	O
;	O
the	O
MOS	O
Technology	O
6502-family	O
;	O
the	O
Intel	O
8051-family	O
;	O
and	O
others	O
.	O
</s>
<s>
For	O
instance	O
,	O
the	O
Microchip	O
Technology	O
PIC	B-Architecture
has	O
been	O
labeled	O
RISC	B-Architecture
in	O
some	O
circles	O
and	O
CISC	O
in	O
others	O
.	O
</s>
<s>
The	O
6502	B-General_Concept
and	O
6809	B-Device
have	O
both	O
been	O
described	O
as	O
RISC-like	O
,	O
although	O
they	O
have	O
complex	O
addressing	B-Language
modes	I-Language
as	O
well	O
as	O
arithmetic	O
instructions	O
that	O
operate	O
on	O
memory	B-General_Concept
,	O
contrary	O
to	O
the	O
RISC	B-Architecture
principles	O
.	O
</s>
<s>
Before	O
the	O
RISC	B-Architecture
philosophy	O
became	O
prominent	O
,	O
many	O
computer	B-General_Concept
architects	I-General_Concept
tried	O
to	O
bridge	O
the	O
so-called	O
semantic	O
gap	O
,	O
i.e.	O
,	O
to	O
design	O
instruction	B-General_Concept
sets	I-General_Concept
that	O
directly	O
support	O
high-level	B-Language
programming	I-Language
constructs	O
such	O
as	O
procedure	O
calls	O
,	O
loop	O
control	O
,	O
and	O
complex	O
addressing	B-Language
modes	I-Language
,	O
allowing	O
data	O
structure	O
and	O
array	O
accesses	O
to	O
be	O
combined	O
into	O
single	O
instructions	O
.	O
</s>
<s>
The	O
compact	O
nature	O
of	O
such	O
instruction	B-General_Concept
sets	I-General_Concept
results	O
in	O
smaller	O
program	B-Application
sizes	O
and	O
fewer	O
main	O
memory	B-General_Concept
accesses	O
(	O
which	O
were	O
often	O
slow	O
)	O
,	O
which	O
at	O
the	O
time	O
(	O
early	O
1960s	O
and	O
onwards	O
)	O
resulted	O
in	O
a	O
tremendous	O
saving	O
on	O
the	O
cost	O
of	O
computer	B-General_Concept
memory	I-General_Concept
and	O
disc	O
storage	O
,	O
as	O
well	O
as	O
faster	O
execution	O
.	O
</s>
<s>
It	O
also	O
meant	O
good	O
programming	O
productivity	O
even	O
in	O
assembly	B-Language
language	I-Language
,	O
as	O
high	B-Language
level	I-Language
languages	I-Language
such	O
as	O
Fortran	B-Application
or	O
Algol	B-Language
were	O
not	O
always	O
available	O
or	O
appropriate	O
.	O
</s>
<s>
Indeed	O
,	O
microprocessors	O
in	O
this	O
category	O
are	O
sometimes	O
still	O
programmed	O
in	O
assembly	B-Language
language	I-Language
for	O
certain	O
types	O
of	O
critical	O
applications	O
.	O
</s>
<s>
In	O
the	O
1970s	O
,	O
analysis	O
of	O
high-level	B-Language
languages	I-Language
indicated	O
compilers	O
produced	O
some	O
complex	O
corresponding	O
machine	O
language	O
.	O
</s>
<s>
Some	O
instructions	O
were	O
added	O
that	O
were	O
never	O
intended	O
to	O
be	O
used	O
in	O
assembly	B-Language
language	I-Language
but	O
fit	O
well	O
with	O
compiled	O
high-level	B-Language
languages	I-Language
.	O
</s>
<s>
The	O
benefits	O
of	O
semantically	O
rich	O
instructions	O
with	O
compact	O
encodings	O
can	O
be	O
seen	O
in	O
modern	O
processors	O
as	O
well	O
,	O
particularly	O
in	O
the	O
high-performance	O
segment	O
where	O
caches	O
are	O
a	O
central	O
component	O
(	O
as	O
opposed	O
to	O
most	O
embedded	B-Architecture
systems	I-Architecture
)	O
.	O
</s>
<s>
While	O
many	O
designs	O
achieved	O
the	O
aim	O
of	O
higher	O
throughput	O
at	O
lower	O
cost	O
and	O
also	O
allowed	O
high-level	B-Language
language	I-Language
constructs	O
to	O
be	O
expressed	O
by	O
fewer	O
instructions	O
,	O
it	O
was	O
observed	O
that	O
this	O
was	O
not	O
always	O
the	O
case	O
.	O
</s>
<s>
using	O
less	O
hardware	O
)	O
could	O
lead	O
to	O
situations	O
where	O
it	O
was	O
possible	O
to	O
improve	O
performance	O
by	O
not	O
using	O
a	O
complex	O
instruction	B-General_Concept
(	O
such	O
as	O
a	O
procedure	O
call	O
or	O
enter	O
instruction	B-General_Concept
)	O
but	O
instead	O
using	O
a	O
sequence	O
of	O
simpler	O
instructions	O
.	O
</s>
<s>
One	O
reason	O
for	O
this	O
was	O
that	O
architects	O
(	O
microcode	B-Device
writers	O
)	O
sometimes	O
"	O
over-designed	O
"	O
assembly	B-Language
language	I-Language
instructions	O
,	O
including	O
features	O
that	O
could	O
not	O
be	O
implemented	O
efficiently	O
on	O
the	O
basic	O
hardware	O
available	O
.	O
</s>
<s>
There	O
could	O
,	O
for	O
instance	O
,	O
be	O
"	O
side	O
effects	O
"	O
(	O
above	O
conventional	O
flags	O
)	O
,	O
such	O
as	O
the	O
setting	O
of	O
a	O
register	O
or	O
memory	B-General_Concept
location	O
that	O
was	O
perhaps	O
seldom	O
used	O
;	O
if	O
this	O
was	O
done	O
via	O
ordinary	O
(	O
non	O
duplicated	O
)	O
internal	O
buses	O
,	O
or	O
even	O
the	O
external	O
bus	O
,	O
it	O
would	O
demand	O
extra	O
cycles	O
every	O
time	O
,	O
and	O
thus	O
be	O
quite	O
inefficient	O
.	O
</s>
<s>
Such	O
architectures	O
therefore	O
required	O
a	O
great	O
deal	O
of	O
work	O
on	O
the	O
part	O
of	O
the	O
processor	O
designer	O
in	O
cases	O
where	O
a	O
simpler	O
,	O
but	O
(	O
typically	O
)	O
slower	O
,	O
solution	O
based	O
on	O
decode	O
tables	O
and/or	O
microcode	B-Device
sequencing	O
is	O
not	O
appropriate	O
.	O
</s>
<s>
The	O
circuitry	O
that	O
performs	O
the	O
actions	O
defined	O
by	O
the	O
microcode	B-Device
in	O
many	O
(	O
but	O
not	O
all	O
)	O
CISC	B-Architecture
processors	I-Architecture
is	O
,	O
in	O
itself	O
,	O
a	O
processor	O
which	O
in	O
many	O
ways	O
is	O
reminiscent	O
in	O
structure	O
to	O
very	O
early	O
CPU	O
designs	O
.	O
</s>
<s>
An	O
early	O
(	O
retroactively	O
)	O
RISC-labeled	O
processor	O
(	O
IBM	B-Device
801	I-Device
IBM	O
's	O
Watson	O
Research	O
Center	O
,	O
mid-1970s	O
)	O
was	O
a	O
tightly	O
pipelined	O
simple	O
machine	O
originally	O
intended	O
to	O
be	O
used	O
as	O
an	O
internal	O
microcode	B-Device
kernel	O
,	O
or	O
engine	O
,	O
in	O
CISC	O
designs	O
,	O
but	O
also	O
became	O
the	O
processor	O
that	O
introduced	O
the	O
RISC	B-Architecture
idea	O
to	O
a	O
somewhat	O
larger	O
audience	O
.	O
</s>
<s>
Simplicity	O
and	O
regularity	O
also	O
in	O
the	O
visible	O
instruction	B-General_Concept
set	I-General_Concept
would	O
make	O
it	O
easier	O
to	O
implement	O
overlapping	O
processor	O
stages	O
(	O
pipelining	B-General_Concept
)	O
at	O
the	O
machine	O
code	O
level	O
(	O
i.e.	O
</s>
<s>
However	O
,	O
pipelining	B-General_Concept
at	O
that	O
level	O
was	O
already	O
used	O
in	O
some	O
high-performance	O
CISC	O
"	O
supercomputers	O
"	O
in	O
order	O
to	O
reduce	O
the	O
instruction	B-General_Concept
cycle	O
time	O
(	O
despite	O
the	O
complications	O
of	O
implementing	O
within	O
the	O
limited	O
component	O
count	O
and	O
wiring	O
complexity	O
feasible	O
at	O
the	O
time	O
)	O
.	O
</s>
<s>
Internal	O
microcode	B-Device
execution	O
in	O
CISC	B-Architecture
processors	I-Architecture
,	O
on	O
the	O
other	O
hand	O
,	O
could	O
be	O
more	O
or	O
less	O
pipelined	O
depending	O
on	O
the	O
particular	O
design	O
,	O
and	O
therefore	O
more	O
or	O
less	O
akin	O
to	O
the	O
basic	O
structure	O
of	O
RISC	B-Architecture
processors	I-Architecture
.	O
</s>
<s>
The	O
CDC	B-Device
6600	I-Device
supercomputer	O
,	O
first	O
delivered	O
in	O
1965	O
,	O
has	O
also	O
been	O
retroactively	O
described	O
as	O
RISC	B-Architecture
.	O
</s>
<s>
It	O
had	O
a	O
load	B-Architecture
–	I-Architecture
store	I-Architecture
architecture	I-Architecture
which	O
allowed	O
up	O
to	O
five	O
loads	O
and	O
two	O
stores	O
to	O
be	O
in	O
progress	O
simultaneously	O
under	O
programmer	O
control	O
.	O
</s>
<s>
In	O
a	O
more	O
modern	O
context	O
,	O
the	O
complex	O
variable-length	O
encoding	O
used	O
by	O
some	O
of	O
the	O
typical	O
CISC	B-Architecture
architectures	I-Architecture
makes	O
it	O
complicated	O
,	O
but	O
still	O
feasible	O
,	O
to	O
build	O
a	O
superscalar	B-General_Concept
implementation	O
of	O
a	O
CISC	O
programming	O
model	O
directly	O
;	O
the	O
in-order	O
superscalar	B-General_Concept
original	B-General_Concept
Pentium	I-General_Concept
and	O
the	O
out-of-order	O
superscalar	B-General_Concept
Cyrix	B-General_Concept
6x86	I-General_Concept
are	O
well-known	O
examples	O
of	O
this	O
.	O
</s>
<s>
The	O
frequent	O
memory	B-General_Concept
accesses	O
for	O
operands	O
of	O
a	O
typical	O
CISC	O
machine	O
may	O
limit	O
the	O
instruction-level	O
parallelism	O
that	O
can	O
be	O
extracted	O
from	O
the	O
code	O
,	O
although	O
this	O
is	O
strongly	O
mediated	O
by	O
the	O
fast	O
cache	O
structures	O
used	O
in	O
modern	O
designs	O
,	O
as	O
well	O
as	O
by	O
other	O
measures	O
.	O
</s>
<s>
per	O
byte	O
or	O
bit	O
)	O
is	O
higher	O
for	O
a	O
CISC	O
than	O
a	O
RISC	B-Architecture
processor	I-Architecture
,	O
which	O
may	O
give	O
it	O
a	O
significant	O
advantage	O
in	O
a	O
modern	O
cache-based	O
implementation	O
.	O
</s>
<s>
Transistors	O
for	O
logic	O
,	O
PLAs	O
,	O
and	O
microcode	B-Device
are	O
no	O
longer	O
scarce	O
resources	O
;	O
only	O
large	O
high-speed	O
cache	O
memories	O
are	O
limited	O
by	O
the	O
maximum	O
number	O
of	O
transistors	O
today	O
.	O
</s>
<s>
Together	O
with	O
better	O
tools	O
and	O
enhanced	O
technologies	O
,	O
this	O
has	O
led	O
to	O
new	O
implementations	O
of	O
highly	O
encoded	O
and	O
variable-length	O
designs	O
without	O
load	B-Architecture
–	I-Architecture
store	I-Architecture
limitations	O
(	O
i.e.	O
</s>
<s>
non-RISC	O
)	O
.	O
</s>
<s>
This	O
governs	O
re-implementations	O
of	O
older	O
architectures	O
such	O
as	O
the	O
ubiquitous	O
x86	B-Operating_System
(	O
see	O
below	O
)	O
as	O
well	O
as	O
new	O
designs	O
for	O
microcontrollers	B-Architecture
for	O
embedded	B-Architecture
systems	I-Architecture
,	O
and	O
similar	O
uses	O
.	O
</s>
<s>
The	O
superscalar	B-General_Concept
complexity	O
in	O
the	O
case	O
of	O
modern	O
x86	B-Operating_System
was	O
solved	O
by	O
converting	O
instructions	O
into	O
one	O
or	O
more	O
micro-operations	B-General_Concept
and	O
dynamically	O
issuing	O
those	O
micro-operations	B-General_Concept
,	O
i.e.	O
</s>
<s>
indirect	O
and	O
dynamic	O
superscalar	B-General_Concept
execution	I-General_Concept
;	O
the	O
Pentium	B-Device
Pro	I-Device
and	O
AMD	O
K5	O
are	O
early	O
examples	O
of	O
this	O
.	O
</s>
<s>
It	O
allows	O
a	O
fairly	O
simple	O
superscalar	B-General_Concept
design	O
to	O
be	O
located	O
after	O
the	O
(	O
fairly	O
complex	O
)	O
decoders	O
(	O
and	O
buffers	O
)	O
,	O
giving	O
,	O
so	O
to	O
speak	O
,	O
the	O
best	O
of	O
both	O
worlds	O
in	O
many	O
respects	O
.	O
</s>
<s>
This	O
technique	O
is	O
also	O
used	O
in	O
IBM	B-Device
z196	I-Device
and	O
later	O
z/Architecture	B-Device
microprocessors	O
.	O
</s>
<s>
The	O
terms	O
CISC	O
and	O
RISC	B-Architecture
have	O
become	O
less	O
meaningful	O
with	O
the	O
continued	O
evolution	O
of	O
both	O
CISC	O
and	O
RISC	B-Architecture
designs	O
and	O
implementations	O
.	O
</s>
<s>
The	O
first	O
highly	O
(	O
or	O
tightly	O
)	O
pipelined	O
x86	B-Operating_System
implementations	O
,	O
the	O
486	O
designs	O
from	O
Intel	O
,	O
AMD	O
,	O
Cyrix	O
,	O
and	O
IBM	O
,	O
supported	O
every	O
instruction	B-General_Concept
that	O
their	O
predecessors	O
did	O
,	O
but	O
achieved	O
maximum	O
efficiency	O
only	O
on	O
a	O
fairly	O
simple	O
x86	B-Operating_System
subset	O
that	O
was	O
only	O
a	O
little	O
more	O
than	O
a	O
typical	O
RISC	B-Architecture
instruction	I-Architecture
set	I-Architecture
(	O
i.e.	O
,	O
without	O
typical	O
RISC	B-Architecture
load	B-Architecture
–	I-Architecture
store	I-Architecture
limits	O
)	O
.	O
</s>
<s>
The	O
Intel	B-General_Concept
P5	I-General_Concept
Pentium	B-General_Concept
generation	O
was	O
a	O
superscalar	B-General_Concept
version	O
of	O
these	O
principles	O
.	O
</s>
<s>
However	O
,	O
modern	O
x86	B-Operating_System
processors	O
also	O
(	O
typically	O
)	O
decode	O
and	O
split	O
instructions	O
into	O
dynamic	O
sequences	O
of	O
internally	O
buffered	O
micro-operations	B-General_Concept
,	O
which	O
helps	O
execute	O
a	O
larger	O
subset	O
of	O
instructions	O
in	O
a	O
pipelined	O
(	O
overlapping	O
)	O
fashion	O
,	O
and	O
facilitates	O
more	O
advanced	O
extraction	O
of	O
parallelism	O
out	O
of	O
the	O
code	O
stream	O
,	O
for	O
even	O
higher	O
performance	O
.	O
</s>
<s>
Contrary	O
to	O
popular	O
simplifications	O
(	O
present	O
also	O
in	O
some	O
academic	O
texts	O
,	O
)	O
not	O
all	O
CISCs	O
are	O
microcoded	B-Device
or	O
have	O
"	O
complex	O
"	O
instructions	O
.	O
</s>
<s>
As	O
CISC	O
became	O
a	O
catch-all	O
term	O
meaning	O
anything	O
that	O
's	O
not	O
a	O
load	B-Architecture
–	I-Architecture
store	I-Architecture
(	O
RISC	B-Architecture
)	O
architecture	O
,	O
it	O
's	O
not	O
the	O
number	O
of	O
instructions	O
,	O
nor	O
the	O
complexity	O
of	O
the	O
implementation	O
or	O
of	O
the	O
instructions	O
,	O
that	O
define	O
CISC	O
,	O
but	O
that	O
arithmetic	O
instructions	O
also	O
perform	O
memory	B-General_Concept
accesses	O
.	O
</s>
<s>
Compared	O
to	O
a	O
small	O
8-bit	O
CISC	B-Architecture
processor	I-Architecture
,	O
a	O
RISC	B-Architecture
floating-point	O
instruction	B-General_Concept
is	O
complex	O
.	O
</s>
<s>
CISC	O
does	O
not	O
even	O
need	O
to	O
have	O
complex	O
addressing	B-Language
modes	I-Language
;	O
32	O
-	O
or	O
64-bit	O
RISC	B-Architecture
processors	I-Architecture
may	O
well	O
have	O
more	O
complex	O
addressing	B-Language
modes	I-Language
than	O
small	O
8-bit	O
CISC	B-Architecture
processors	I-Architecture
.	O
</s>
<s>
A	O
PDP-10	B-Device
,	O
a	O
PDP-8	B-Device
,	O
an	O
Intel	B-General_Concept
80386	I-General_Concept
,	O
an	O
Intel	B-General_Concept
4004	I-General_Concept
,	O
a	O
Motorola	B-Device
68000	I-Device
,	O
a	O
System	B-Device
z	I-Device
mainframe	B-Architecture
,	O
a	O
Burroughs	B-Device
B5000	I-Device
,	O
a	O
VAX	B-Device
,	O
a	O
Zilog	B-Device
Z80000	I-Device
,	O
and	O
a	O
MOS	B-General_Concept
Technology	I-General_Concept
6502	I-General_Concept
all	O
vary	O
widely	O
in	O
the	O
number	O
,	O
sizes	O
,	O
and	O
formats	O
of	O
instructions	O
,	O
the	O
number	O
,	O
types	O
,	O
and	O
sizes	O
of	O
registers	O
,	O
and	O
the	O
available	O
data	O
types	O
.	O
</s>
<s>
because	O
they	O
have	O
"	O
load-operate	O
"	O
instructions	O
that	O
load	O
and/or	O
store	O
memory	B-General_Concept
contents	O
within	O
the	O
same	O
instructions	O
that	O
perform	O
the	O
actual	O
calculations	O
.	O
</s>
<s>
For	O
instance	O
,	O
the	O
PDP-8	B-Device
,	O
having	O
only	O
8	O
fixed-length	O
instructions	O
and	O
no	O
microcode	B-Device
at	O
all	O
,	O
is	O
a	O
CISC	O
because	O
of	O
how	O
the	O
instructions	O
work	O
,	O
PowerPC	O
,	O
which	O
has	O
over	O
230	O
instructions	O
(	O
more	O
than	O
some	O
VAXes	B-Device
)	O
,	O
and	O
complex	O
internals	O
like	O
register	O
renaming	O
and	O
a	O
reorder	O
buffer	O
,	O
is	O
a	O
RISC	B-Architecture
,	O
while	O
has	O
8	O
instructions	O
,	O
but	O
is	O
clearly	O
a	O
CISC	O
because	O
it	O
combines	O
memory	B-General_Concept
access	O
and	O
computation	O
in	O
the	O
same	O
instructions	O
.	O
</s>
