<s>
The	O
following	O
is	O
a	O
comparison	B-Architecture
of	I-Architecture
CPU	I-Architecture
microarchitectures	I-Architecture
.	O
</s>
<s>
Microarchitecture	B-General_Concept
Year	O
Pipeline	O
stages	O
Misc	O
Elbrus-8S	B-General_Concept
2014	O
VLIW	B-General_Concept
,	O
Elbrus	O
(	O
proprietary	O
,	O
closed	O
)	O
version	O
5	O
,	O
64-bit	O
AMD	O
K51996	O
5	O
Superscalar	B-General_Concept
,	O
branch	B-General_Concept
prediction	I-General_Concept
,	O
speculative	B-General_Concept
execution	I-General_Concept
,	O
out-of-order	B-General_Concept
execution	I-General_Concept
,	O
register	O
renaming	O
AMD	O
K61997	O
6	O
Superscalar	B-General_Concept
,	O
branch	B-General_Concept
prediction	I-General_Concept
,	O
speculative	B-General_Concept
execution	I-General_Concept
,	O
out-of-order	B-General_Concept
execution	I-General_Concept
,	O
register	O
renaming	O
AMD	O
K6-III1999	O
Branch	B-General_Concept
prediction	I-General_Concept
,	O
speculative	B-General_Concept
execution	I-General_Concept
,	O
out-of-order	B-General_Concept
execution	I-General_Concept
AMD	B-Architecture
K7	I-Architecture
1999	O
Out-of-order	B-General_Concept
execution	I-General_Concept
,	O
branch	B-General_Concept
prediction	I-General_Concept
,	O
Harvard	B-Architecture
architecture	I-Architecture
AMD	B-Device
K8	I-Device
2003	O
64-bit	O
,	O
integrated	B-General_Concept
memory	I-General_Concept
controller	I-General_Concept
,	O
16	O
byte	B-Application
instruction	O
prefetching	B-General_Concept
AMD	O
K10	O
2007	O
Superscalar	B-General_Concept
,	O
out-of-order	B-General_Concept
execution	I-General_Concept
,	O
32-way	O
set	O
associative	O
L3	O
victim	B-General_Concept
cache	I-General_Concept
,	O
32-byte	O
instruction	O
prefetching	B-General_Concept
ARM7TDMI	O
(	O
-S	O
)	O
2001	O
3	O
ARM7EJ-S	O
2001	O
5	O
ARM810	O
5	O
static	O
branch	B-General_Concept
prediction	I-General_Concept
,	O
double-bandwidth	O
memory	O
ARM9TDMI	O
1998	O
5	O
ARM1020E	O
6	O
XScale	B-Application
PXA210/PXA250	I-Application
2002	O
7	O
ARM1136J(F )	O
-S	O
8	O
ARM1156T2(F )	O
-S	O
9	O
ARM	B-Application
Cortex-A5	I-Application
8	O
Multi-core	B-Architecture
,	O
single	O
issue	O
,	O
in-order	O
ARM	B-Application
Cortex-A7	I-Application
MPCore	I-Application
8	O
Partial	O
dual-issue	O
,	O
in-order	O
,	O
2-way	O
set	O
associative	O
level	O
1	O
instruction	O
cache	B-General_Concept
ARM	B-Application
Cortex-A8	I-Application
2005	O
13	O
Dual-issue	O
,	O
in-order	O
,	O
speculative	B-General_Concept
execution	I-General_Concept
,	O
superscalar	B-General_Concept
,	O
2-way	O
pipeline	O
decode	O
ARM	B-Application
Cortex-A9	I-Application
MPCore	I-Application
2007	O
8	O
–	O
11	O
Out-of-order	O
,	O
speculative	O
issue	O
,	O
superscalar	B-General_Concept
ARM	O
Cortex-A15	O
MPCore	O
2010	O
15	O
Multi-core	B-Architecture
(	O
up	O
to	O
16	O
)	O
,	O
out-of-order	O
,	O
speculative	O
issue	O
,	O
3-way	O
superscalar	B-General_Concept
ARM	O
Cortex-A53	O
2012	O
Partial	O
dual-issue	O
,	O
in-order	O
ARM	O
Cortex-A55	O
2017	O
8	O
in-order	O
,	O
speculative	B-General_Concept
execution	I-General_Concept
ARM	O
Cortex-A57	O
2012	O
Deeply	O
out-of-order	O
,	O
wide	O
multi-issue	O
,	O
3-way	O
superscalar	B-General_Concept
ARM	O
Cortex-A72	O
2015	O
ARM	O
Cortex-A73	O
2016	O
Out-of-order	O
superscalar	B-General_Concept
ARM	O
Cortex-A75	O
2017	O
11	O
–	O
13	O
Out-of-order	O
superscalar	B-General_Concept
,	O
speculative	B-General_Concept
execution	I-General_Concept
,	O
register	O
renaming	O
,	O
3-way	O
ARM	O
Cortex-A76	O
2018	O
13	O
Out-of-order	O
superscalar	B-General_Concept
,	O
4-way	O
pipeline	O
decode	O
ARM	O
Cortex-A77	O
2019	O
13	O
Out-of-order	O
superscalar	B-General_Concept
,	O
speculative	B-General_Concept
execution	I-General_Concept
,	O
register	O
renaming	O
,	O
6-way	O
pipeline	O
decode	O
,	O
10-issue	O
,	O
branch	B-General_Concept
prediction	I-General_Concept
,	O
L3	O
cache	B-General_Concept
ARM	O
Cortex-A78	O
2020	O
13	O
Out-of-order	O
superscalar	B-General_Concept
,	O
register	O
renaming	O
,	O
4-way	O
pipeline	O
decode	O
,	O
6	O
instruction	O
per	O
cycle	O
,	O
branch	B-General_Concept
prediction	I-General_Concept
,	O
L3	O
cache	B-General_Concept
ARM	O
Cortex-X1	O
2020	O
13	O
5-wide	O
decode	O
out-of-order	O
superscalar	B-General_Concept
,	O
L3	O
cache	B-General_Concept
AVR32	O
AP7	O
7	O
AVR32	O
UC3	O
3	O
Harvard	B-Architecture
architecture	I-Architecture
Bobcat2011	O
Out-of-order	B-General_Concept
execution	I-General_Concept
Bulldozer2011	O
20	O
Shared	O
multithreaded	O
L2	O
cache	B-General_Concept
,	O
multithreading	B-General_Concept
,	O
multi-core	B-Architecture
,	O
around	O
20	O
stage	O
long	O
pipeline	O
,	O
integrated	B-General_Concept
memory	I-General_Concept
controller	I-General_Concept
,	O
out-of-order	O
,	O
superscalar	B-General_Concept
,	O
up	O
to	O
16	O
cores	O
per	O
chip	O
,	O
up	O
to	O
16	O
MB	O
L3	O
cache	B-General_Concept
,	O
Virtualization	B-General_Concept
,	O
Turbo	O
Core	B-Device
,	O
FlexFPU	O
which	O
uses	O
simultaneous	B-Operating_System
multithreading	I-Operating_System
Piledriver2012	O
Shared	O
multithreaded	O
L2	O
cache	B-General_Concept
,	O
multithreading	B-General_Concept
,	O
multi-core	B-Architecture
,	O
around	O
20	O
stage	O
long	O
pipeline	O
,	O
integrated	B-General_Concept
memory	I-General_Concept
controller	I-General_Concept
,	O
out-of-order	O
,	O
superscalar	B-General_Concept
,	O
up	O
to	O
16	O
MB	O
L2	O
cache	B-General_Concept
,	O
up	O
to	O
16	O
MB	O
L3	O
cache	B-General_Concept
,	O
Virtualization	B-General_Concept
,	O
FlexFPU	O
which	O
use	O
simultaneous	B-Operating_System
multithreading	I-Operating_System
,	O
up	O
to	O
16	O
cores	O
per	O
chip	O
,	O
up	O
to	O
5	O
GHz	O
clock	O
speed	O
,	O
up	O
to	O
220	O
W	O
TDP	O
,	O
Turbo	O
Core	B-Device
Steamroller2014	O
Multi-core	B-Architecture
,	O
branch	B-General_Concept
prediction	I-General_Concept
Excavator2015	O
20	O
Multi-core	B-Architecture
Zen	O
2017	O
19	O
Multi-core	B-Architecture
,	O
superscalar	B-General_Concept
,	O
2-way	O
simultaneous	B-Operating_System
multithreading	I-Operating_System
,	O
4-way	O
decode	O
,	O
out-of-order	B-General_Concept
execution	I-General_Concept
,	O
L3	O
cache	B-General_Concept
Zen+	O
2018	O
19	O
Multi-core	B-Architecture
,	O
superscalar	B-General_Concept
,	O
4-way	O
decode	O
,	O
out-of-order	B-General_Concept
execution	I-General_Concept
,	O
L3	O
cache	B-General_Concept
Zen	O
2	O
2019	O
19	O
Multi-chip	O
module	O
,	O
multi-core	B-Architecture
,	O
superscalar	B-General_Concept
,	O
4-way	O
decode	O
,	O
out-of-order	B-General_Concept
execution	I-General_Concept
,	O
L3	O
cache	B-General_Concept
Zen	O
3	O
2020	O
19	O
Multi-chip	O
module	O
,	O
multi-core	B-Architecture
,	O
superscalar	B-General_Concept
,	O
4-way	O
decode	O
,	O
out-of-order	B-General_Concept
execution	I-General_Concept
,	O
SMT	O
,	O
L3	O
cache	B-General_Concept
Zen	O
4	O
2022	O
Multi-chip	O
module	O
,	O
multi-core	B-Architecture
,	O
superscalar	B-General_Concept
,	O
L3	O
cache	B-General_Concept
Crusoe2000	O
In-order	O
execution	O
,	O
128-bit	O
VLIW	B-General_Concept
,	O
integrated	B-General_Concept
memory	I-General_Concept
controller	I-General_Concept
Efficeon2004	O
In-order	O
execution	O
,	O
256-bit	O
VLIW	B-General_Concept
,	O
fully	O
integrated	B-General_Concept
memory	I-General_Concept
controller	I-General_Concept
Cyrix	O
Cx5x861995	O
6	O
Branch	B-General_Concept
prediction	I-General_Concept
Cyrix	O
6x861996	O
Superscalar	B-General_Concept
,	O
superpipelined	O
,	O
register	O
renaming	O
,	O
speculative	B-General_Concept
execution	I-General_Concept
,	O
out-of-order	B-General_Concept
execution	I-General_Concept
DLX	B-Architecture
5	O
eSi-3200	B-Architecture
5	O
In-order	O
,	O
speculative	O
issue	O
eSi-3250	B-Architecture
5	O
In-order	O
,	O
speculative	O
issue	O
EV4	O
(	O
Alpha	B-General_Concept
21064	I-General_Concept
)	O
Superscalar	B-General_Concept
EV7	O
(	O
Alpha	B-General_Concept
21364	I-General_Concept
)	O
Superscalar	B-General_Concept
design	O
with	O
out-of-order	B-General_Concept
execution	I-General_Concept
,	O
branch	B-General_Concept
prediction	I-General_Concept
,	O
4-way	O
simultaneous	B-Operating_System
multithreading	I-Operating_System
,	O
integrated	B-General_Concept
memory	I-General_Concept
controller	I-General_Concept
EV8	O
(	O
Alpha	B-General_Concept
21464	I-General_Concept
)	O
Superscalar	B-General_Concept
design	O
with	O
out-of-order	B-General_Concept
execution	I-General_Concept
65k	O
Ultra	O
low	O
power	O
consumption	O
,	O
register	O
renaming	O
,	O
out-of-order	B-General_Concept
execution	I-General_Concept
,	O
branch	B-General_Concept
prediction	I-General_Concept
,	O
multi-core	B-Architecture
,	O
module	O
,	O
capable	O
of	O
reach	O
higher	O
clock	O
P5	B-General_Concept
(	O
Pentium	B-General_Concept
)	O
1993	O
5	O
Superscalar	B-General_Concept
P6	B-Device
(	O
Pentium	B-Device
Pro	I-Device
)	O
14	O
Speculative	B-General_Concept
execution	I-General_Concept
,	O
register	O
renaming	O
,	O
superscalar	B-General_Concept
design	O
with	O
out-of-order	B-General_Concept
execution	I-General_Concept
P6	B-Device
(	O
Pentium	B-General_Concept
II	I-General_Concept
)	O
14	O
Branch	B-General_Concept
prediction	I-General_Concept
P6	B-Device
(	O
Pentium	B-General_Concept
III	I-General_Concept
)	O
1995	O
14	O
Intel	B-General_Concept
Itanium	I-General_Concept
"	O
Merced	O
"	O
2001	O
Single	O
core	B-Device
,	O
L3	O
cache	B-General_Concept
Intel	B-General_Concept
Itanium	I-General_Concept
2	O
"	O
McKinley	O
"	O
2002	O
11Intel	O
Itanium	B-General_Concept
2	O
Processor	O
Hardware	O
Developer	O
's	O
Manual	O
.	O
</s>
<s>
p	O
.	O
14	O
.	O
http://www.intel.com/design/itanium2/manuals/25110901.pdf	O
(	O
2002	O
)	O
Retrieved	O
28	O
November	O
2011	O
Speculative	B-General_Concept
execution	I-General_Concept
,	O
branch	B-General_Concept
prediction	I-General_Concept
,	O
register	O
renaming	O
,	O
30	O
execution	B-General_Concept
units	I-General_Concept
,	O
multithreading	B-General_Concept
,	O
multi-core	B-Architecture
,	O
coarse-grained	O
multithreading	B-General_Concept
,	O
2-way	O
simultaneous	B-Operating_System
multithreading	I-Operating_System
,	O
Dual-domain	O
multithreading	B-General_Concept
,	O
Turbo	B-Device
Boost	I-Device
,	O
Virtualization	B-General_Concept
,	O
VLIW	B-General_Concept
,	O
RAS	O
with	O
Advanced	O
Machine	O
Check	O
Architecture	O
,	O
Instruction	O
Replay	O
technology	O
,	O
Cache	B-General_Concept
Safe	O
technology	O
,	O
Enhanced	O
SpeedStep	O
technology	O
Intel	B-Device
NetBurst	I-Device
(	O
Willamette	O
)	O
2000	O
20	O
2-way	O
simultaneous	B-Operating_System
multithreading	I-Operating_System
(	O
Hyper-threading	B-Operating_System
)	O
,	O
Rapid	O
Execution	O
Engine	O
,	O
Execution	O
Trace	O
Cache	B-General_Concept
,	O
quad-pumped	O
Front-Side	O
Bus	O
,	O
Hyper-pipelined	O
Technology	O
,	O
superscalar	B-General_Concept
,	O
out-of	O
order	O
NetBurst	B-Device
(	O
Northwood	O
)	O
2002	O
20	O
2-way	O
simultaneous	B-Operating_System
multithreading	I-Operating_System
NetBurst	B-Device
(	O
Prescott	O
)	O
2004	O
31	O
2-way	O
simultaneous	B-Operating_System
multithreading	I-Operating_System
NetBurst	B-Device
(	O
Cedar	O
Mill	O
)	O
2006	O
31	O
2-way	O
simultaneous	B-Operating_System
multithreading	I-Operating_System
Intel	B-Device
Core	I-Device
2006	O
12	O
Multi-core	B-Architecture
,	O
out-of-order	O
,	O
4-way	O
superscalar	B-General_Concept
Intel	B-Device
Atom	I-Device
16	O
2-way	O
simultaneous	B-Operating_System
multithreading	I-Operating_System
,	O
in-order	O
,	O
no	O
instruction	O
reordering	O
,	O
speculative	B-General_Concept
execution	I-General_Concept
,	O
or	O
register	O
renaming	O
Intel	B-Device
Atom	I-Device
Oak	O
Trail	O
2-way	O
simultaneous	B-Operating_System
multithreading	I-Operating_System
,	O
in-order	O
,	O
burst	O
mode	O
,	O
512	O
KB	O
L2	O
cache	B-General_Concept
Intel	B-Device
Atom	I-Device
Bonnell	B-Device
2008	O
SMT	O
Intel	B-Device
Atom	I-Device
Silvermont	B-Device
2013	O
Out-of-order	B-General_Concept
execution	I-General_Concept
Intel	B-Device
Atom	I-Device
Goldmont	B-Device
2016	O
Multi-core	B-Architecture
,	O
out-of-order	B-General_Concept
execution	I-General_Concept
,	O
3-wide	O
superscalar	B-General_Concept
pipeline	O
,	O
L2	O
cache	B-General_Concept
Intel	B-Device
Atom	I-Device
Goldmont	B-Device
Plus	I-Device
2017	O
Multi-core	B-Architecture
Intel	B-Device
Atom	I-Device
Tremont	B-Device
2019	O
Multi-core	B-Architecture
,	O
superscalar	B-General_Concept
,	O
out-of-order	B-General_Concept
execution	I-General_Concept
,	O
speculative	B-General_Concept
execution	I-General_Concept
,	O
register	O
renaming	O
Intel	B-Device
Atom	I-Device
Gracemont	O
2021	O
Multi-core	B-Architecture
,	O
superscalar	B-General_Concept
,	O
out-of-order	B-General_Concept
execution	I-General_Concept
,	O
speculative	B-General_Concept
execution	I-General_Concept
,	O
register	O
renaming	O
Nehalem2008	O
14	O
2-way	O
simultaneous	B-Operating_System
multithreading	I-Operating_System
,	O
out-of-order	O
,	O
6-way	O
superscalar	B-General_Concept
,	O
integrated	B-General_Concept
memory	I-General_Concept
controller	I-General_Concept
,	O
L1/L2/L3	O
cache	B-General_Concept
,	O
Turbo	B-Device
Boost	I-Device
Sandy	O
Bridge2011	O
14	O
2-way	O
simultaneous	B-Operating_System
multithreading	I-Operating_System
,	O
multi-core	B-Architecture
,	O
on-die	O
graphics	O
and	O
PCIe	O
controller	O
,	O
system	O
agent	O
with	O
integrated	O
memory	O
and	O
display	O
controller	O
,	O
ring	O
interconnect	O
,	O
L1/L2/L3	O
cache	B-General_Concept
,	O
micro-op	O
cache	B-General_Concept
,	O
2	O
threads	O
per	O
core	B-Device
,	O
Turbo	B-Device
Boost	I-Device
,	O
Intel	O
Haswell2013	O
14	O
–	O
19	O
SoC	B-Architecture
design	O
,	O
multi-core	B-Architecture
,	O
multithreading	B-General_Concept
,	O
2-way	O
simultaneous	B-Operating_System
multithreading	I-Operating_System
,	O
hardware-based	O
transactional	B-Operating_System
memory	I-Operating_System
(	O
in	O
selected	O
models	O
)	O
,	O
L4	O
cache	B-General_Concept
(	O
in	O
GT3	O
models	O
)	O
,	O
Turbo	B-Device
Boost	I-Device
,	O
out-of-order	B-General_Concept
execution	I-General_Concept
,	O
superscalar	B-General_Concept
,	O
up	O
to	O
8	O
MB	O
L3	O
cache	B-General_Concept
(	O
mainstream	O
)	O
,	O
up	O
to	O
20	O
MB	O
L3	O
cache	B-General_Concept
(	O
Extreme	O
)	O
Broadwell2014	O
14	O
–	O
19	O
Multi-core	B-Architecture
,	O
multithreading	B-General_Concept
Skylake2015	O
14	O
–	O
19	O
Multi-core	B-Architecture
,	O
L4	O
cache	B-General_Concept
on	O
certain	O
Skylake-R	O
,	O
Skylake-U	O
and	O
Skylake-Y	O
models	O
.	O
</s>
<s>
On-package	O
PCH	B-Device
on	O
U	O
,	O
Y	O
,	O
m3	O
,	O
m5	O
and	O
m7	O
models	O
.	O
</s>
<s>
5	O
wide	O
superscalar/5	O
issues	O
.	O
</s>
<s>
Kaby	O
Lake2016	O
14	O
–	O
19	O
Multi-core	B-Architecture
,	O
L4	O
cache	B-General_Concept
on	O
certain	O
low	O
and	O
ultra	O
low	O
power	O
models	O
(	O
Kaby	O
Lake-U	O
and	O
Kaby	O
Lake-Y	O
)	O
,	O
Intel	O
Sunny	O
Cove	O
2019	O
14	O
–	O
20	O
Multicore	B-Architecture
,	O
2-way	O
multithreading	B-General_Concept
,	O
massive	O
OoOE	B-General_Concept
engine	O
,	O
5	O
wide	O
superscalar/5	O
issue	O
.	O
</s>
<s>
Intel	O
Cypress	O
Cove	O
2021	O
14	O
multicore	B-Architecture
,	O
5	O
wide	O
superscalar/6	O
issues	O
,	O
massive	O
OoOE	B-General_Concept
engine	O
,	O
big	O
core	B-Device
design	O
.	O
</s>
