<s>
In	O
the	O
history	B-Architecture
of	I-Architecture
computer	I-Architecture
hardware	I-Architecture
,	O
some	O
early	O
reduced	B-Architecture
instruction	I-Architecture
set	I-Architecture
computer	I-Architecture
central	B-General_Concept
processing	I-General_Concept
units	I-General_Concept
(	O
RISC	B-Architecture
CPUs	O
)	O
used	O
a	O
very	O
similar	O
architectural	O
solution	O
,	O
now	O
called	O
a	O
classic	B-General_Concept
RISC	I-General_Concept
pipeline	I-General_Concept
.	O
</s>
<s>
Those	O
CPUs	O
were	O
:	O
MIPS	B-Device
,	O
SPARC	B-Architecture
,	O
Motorola	B-Architecture
88000	I-Architecture
,	O
and	O
later	O
the	O
notional	O
CPU	O
DLX	B-Architecture
invented	O
for	O
education	O
.	O
</s>
<s>
Each	O
of	O
these	O
classic	O
scalar	O
RISC	B-Architecture
designs	O
fetches	O
and	O
tries	O
to	O
execute	O
one	O
instruction	O
per	O
cycle	O
.	O
</s>
<s>
The	O
main	O
common	O
concept	O
of	O
each	O
design	O
is	O
a	O
five-stage	O
execution	O
instruction	B-General_Concept
pipeline	I-General_Concept
.	O
</s>
<s>
Each	O
of	O
these	O
stages	O
consists	O
of	O
a	O
set	O
of	O
flip-flops	B-General_Concept
to	O
hold	O
state	O
,	O
and	O
combinational	O
logic	O
that	O
operates	O
on	O
the	O
outputs	O
of	O
those	O
flip-flops	B-General_Concept
.	O
</s>
<s>
This	O
memory	O
can	O
be	O
dedicated	O
to	O
SRAM	O
,	O
or	O
an	O
Instruction	O
Cache	B-General_Concept
.	O
</s>
<s>
Thus	O
,	O
instruction	O
fetch	O
has	O
a	O
latency	O
of	O
one	O
clock	O
cycle	O
(	O
if	O
using	O
single-cycle	O
SRAM	O
or	O
if	O
the	O
instruction	O
was	O
in	O
the	O
cache	B-General_Concept
)	O
.	O
</s>
<s>
The	O
Program	B-General_Concept
Counter	I-General_Concept
,	O
or	O
PC	O
is	O
a	O
register	O
that	O
holds	O
the	O
address	O
that	O
is	O
presented	O
to	O
the	O
instruction	O
memory	O
.	O
</s>
<s>
Note	O
that	O
in	O
classic	O
RISC	B-Architecture
,	O
all	O
instructions	O
have	O
the	O
same	O
length	O
.	O
</s>
<s>
(	O
This	O
is	O
one	O
thing	O
that	O
separates	O
RISC	B-Architecture
from	O
CISC	O
)	O
.	O
</s>
<s>
In	O
the	O
original	O
RISC	B-Architecture
designs	O
,	O
the	O
size	O
of	O
an	O
instruction	O
is	O
4	O
bytes	O
,	O
so	O
always	O
add	O
4	O
to	O
the	O
instruction	O
address	O
,	O
but	O
do	O
n't	O
use	O
PC	O
+	O
4	O
for	O
the	O
case	O
of	O
a	O
taken	O
branch	O
,	O
jump	O
,	O
or	O
exception	O
(	O
see	O
delayed	O
branches	O
,	O
below	O
)	O
.	O
</s>
<s>
(	O
Note	O
that	O
some	O
modern	O
machines	O
use	O
more	O
complicated	O
algorithms	O
(	O
branch	B-General_Concept
prediction	I-General_Concept
and	O
branch	B-General_Concept
target	I-General_Concept
prediction	I-General_Concept
)	O
to	O
guess	O
the	O
next	B-General_Concept
instruction	I-General_Concept
address	I-General_Concept
.	O
)	O
</s>
<s>
Another	O
thing	O
that	O
separates	O
the	O
first	O
RISC	B-Architecture
machines	O
from	O
earlier	O
CISC	O
machines	O
,	O
is	O
that	O
RISC	B-Architecture
has	O
no	O
microcode	B-Device
.	O
</s>
<s>
In	O
the	O
case	O
of	O
CISC	O
micro-coded	O
instructions	O
,	O
once	O
fetched	O
from	O
the	O
instruction	O
cache	B-General_Concept
,	O
the	O
instruction	O
bits	O
are	O
shifted	O
down	O
the	O
pipeline	O
,	O
where	O
simple	O
combinational	O
logic	O
in	O
each	O
pipeline	O
stage	O
produces	O
control	O
signals	O
for	O
the	O
datapath	O
directly	O
from	O
the	O
instruction	O
bits	O
.	O
</s>
<s>
All	O
MIPS	B-Device
,	O
SPARC	B-Architecture
,	O
and	O
DLX	B-Architecture
instructions	O
have	O
at	O
most	O
two	O
register	O
inputs	O
.	O
</s>
<s>
Thus	O
the	O
two	O
registers	O
named	O
are	O
read	O
from	O
the	O
register	B-General_Concept
file	I-General_Concept
.	O
</s>
<s>
In	O
the	O
MIPS	B-Device
design	O
,	O
the	O
register	B-General_Concept
file	I-General_Concept
had	O
32	O
entries	O
.	O
</s>
<s>
At	O
the	O
same	O
time	O
the	O
register	B-General_Concept
file	I-General_Concept
is	O
read	O
,	O
instruction	O
issue	O
logic	O
in	O
this	O
stage	O
determines	O
if	O
the	O
pipeline	O
is	O
ready	O
to	O
execute	O
the	O
instruction	O
in	O
this	O
stage	O
.	O
</s>
<s>
On	O
a	O
stall	O
cycle	O
,	O
the	O
input	O
flip	B-General_Concept
flops	I-General_Concept
do	O
not	O
accept	O
new	O
bits	O
,	O
thus	O
no	O
new	O
calculations	O
take	O
place	O
during	O
that	O
cycle	O
.	O
</s>
<s>
If	O
the	O
instruction	O
decoded	O
is	O
a	O
branch	O
or	O
jump	O
,	O
the	O
target	O
address	O
of	O
the	O
branch	O
or	O
jump	O
is	O
computed	O
in	O
parallel	O
with	O
reading	O
the	O
register	B-General_Concept
file	I-General_Concept
.	O
</s>
<s>
The	O
branch	O
condition	O
is	O
computed	O
in	O
the	O
following	O
cycle	O
(	O
after	O
the	O
register	B-General_Concept
file	I-General_Concept
is	O
read	O
)	O
,	O
and	O
if	O
the	O
branch	O
is	O
taken	O
or	O
if	O
the	O
instruction	O
is	O
a	O
jump	O
,	O
the	O
PC	O
in	O
the	O
first	O
stage	O
is	O
assigned	O
the	O
branch	O
target	O
,	O
rather	O
than	O
the	O
incremented	O
PC	O
that	O
has	O
been	O
computed	O
.	O
</s>
<s>
Some	O
architectures	O
made	O
use	O
of	O
the	O
Arithmetic	B-General_Concept
logic	I-General_Concept
unit	I-General_Concept
(	O
ALU	O
)	O
in	O
the	O
Execute	O
stage	O
,	O
at	O
the	O
cost	O
of	O
slightly	O
decreased	O
instruction	O
throughput	O
.	O
</s>
<s>
The	O
decode	O
stage	O
ended	O
up	O
with	O
quite	O
a	O
lot	O
of	O
hardware	O
:	O
MIPS	B-Device
has	O
the	O
possibility	O
of	O
branching	O
if	O
two	O
registers	O
are	O
equal	O
,	O
so	O
a	O
32-bit-wide	O
AND	O
tree	O
runs	O
in	O
series	O
after	O
the	O
register	B-General_Concept
file	I-General_Concept
read	O
,	O
making	O
a	O
very	O
long	O
critical	O
path	O
through	O
this	O
stage	O
(	O
which	O
means	O
fewer	O
cycles	O
per	O
second	O
)	O
.	O
</s>
<s>
Instructions	O
on	O
these	O
simple	O
RISC	B-Architecture
machines	O
can	O
be	O
divided	O
into	O
three	O
latency	O
classes	O
according	O
to	O
the	O
type	O
of	O
the	O
operation	O
:	O
</s>
<s>
Integer	O
multiply	O
and	O
divide	O
and	O
all	O
floating-point	B-Algorithm
operations	O
.	O
</s>
<s>
This	O
forwarding	O
ensures	O
that	O
both	O
one	O
and	O
two	O
cycle	O
instructions	O
always	O
write	O
their	O
results	O
in	O
the	O
same	O
stage	O
of	O
the	O
pipeline	O
so	O
that	O
just	O
one	O
write	O
port	O
to	O
the	O
register	B-General_Concept
file	I-General_Concept
can	O
be	O
used	O
,	O
and	O
it	O
is	O
always	O
available	O
.	O
</s>
<s>
For	O
direct	O
mapped	O
and	O
virtually	O
tagged	O
data	O
caching	B-General_Concept
,	O
the	O
simplest	O
by	O
far	O
of	O
the	O
numerous	B-General_Concept
data	I-General_Concept
cache	I-General_Concept
organizations	I-General_Concept
,	O
two	O
SRAMs	B-Architecture
are	O
used	O
,	O
one	O
storing	O
data	O
and	O
the	O
other	O
storing	O
tags	O
.	O
</s>
<s>
During	O
this	O
stage	O
,	O
both	O
single	O
cycle	O
and	O
two	O
cycle	O
instructions	O
write	O
their	O
results	O
into	O
the	O
register	B-General_Concept
file	I-General_Concept
.	O
</s>
<s>
Note	O
that	O
two	O
different	O
stages	O
are	O
accessing	O
the	O
register	B-General_Concept
file	I-General_Concept
at	O
the	O
same	O
time	O
--	O
the	O
decode	O
stage	O
is	O
reading	O
two	O
source	O
registers	O
,	O
at	O
the	O
same	O
time	O
that	O
the	O
writeback	O
stage	O
is	O
writing	O
a	O
previous	O
instruction	O
's	O
destination	O
register	O
.	O
</s>
<s>
On	O
real	O
silicon	O
,	O
this	O
can	O
be	O
a	O
hazard	B-General_Concept
(	O
see	O
below	O
for	O
more	O
on	O
hazards	B-General_Concept
)	O
.	O
</s>
<s>
When	O
that	O
happens	O
,	O
then	O
the	O
same	O
memory	O
cells	O
in	O
the	O
register	B-General_Concept
file	I-General_Concept
are	O
being	O
both	O
read	O
and	O
written	O
the	O
same	O
time	O
.	O
</s>
<s>
Hennessy	O
and	O
Patterson	O
coined	O
the	O
term	O
hazard	B-General_Concept
for	O
situations	O
where	O
instructions	O
in	O
a	O
pipeline	O
would	O
produce	O
wrong	O
answers	O
.	O
</s>
<s>
Structural	O
hazards	B-General_Concept
occur	O
when	O
two	O
instructions	O
might	O
attempt	O
to	O
use	O
the	O
same	O
resources	O
at	O
the	O
same	O
time	O
.	O
</s>
<s>
Classic	B-General_Concept
RISC	I-General_Concept
pipelines	I-General_Concept
avoided	O
these	O
hazards	B-General_Concept
by	O
replicating	O
hardware	O
.	O
</s>
<s>
Data	O
hazards	B-General_Concept
occur	O
when	O
an	O
instruction	O
,	O
scheduled	O
blindly	O
,	O
would	O
attempt	O
to	O
use	O
data	O
before	O
the	O
data	O
is	O
available	O
in	O
the	O
register	B-General_Concept
file	I-General_Concept
.	O
</s>
<s>
In	O
the	O
classic	B-General_Concept
RISC	I-General_Concept
pipeline	I-General_Concept
,	O
Data	O
hazards	B-General_Concept
are	O
avoided	O
in	O
one	O
of	O
two	O
ways	O
:	O
</s>
<s>
Bypassing	O
is	O
also	O
known	O
as	O
operand	B-General_Concept
forwarding	I-General_Concept
.	O
</s>
<s>
In	O
a	O
naive	O
pipeline	O
,	O
without	O
hazard	B-General_Concept
consideration	O
,	O
the	O
data	O
hazard	B-General_Concept
progresses	O
as	O
follows	O
:	O
</s>
<s>
In	O
the	O
same	O
cycle	O
,	O
the	O
AND	O
operation	O
is	O
decoded	O
,	O
and	O
the	O
value	O
of	O
r10	O
is	O
fetched	O
from	O
the	O
register	B-General_Concept
file	I-General_Concept
.	O
</s>
<s>
Therefore	O
,	O
the	O
value	O
read	O
from	O
the	O
register	B-General_Concept
file	I-General_Concept
and	O
passed	O
to	O
the	O
ALU	O
(	O
in	O
the	O
Execute	O
stage	O
of	O
the	O
AND	O
operation	O
,	O
red	O
box	O
)	O
is	O
incorrect	O
.	O
</s>
<s>
A	O
register	B-General_Concept
file	I-General_Concept
read	O
port	O
(	O
i.e.	O
</s>
<s>
If	O
this	O
occurs	O
,	O
a	O
bubble	B-General_Concept
must	O
be	O
inserted	O
to	O
stall	O
the	O
AND	O
operation	O
until	O
the	O
data	O
is	O
ready	O
.	O
</s>
<s>
These	O
bypass	O
multiplexers	O
make	O
it	O
possible	O
for	O
the	O
pipeline	O
to	O
execute	O
simple	O
instructions	O
with	O
just	O
the	O
latency	O
of	O
the	O
ALU	O
,	O
the	O
multiplexer	O
,	O
and	O
a	O
flip-flop	B-General_Concept
.	O
</s>
<s>
Without	O
the	O
multiplexers	O
,	O
the	O
latency	O
of	O
writing	O
and	O
then	O
reading	O
the	O
register	B-General_Concept
file	I-General_Concept
would	O
have	O
to	O
be	O
included	O
in	O
the	O
latency	O
of	O
these	O
instructions	O
.	O
</s>
<s>
The	O
data	O
read	O
from	O
the	O
address	O
adr	O
is	O
not	O
present	O
in	O
the	O
data	B-General_Concept
cache	I-General_Concept
until	O
after	O
the	O
Memory	O
Access	O
stage	O
of	O
the	O
LD	O
instruction	O
.	O
</s>
<s>
The	O
data	O
hazard	B-General_Concept
is	O
detected	O
in	O
the	O
decode	O
stage	O
,	O
and	O
the	O
fetch	O
and	O
decode	O
stages	O
are	O
stalled	O
-	O
they	O
are	O
prevented	O
from	O
flopping	O
their	O
inputs	O
and	O
so	O
stay	O
in	O
the	O
same	O
state	O
for	O
a	O
cycle	O
.	O
</s>
<s>
This	O
NOP	O
is	O
termed	O
a	O
pipeline	B-General_Concept
bubble	I-General_Concept
since	O
it	O
floats	B-Algorithm
in	O
the	O
pipeline	O
,	O
like	O
an	O
air	O
bubble	B-General_Concept
in	O
a	O
water	O
pipe	O
,	O
occupying	O
resources	O
but	O
not	O
producing	O
useful	O
results	O
.	O
</s>
<s>
The	O
hardware	O
to	O
detect	O
a	O
data	O
hazard	B-General_Concept
and	O
stall	O
the	O
pipeline	O
until	O
the	O
hazard	B-General_Concept
is	O
cleared	O
is	O
called	O
a	O
pipeline	O
interlock	O
.	O
</s>
<s>
A	O
pipeline	O
interlock	O
does	O
not	O
have	O
to	O
be	O
used	O
with	O
any	O
data	B-General_Concept
forwarding	I-General_Concept
,	O
however	O
.	O
</s>
<s>
The	O
first	O
example	O
of	O
the	O
SUB	O
followed	O
by	O
AND	O
and	O
the	O
second	O
example	O
of	O
LD	O
followed	O
by	O
AND	O
can	O
be	O
solved	O
by	O
stalling	O
the	O
first	O
stage	O
by	O
three	O
cycles	O
until	O
write-back	O
is	O
achieved	O
,	O
and	O
the	O
data	O
in	O
the	O
register	B-General_Concept
file	I-General_Concept
is	O
correct	O
,	O
causing	O
the	O
correct	O
register	O
value	O
to	O
be	O
fetched	O
by	O
the	O
AND	O
's	O
Decode	O
stage	O
.	O
</s>
<s>
This	O
data	O
hazard	B-General_Concept
can	O
be	O
detected	O
quite	O
easily	O
when	O
the	O
program	O
's	O
machine	O
code	O
is	O
written	O
by	O
the	O
compiler	O
.	O
</s>
<s>
The	O
Stanford	B-General_Concept
MIPS	I-General_Concept
machine	O
relied	O
on	O
the	O
compiler	O
to	O
add	O
the	O
NOP	O
instructions	O
in	O
this	O
case	O
,	O
rather	O
than	O
having	O
the	O
circuitry	O
to	O
detect	O
and	O
(	O
more	O
taxingly	O
)	O
stall	O
the	O
first	O
two	O
pipeline	O
stages	O
.	O
</s>
<s>
Hence	O
the	O
name	O
MIPS	B-Device
:	O
Microprocessor	B-General_Concept
without	I-General_Concept
Interlocked	I-General_Concept
Pipeline	I-General_Concept
Stages	I-General_Concept
.	O
</s>
<s>
It	O
turned	O
out	O
that	O
the	O
extra	O
NOP	O
instructions	O
added	O
by	O
the	O
compiler	O
expanded	O
the	O
program	O
binaries	O
enough	O
that	O
the	O
instruction	O
cache	B-General_Concept
hit	O
rate	O
was	O
reduced	O
.	O
</s>
<s>
The	O
stall	O
hardware	O
,	O
although	O
expensive	O
,	O
was	O
put	O
back	O
into	O
later	O
designs	O
to	O
improve	O
instruction	O
cache	B-General_Concept
hit	O
rate	O
,	O
at	O
which	O
point	O
the	O
acronym	O
no	O
longer	O
made	O
sense	O
.	O
</s>
<s>
Control	B-General_Concept
hazards	I-General_Concept
are	O
caused	O
by	O
conditional	O
and	O
unconditional	O
branching	O
.	O
</s>
<s>
The	O
classic	B-General_Concept
RISC	I-General_Concept
pipeline	I-General_Concept
resolves	O
branches	O
in	O
the	O
decode	O
stage	O
,	O
which	O
means	O
the	O
branch	O
resolution	O
recurrence	O
is	O
two	O
cycles	O
long	O
.	O
</s>
<s>
The	O
branch	O
resolution	O
recurrence	O
goes	O
through	O
quite	O
a	O
bit	O
of	O
circuitry	O
:	O
the	O
instruction	O
cache	B-General_Concept
read	O
,	O
register	B-General_Concept
file	I-General_Concept
read	O
,	O
branch	O
condition	O
compute	O
(	O
which	O
involves	O
a	O
32-bit	O
compare	O
on	O
the	O
MIPS	B-Device
CPUs	O
)	O
,	O
and	O
the	O
next	B-General_Concept
instruction	I-General_Concept
address	I-General_Concept
multiplexer	O
.	O
</s>
<s>
Because	O
branch	O
and	O
jump	O
targets	O
are	O
calculated	O
in	O
parallel	O
to	O
the	O
register	O
read	O
,	O
RISC	B-Architecture
ISAs	O
typically	O
do	O
not	O
have	O
instructions	O
that	O
branch	O
to	O
a	O
register+offset	O
address	O
.	O
</s>
<s>
On	O
any	O
branch	O
taken	O
,	O
the	O
instruction	O
immediately	O
after	O
the	O
branch	O
is	O
always	O
fetched	O
from	O
the	O
instruction	O
cache	B-General_Concept
.	O
</s>
<s>
Predict	O
Not	O
Taken	O
:	O
Always	O
fetch	O
the	O
instruction	O
after	O
the	O
branch	O
from	O
the	O
instruction	O
cache	B-General_Concept
,	O
but	O
only	O
execute	O
it	O
if	O
the	O
branch	O
is	O
not	O
taken	O
.	O
</s>
<s>
Branch	O
Likely	O
:	O
Always	O
fetch	O
the	O
instruction	O
after	O
the	O
branch	O
from	O
the	O
instruction	O
cache	B-General_Concept
,	O
but	O
only	O
execute	O
it	O
if	O
the	O
branch	O
was	O
taken	O
.	O
</s>
<s>
The	O
compiler	O
can	O
always	O
fill	O
the	O
branch	B-General_Concept
delay	I-General_Concept
slot	I-General_Concept
on	O
such	O
a	O
branch	O
,	O
and	O
since	O
branches	O
are	O
more	O
often	O
taken	O
than	O
not	O
,	O
such	O
branches	O
have	O
a	O
smaller	O
IPC	O
penalty	O
than	O
the	O
previous	O
kind	O
.	O
</s>
<s>
Branch	B-General_Concept
Delay	I-General_Concept
Slot	I-General_Concept
:	O
Always	O
fetch	O
the	O
instruction	O
after	O
the	O
branch	O
from	O
the	O
instruction	O
cache	B-General_Concept
,	O
and	O
always	O
execute	O
it	O
,	O
even	O
if	O
the	O
branch	O
is	O
taken	O
.	O
</s>
<s>
Instead	O
of	O
taking	O
an	O
IPC	O
penalty	O
for	O
some	O
fraction	O
of	O
branches	O
either	O
taken	O
(	O
perhaps	O
60%	O
)	O
or	O
not	O
taken	O
(	O
perhaps	O
40%	O
)	O
,	O
branch	B-General_Concept
delay	I-General_Concept
slots	I-General_Concept
take	O
an	O
IPC	O
penalty	O
for	O
those	O
branches	O
into	O
which	O
the	O
compiler	O
could	O
not	O
schedule	O
the	O
branch	B-General_Concept
delay	I-General_Concept
slot	I-General_Concept
.	O
</s>
<s>
The	O
SPARC	B-Architecture
,	O
MIPS	B-Device
,	O
and	O
MC88K	O
designers	O
designed	O
a	O
branch	B-General_Concept
delay	I-General_Concept
slot	I-General_Concept
into	O
their	O
ISAs	O
.	O
</s>
<s>
Branch	B-General_Concept
Prediction	I-General_Concept
:	O
In	O
parallel	O
with	O
fetching	O
each	O
instruction	O
,	O
guess	O
if	O
the	O
instruction	O
is	O
a	O
branch	O
or	O
jump	O
,	O
and	O
if	O
so	O
,	O
guess	O
the	O
target	O
.	O
</s>
<s>
A	O
delayed	O
branch	O
specifies	O
that	O
the	O
jump	O
to	O
a	O
new	O
location	O
happens	O
after	O
the	O
next	B-General_Concept
instruction	I-General_Concept
.	O
</s>
<s>
That	O
next	B-General_Concept
instruction	I-General_Concept
is	O
the	O
one	O
unavoidably	O
loaded	O
by	O
the	O
instruction	O
cache	B-General_Concept
after	O
the	O
branch	O
.	O
</s>
<s>
Compilers	O
typically	O
have	O
some	O
difficulty	O
finding	O
logically	O
independent	O
instructions	O
to	O
place	O
after	O
the	O
branch	O
(	O
the	O
instruction	O
after	O
the	O
branch	O
is	O
called	O
the	O
delay	B-General_Concept
slot	I-General_Concept
)	O
,	O
so	O
that	O
they	O
must	O
insert	O
NOPs	O
into	O
the	O
delay	B-General_Concept
slots	I-General_Concept
.	O
</s>
<s>
Superscalar	B-General_Concept
processors	I-General_Concept
,	O
which	O
fetch	O
multiple	O
instructions	O
per	O
cycle	O
and	O
must	O
have	O
some	O
form	O
of	O
branch	B-General_Concept
prediction	I-General_Concept
,	O
do	O
not	O
benefit	O
from	O
delayed	O
branches	O
.	O
</s>
<s>
The	O
Alpha	B-Device
ISA	O
left	O
out	O
delayed	O
branches	O
,	O
as	O
it	O
was	O
intended	O
for	O
superscalar	B-General_Concept
processors	I-General_Concept
.	O
</s>
<s>
If	O
the	O
delay	B-General_Concept
slot	I-General_Concept
instruction	O
takes	O
an	O
exception	O
,	O
the	O
processor	O
has	O
to	O
be	O
restarted	O
on	O
the	O
branch	O
,	O
rather	O
than	O
that	O
next	B-General_Concept
instruction	I-General_Concept
.	O
</s>
<s>
Suppose	O
a	O
32-bit	O
RISC	B-Architecture
processes	O
an	O
ADD	O
instruction	O
that	O
adds	O
two	O
large	O
numbers	O
,	O
and	O
the	O
result	O
does	O
not	O
fit	O
in	O
32	O
bits	O
.	O
</s>
<s>
Lisp	B-Language
or	O
Scheme	B-Language
)	O
,	O
may	O
not	O
want	O
wrapping	O
arithmetic	O
.	O
</s>
<s>
MIPS	B-Device
)	O
,	O
define	O
special	O
addition	O
operations	O
that	O
branch	O
to	O
special	O
locations	O
on	O
overflow	O
,	O
rather	O
than	O
wrapping	O
the	O
result	O
.	O
</s>
<s>
The	O
most	O
common	O
kind	O
of	O
software-visible	O
exception	O
on	O
one	O
of	O
the	O
classic	O
RISC	B-Architecture
machines	O
is	O
a	O
TLB	O
miss	O
.	O
</s>
<s>
The	O
program	B-General_Concept
counter	I-General_Concept
is	O
set	O
to	O
the	O
address	O
of	O
a	O
special	O
exception	O
handler	O
,	O
and	O
special	O
registers	O
are	O
written	O
with	O
the	O
exception	O
location	O
and	O
cause	O
.	O
</s>
<s>
This	O
in-order	O
commit	O
happens	O
very	O
naturally	O
in	O
the	O
classic	B-General_Concept
RISC	I-General_Concept
pipeline	I-General_Concept
.	O
</s>
<s>
Most	O
instructions	O
write	O
their	O
results	O
to	O
the	O
register	B-General_Concept
file	I-General_Concept
in	O
the	O
writeback	O
stage	O
,	O
and	O
so	O
those	O
writes	O
automatically	O
happen	O
in	O
program	O
order	O
.	O
</s>
<s>
If	O
the	O
store	O
instruction	O
takes	O
an	O
exception	O
,	O
the	O
Store	O
Data	O
Queue	O
entry	O
is	O
invalidated	O
so	O
that	O
it	O
is	O
not	O
written	O
to	O
the	O
cache	B-General_Concept
data	O
SRAM	O
later	O
.	O
</s>
<s>
Occasionally	O
,	O
either	O
the	O
data	O
or	O
instruction	O
cache	B-General_Concept
does	O
not	O
contain	O
a	O
required	O
datum	O
or	O
instruction	O
.	O
</s>
<s>
In	O
these	O
cases	O
,	O
the	O
CPU	O
must	O
suspend	O
operation	O
until	O
the	O
cache	B-General_Concept
can	O
be	O
filled	O
with	O
the	O
necessary	O
data	O
,	O
and	O
then	O
must	O
resume	O
execution	O
.	O
</s>
<s>
The	O
problem	O
of	O
filling	O
the	O
cache	B-General_Concept
with	O
the	O
required	O
data	O
(	O
and	O
potentially	O
writing	O
back	O
to	O
memory	O
the	O
evicted	O
cache	B-General_Concept
line	O
)	O
is	O
not	O
specific	O
to	O
the	O
pipeline	O
organization	O
,	O
and	O
is	O
not	O
discussed	O
here	O
.	O
</s>
<s>
This	O
signal	O
,	O
when	O
activated	O
,	O
prevents	O
instructions	O
from	O
advancing	O
down	O
the	O
pipeline	O
,	O
generally	O
by	O
gating	O
off	O
the	O
clock	O
to	O
the	O
flip-flops	B-General_Concept
at	O
the	O
start	O
of	O
each	O
stage	O
.	O
</s>
<s>
The	O
disadvantage	O
of	O
this	O
strategy	O
is	O
that	O
there	O
are	O
a	O
large	O
number	O
of	O
flip	B-General_Concept
flops	I-General_Concept
,	O
so	O
the	O
global	O
stall	O
signal	O
takes	O
a	O
long	O
time	O
to	O
propagate	O
.	O
</s>
<s>
When	O
the	O
cache	B-General_Concept
has	O
been	O
filled	O
with	O
the	O
necessary	O
data	O
,	O
the	O
instruction	O
that	O
caused	O
the	O
cache	B-General_Concept
miss	O
restarts	O
.	O
</s>
<s>
To	O
expedite	O
data	B-General_Concept
cache	I-General_Concept
miss	O
handling	O
,	O
the	O
instruction	O
can	O
be	O
restarted	O
so	O
that	O
its	O
access	O
cycle	O
happens	O
one	O
cycle	O
after	O
the	O
data	B-General_Concept
cache	I-General_Concept
is	O
filled	O
.	O
</s>
