<s>
Chip	B-Architecture
select	I-Architecture
(	O
CS	O
)	O
or	O
slave	B-Architecture
select	I-Architecture
(	O
SS	O
)	O
is	O
the	O
name	O
of	O
a	O
control	O
line	O
in	O
digital	O
electronics	O
used	O
to	O
select	O
one	O
(	O
or	O
a	O
set	O
)	O
of	O
integrated	O
circuits	O
(	O
commonly	O
called	O
"	O
chips	O
"	O
)	O
out	O
of	O
several	O
connected	O
to	O
the	O
same	O
computer	B-General_Concept
bus	I-General_Concept
,	O
usually	O
utilizing	O
the	O
three-state	B-Device
logic	I-Device
.	O
</s>
<s>
One	O
bus	O
that	O
uses	O
the	O
chip/slave	O
select	O
is	O
the	O
Serial	B-Architecture
Peripheral	I-Architecture
Interface	I-Architecture
Bus	I-Architecture
(	O
SPI	B-Architecture
bus	I-Architecture
)	O
.	O
</s>
<s>
When	O
an	O
engineer	O
needs	O
to	O
connect	O
several	O
devices	O
to	O
the	O
same	O
set	O
of	O
input	O
wires	O
(	O
e.g.	O
,	O
a	O
computer	B-General_Concept
bus	I-General_Concept
)	O
,	O
but	O
retain	O
the	O
ability	O
to	O
send	O
and	O
receive	O
data	O
or	O
commands	O
to	O
each	O
device	O
independently	O
of	O
the	O
others	O
on	O
the	O
bus	O
,	O
they	O
can	O
use	O
a	O
chip	B-Architecture
select	I-Architecture
.	O
</s>
<s>
The	O
chip	B-Architecture
select	I-Architecture
is	O
a	O
command	O
pin	O
on	O
many	O
integrated	O
circuits	O
which	O
connects	O
the	O
I/O	B-General_Concept
pins	O
on	O
the	O
device	O
to	O
the	O
internal	O
circuitry	O
of	O
that	O
device	O
.	O
</s>
<s>
When	O
the	O
chip	B-Architecture
select	I-Architecture
pin	O
is	O
held	O
in	O
the	O
inactive	O
state	O
,	O
the	O
chip	O
or	O
device	O
is	O
"	O
deaf	O
"	O
,	O
and	O
pays	O
no	O
heed	O
to	O
changes	O
in	O
the	O
state	O
of	O
its	O
other	O
input	O
pins	O
;	O
it	O
holds	O
its	O
outputs	O
in	O
the	O
high	O
impedance	O
state	O
,	O
so	O
other	O
chips	O
can	O
drive	O
those	O
signals	O
.	O
</s>
<s>
When	O
the	O
chip	B-Architecture
select	I-Architecture
pin	O
is	O
held	O
in	O
the	O
active	O
state	O
,	O
the	O
chip	O
or	O
device	O
assumes	O
that	O
any	O
input	O
changes	O
it	O
"	O
hears	O
"	O
are	O
meant	O
for	O
it	O
,	O
and	O
responds	O
as	O
if	O
it	O
is	O
the	O
only	O
chip	O
on	O
the	O
bus	O
.	O
</s>
<s>
Because	O
the	O
other	O
chips	O
have	O
their	O
chip	B-Architecture
select	I-Architecture
pins	O
in	O
the	O
inactive	O
state	O
,	O
their	O
outputs	O
are	O
high	O
impedance	O
,	O
allowing	O
the	O
single	O
selected	O
chip	O
to	O
drive	O
its	O
outputs	O
.	O
</s>
<s>
CS	O
may	O
also	O
affect	O
a	O
power	O
consumption	O
or	O
serve	O
as	O
cycle	O
control	O
in	O
certain	O
circuits	O
(	O
such	O
as	O
SRAM	B-Architecture
or	O
DRAM	O
)	O
.	O
</s>
