<s>
A	O
chip	B-Algorithm
scale	I-Algorithm
package	I-Algorithm
or	O
chip-scale	B-Algorithm
package	I-Algorithm
(	O
CSP	O
)	O
is	O
a	O
type	O
of	O
integrated	O
circuit	O
package	O
.	O
</s>
<s>
Since	O
only	O
a	O
few	O
packages	O
are	O
chip	O
size	O
,	O
the	O
meaning	O
of	O
the	O
acronym	O
was	O
adapted	O
to	O
chip-scale	B-Algorithm
packaging	I-Algorithm
.	O
</s>
<s>
According	O
to	O
IPC	O
's	O
standard	O
J-STD-012	O
,	O
Implementation	O
of	O
Flip	B-Device
Chip	I-Device
and	O
Chip	O
Scale	O
Technology	O
,	O
in	O
order	O
to	O
qualify	O
as	O
chip	O
scale	O
,	O
the	O
package	O
must	O
have	O
an	O
area	O
no	O
greater	O
than	O
1.2	O
times	O
that	O
of	O
the	O
die	O
and	O
it	O
must	O
be	O
a	O
single-die	O
,	O
direct	O
surface	O
mountable	O
package	O
.	O
</s>
<s>
The	O
die	O
may	O
be	O
mounted	O
on	O
an	O
interposer	O
upon	O
which	O
pads	O
or	O
balls	O
are	O
formed	O
,	O
like	O
with	O
flip	B-Device
chip	I-Device
ball	B-Algorithm
grid	I-Algorithm
array	I-Algorithm
(	O
BGA	O
)	O
packaging	O
,	O
or	O
the	O
pads	O
may	O
be	O
etched	O
or	O
printed	O
directly	O
onto	O
the	O
silicon	B-Architecture
wafer	I-Architecture
,	O
resulting	O
in	O
a	O
package	O
very	O
close	O
to	O
the	O
size	O
of	O
the	O
silicon	O
die	O
:	O
such	O
a	O
package	O
is	O
called	O
a	O
wafer-level	O
package	O
(	O
WLP	O
)	O
or	O
a	O
wafer-level	O
chip-scale	B-Algorithm
package	I-Algorithm
(	O
WL-CSP	O
)	O
.	O
</s>
<s>
Chip	B-Algorithm
scale	I-Algorithm
packages	I-Algorithm
can	O
be	O
classified	O
into	O
the	O
following	O
groups	O
:	O
</s>
