<s>
Chemical	B-Algorithm
mechanical	I-Algorithm
polishing	I-Algorithm
(	O
CMP	O
)	O
or	O
planarization	O
is	O
a	O
process	O
of	O
smoothing	O
surfaces	O
with	O
the	O
combination	O
of	O
chemical	O
and	O
mechanical	O
forces	O
.	O
</s>
<s>
It	O
can	O
be	O
thought	O
of	O
as	O
a	O
hybrid	O
of	O
chemical	O
etching	B-Algorithm
and	O
free	O
abrasive	O
polishing	O
.	O
</s>
<s>
The	O
process	O
uses	O
an	O
abrasive	O
and	O
corrosive	O
chemical	O
slurry	O
(	O
commonly	O
a	O
colloid	O
)	O
in	O
conjunction	O
with	O
a	O
polishing	O
pad	O
and	O
retaining	O
ring	O
,	O
typically	O
of	O
a	O
greater	O
diameter	O
than	O
the	O
wafer	B-Architecture
.	O
</s>
<s>
The	O
pad	O
and	O
wafer	B-Architecture
are	O
pressed	O
together	O
by	O
a	O
dynamic	O
polishing	O
head	O
and	O
held	O
in	O
place	O
by	O
a	O
plastic	O
retaining	O
ring	O
.	O
</s>
<s>
This	O
removes	O
material	O
and	O
tends	O
to	O
even	O
out	O
any	O
irregular	O
topography	O
,	O
making	O
the	O
wafer	B-Architecture
flat	O
or	O
planar	O
.	O
</s>
<s>
This	O
may	O
be	O
necessary	O
to	O
set	O
up	O
the	O
wafer	B-Architecture
for	O
the	O
formation	O
of	O
additional	O
circuit	O
elements	O
.	O
</s>
<s>
For	O
example	O
,	O
CMP	O
can	O
bring	O
the	O
entire	O
surface	O
within	O
the	O
depth	O
of	O
field	O
of	O
a	O
photolithography	B-Algorithm
system	O
,	O
or	O
selectively	O
remove	O
material	O
based	O
on	O
its	O
position	O
.	O
</s>
<s>
The	O
wafer	B-Architecture
that	O
is	O
being	O
polished	O
is	O
mounted	O
upside-down	O
in	O
a	O
carrier/spindle	O
on	O
a	O
backing	O
film	O
.	O
</s>
<s>
The	O
retaining	O
ring	O
(	O
Figure	O
1	O
)	O
keeps	O
the	O
wafer	B-Architecture
in	O
the	O
correct	O
horizontal	O
position	O
.	O
</s>
<s>
During	O
the	O
process	O
of	O
loading	O
and	O
unloading	O
the	O
wafer	B-Architecture
onto	O
the	O
tool	O
,	O
the	O
wafer	B-Architecture
is	O
held	O
by	O
vacuum	O
by	O
the	O
carrier	O
to	O
prevent	O
unwanted	O
particles	O
from	O
building	O
up	O
on	O
the	O
wafer	B-Architecture
surface	O
.	O
</s>
<s>
Down	O
force	O
depends	O
on	O
the	O
contact	O
area	O
which	O
,	O
in	O
turn	O
,	O
is	O
dependent	O
on	O
the	O
structures	O
of	O
both	O
the	O
wafer	B-Architecture
and	O
the	O
pad	O
.	O
</s>
<s>
Typically	O
the	O
pads	O
have	O
a	O
roughness	O
of	O
50μm	O
;	O
contact	O
is	O
made	O
by	O
asperities	O
(	O
which	O
typically	O
are	O
the	O
high	O
points	O
on	O
the	O
wafer	B-Architecture
)	O
and	O
,	O
as	O
a	O
result	O
,	O
the	O
contact	O
area	O
is	O
only	O
a	O
fraction	O
of	O
the	O
wafer	B-Architecture
area	O
.	O
</s>
<s>
In	O
CMP	O
,	O
the	O
mechanical	O
properties	O
of	O
the	O
wafer	B-Architecture
itself	O
must	O
be	O
considered	O
too	O
.	O
</s>
<s>
If	O
the	O
wafer	B-Architecture
has	O
a	O
slightly	O
bowed	O
structure	O
,	O
the	O
pressure	O
will	O
be	O
greater	O
on	O
the	O
edges	O
than	O
it	O
would	O
on	O
the	O
center	O
,	O
which	O
causes	O
non-uniform	O
polishing	O
.	O
</s>
<s>
In	O
order	O
to	O
compensate	O
for	O
the	O
wafer	B-Architecture
bow	O
,	O
pressure	O
can	O
be	O
applied	O
to	O
the	O
wafer	B-Architecture
's	O
backside	O
which	O
,	O
in	O
turn	O
,	O
will	O
equalize	O
the	O
centre-edge	O
differences	O
.	O
</s>
<s>
The	O
pads	O
used	O
in	O
the	O
CMP	O
tool	O
should	O
be	O
rigid	O
in	O
order	O
to	O
uniformly	O
polish	O
the	O
wafer	B-Architecture
surface	O
.	O
</s>
<s>
However	O
,	O
these	O
rigid	O
pads	O
must	O
be	O
kept	O
in	O
alignment	O
with	O
the	O
wafer	B-Architecture
at	O
all	O
times	O
.	O
</s>
<s>
Therefore	O
,	O
real	O
pads	O
are	O
often	O
just	O
stacks	O
of	O
soft	O
and	O
hard	O
materials	O
that	O
conform	O
to	O
wafer	B-Architecture
topography	O
to	O
some	O
extent	O
.	O
</s>
<s>
Chemical	B-Algorithm
mechanical	I-Algorithm
polishing	I-Algorithm
or	O
planarization	O
is	O
a	O
process	O
of	O
smoothing	O
surfaces	O
with	O
the	O
combination	O
of	O
chemical	O
and	O
mechanical	O
forces	O
.	O
</s>
<s>
It	O
can	O
be	O
thought	O
of	O
as	O
a	O
hybrid	O
of	O
chemical	O
etching	B-Algorithm
and	O
free	O
abrasive	O
polishing	O
.	O
</s>
<s>
In	O
particular	O
,	O
an	O
improvement	O
in	O
wafer	B-Architecture
metrology	O
is	O
required	O
.	O
</s>
<s>
In	O
addition	O
,	O
it	O
was	O
discovered	O
that	O
the	O
CMP	O
process	O
has	O
several	O
potential	O
defects	O
including	O
stress	O
cracking	B-Application
,	O
delaminating	O
at	O
weak	O
interfaces	O
,	O
and	O
corrosive	O
attacks	O
from	O
slurry	O
chemicals	O
.	O
</s>
<s>
If	O
the	O
oxide	O
layer	O
has	O
not	O
been	O
sufficiently	O
thinned	O
and/or	O
the	O
desired	O
degree	O
of	O
planarity	O
has	O
not	O
been	O
achieved	O
during	O
this	O
process	O
,	O
then	O
(	O
theoretically	O
)	O
the	O
wafer	B-Architecture
can	O
be	O
repolished	O
,	O
but	O
in	O
a	O
practical	O
sense	O
this	O
is	O
unattractive	O
in	O
production	O
and	O
is	O
to	O
be	O
avoided	O
if	O
at	O
all	O
possible	O
.	O
</s>
<s>
If	O
the	O
oxide	O
thickness	O
is	O
too	O
thin	O
or	O
too	O
non-uniform	O
,	O
then	O
the	O
wafer	B-Architecture
must	O
be	O
reworked	O
,	O
an	O
even	O
less	O
attractive	O
process	O
and	O
one	O
that	O
is	O
likely	O
to	O
fail	O
.	O
</s>
<s>
Moreover	O
,	O
STI	O
has	O
a	O
higher	O
degree	O
of	O
planarity	O
making	O
it	O
essential	O
in	O
photolithographic	B-Algorithm
applications	O
,	O
depth	O
of	O
focus	O
budget	O
by	O
decreasing	O
minimum	O
line	O
width	O
.	O
</s>
<s>
To	O
planarize	O
shallow	O
trenches	O
,	O
a	O
common	O
method	O
should	O
be	O
used	O
such	O
as	O
the	O
combination	O
of	O
resist	O
etching-back	O
(	O
REB	O
)	O
and	O
chemical	B-Algorithm
mechanical	I-Algorithm
polishing	I-Algorithm
(	O
CMP	O
)	O
.	O
</s>
<s>
First	O
,	O
the	O
isolation	O
trench	O
pattern	O
is	O
transferred	O
to	O
the	O
silicon	B-Architecture
wafer	I-Architecture
.	O
</s>
<s>
Oxide	O
is	O
deposited	O
on	O
the	O
wafer	B-Architecture
in	O
the	O
shape	O
of	O
trenches	O
.	O
</s>
<s>
A	O
second	O
layer	O
is	O
added	O
to	O
the	O
wafer	B-Architecture
to	O
create	O
a	O
planar	O
surface	O
.	O
</s>
<s>
Next	O
,	O
the	O
etching	B-Algorithm
process	O
is	O
used	O
to	O
etch	O
the	O
wafer	B-Architecture
and	O
leave	O
a	O
small	O
amount	O
of	O
oxide	O
in	O
the	O
active	O
areas	O
.	O
</s>
