<s>
Charge	B-Algorithm
trap	I-Algorithm
flash	I-Algorithm
(	O
CTF	O
)	O
is	O
a	O
semiconductor	B-Architecture
memory	I-Architecture
technology	O
used	O
in	O
creating	O
non-volatile	B-General_Concept
NOR	O
and	O
NAND	O
flash	B-Device
memory	I-Device
.	O
</s>
<s>
It	O
is	O
a	O
type	O
of	O
floating-gate	B-Algorithm
MOSFET	I-Algorithm
memory	B-General_Concept
technology	I-General_Concept
,	O
but	O
differs	O
from	O
the	O
conventional	O
floating-gate	B-Algorithm
technology	O
in	O
that	O
it	O
uses	O
a	O
silicon	O
nitride	O
film	O
to	O
store	O
electrons	O
rather	O
than	O
the	O
doped	O
polycrystalline	O
silicon	O
typical	O
of	O
a	O
floating-gate	B-Algorithm
structure	O
.	O
</s>
<s>
While	O
the	O
charge-trapping	O
concept	O
was	O
around	O
earlier	O
,	O
it	O
was	O
n't	O
until	O
2002	O
that	O
AMD	O
and	O
Fujitsu	O
produced	O
high-volume	O
charge-trapping	O
flash	B-Device
memory	I-Device
.	O
</s>
<s>
They	O
began	O
the	O
commercial	O
production	O
of	O
charge-trapping	O
flash	B-Device
memory	I-Device
with	O
the	O
introduction	O
of	O
the	O
GL	O
NOR	O
flash	B-Device
memory	I-Device
family	O
.	O
</s>
<s>
From	O
the	O
late	O
2000s	O
,	O
CTF	O
became	O
a	O
core	O
component	O
of	O
3D	O
V-NAND	O
flash	B-Device
memory	I-Device
developed	O
by	O
Toshiba	O
and	O
Samsung	O
Electronics	O
.	O
</s>
<s>
The	O
original	O
MOSFET	B-Architecture
(	O
metal	B-Architecture
–	I-Architecture
oxide	I-Architecture
–	I-Architecture
semiconductor	I-Architecture
field-effect	I-Architecture
transistor	I-Architecture
,	O
or	O
MOS	B-Architecture
transistor	I-Architecture
)	O
was	O
invented	O
by	O
Egyptian	O
engineer	O
Mohamed	O
M	O
.	O
Atalla	O
and	O
Korean	O
engineer	O
Dawon	O
Kahng	O
at	O
Bell	O
Labs	O
in	O
1959	O
,	O
and	O
demonstrated	O
in	O
1960	O
.	O
</s>
<s>
Kahng	O
went	O
on	O
to	O
invent	O
the	O
floating-gate	B-Algorithm
MOSFET	I-Algorithm
with	O
Simon	O
Min	O
Sze	O
at	O
Bell	O
Labs	O
,	O
and	O
they	O
proposed	O
its	O
use	O
as	O
a	O
floating-gate	B-Algorithm
(	O
FG	O
)	O
memory	B-Algorithm
cell	I-Algorithm
,	O
in	O
1967	O
.	O
</s>
<s>
This	O
was	O
the	O
first	O
form	O
of	O
non-volatile	B-General_Concept
memory	I-General_Concept
based	O
on	O
the	O
injection	O
and	O
storage	O
of	O
charges	O
in	O
a	O
floating-gate	B-Algorithm
MOSFET	I-Algorithm
,	O
which	O
later	O
became	O
the	O
basis	O
for	O
EPROM	B-General_Concept
(	O
erasable	O
PROM	B-General_Concept
)	O
,	O
EEPROM	B-General_Concept
(	O
electrically	O
erasable	O
PROM	B-General_Concept
)	O
and	O
flash	B-Device
memory	I-Device
technologies	O
.	O
</s>
<s>
Richard	O
Wegener	O
invented	O
the	O
metal	B-Algorithm
–	I-Algorithm
nitride	I-Algorithm
–	I-Algorithm
oxide	I-Algorithm
–	I-Algorithm
semiconductor	I-Algorithm
transistor	I-Algorithm
(	O
MNOS	O
transistor	O
)	O
,	O
a	O
type	O
of	O
MOSFET	B-Architecture
in	O
which	O
the	O
oxide	O
layer	O
is	O
replaced	O
by	O
a	O
double	O
layer	O
of	O
nitride	O
and	O
oxide	O
.	O
</s>
<s>
Nitride	O
was	O
used	O
as	O
a	O
trapping	O
layer	O
instead	O
of	O
a	O
floating	B-Algorithm
gate	I-Algorithm
,	O
but	O
its	O
use	O
was	O
limited	O
as	O
it	O
was	O
considered	O
inferior	O
to	O
a	O
floating	B-Algorithm
gate	I-Algorithm
.	O
</s>
<s>
It	O
had	O
a	O
device	O
structure	O
and	O
operating	O
principles	O
similar	O
to	O
floating-gate	B-Algorithm
(	O
FG	O
)	O
memory	O
,	O
but	O
the	O
main	O
difference	O
is	O
that	O
the	O
charges	O
are	O
stored	O
in	O
a	O
conducting	O
material	O
(	O
typically	O
a	O
doped	O
polysilicon	O
layer	O
)	O
in	O
FG	O
memory	O
,	O
whereas	O
CT	O
memory	O
stored	O
charges	O
in	O
localized	O
traps	O
within	O
a	O
dielectric	O
layer	O
(	O
typically	O
made	O
of	O
silicon	O
nitride	O
)	O
.	O
</s>
<s>
By	O
1974	O
,	O
charge	O
trap	O
technology	O
was	O
used	O
as	O
a	O
storage	O
mechanism	O
in	O
electrically	B-General_Concept
erasable	I-General_Concept
programmable	I-General_Concept
read-only	I-General_Concept
memory	I-General_Concept
(	O
EEPROM	B-General_Concept
)	O
,	O
and	O
was	O
an	O
alternative	O
to	O
the	O
standard	O
floating-gate	B-Algorithm
MOSFET	I-Algorithm
technology	O
.	O
</s>
<s>
Chen	O
of	O
Fairchild	O
Camera	O
and	O
Instrument	O
published	O
a	O
paper	O
detailing	O
the	O
invention	O
of	O
SONOS	B-Algorithm
,	O
a	O
MOSFET	B-Architecture
technology	O
with	O
far	O
less	O
demanding	O
program	O
and	O
erase	O
conditions	O
and	O
longer	O
charge	O
storage	O
.	O
</s>
<s>
This	O
improvement	O
led	O
to	O
manufacturable	O
EEPROM	B-General_Concept
devices	O
based	O
on	O
charge-trapping	O
SONOS	B-Algorithm
in	O
the	O
1980s	O
.	O
</s>
<s>
In	O
1991	O
,	O
Japanese	O
NEC	O
researchers	O
including	O
N	O
.	O
Kodama	O
,	O
K	O
.	O
Oyama	O
and	O
Hiroki	O
Shirai	O
developed	O
a	O
type	O
of	O
flash	B-Device
memory	I-Device
that	O
incorporated	O
a	O
charge	O
trap	O
method	O
.	O
</s>
<s>
In	O
1998	O
,	O
Israeli	O
engineer	O
Boaz	O
Eitan	O
of	O
Saifun	O
Semiconductors	O
(	O
later	O
acquired	O
by	O
Spansion	O
)	O
patented	O
a	O
flash	B-Device
memory	I-Device
technology	O
named	O
NROM	B-Algorithm
that	O
took	O
advantage	O
of	O
a	O
charge	O
trapping	O
layer	O
to	O
replace	O
the	O
floating	B-Algorithm
gate	I-Algorithm
used	O
in	O
conventional	O
flash	B-Device
memory	I-Device
designs	O
.	O
</s>
<s>
These	O
two	O
new	O
ideas	O
enabled	O
high	O
cycling	O
thus	O
allowing	O
reliable	O
charge	B-Algorithm
trap	I-Algorithm
flash	I-Algorithm
products	O
to	O
be	O
produced	O
for	O
the	O
first	O
time	O
since	O
the	O
charge	O
trapping	O
concept	O
was	O
invented	O
30	O
years	O
earlier	O
.	O
</s>
<s>
In	O
2000	O
,	O
an	O
Advanced	O
Micro	O
Devices	O
(	O
AMD	O
)	O
research	O
team	O
led	O
by	O
Richard	O
M	O
.	O
Fastow	O
,	O
Egyptian	O
engineer	O
Khaled	O
Z	O
.	O
Ahmed	O
and	O
Jordanian	O
engineer	O
Sameer	O
Haddad	O
(	O
who	O
later	O
joined	O
Spansion	O
)	O
demonstrated	O
a	O
charge	O
trap	O
mechanism	O
for	O
NOR	O
flash	B-Device
memory	I-Device
cells	O
.	O
</s>
<s>
That	O
year	O
,	O
AMD	O
(	O
in	O
a	O
division	O
later	O
spun	O
off	O
as	O
Spansion	O
)	O
announced	O
a	O
new	O
flash	B-Device
memory	I-Device
technology	O
it	O
called	O
"	O
MirrorBit	O
"	O
.	O
</s>
<s>
Spansion	O
used	O
this	O
product	O
to	O
reduce	O
manufacturing	O
costs	O
and	O
extend	O
the	O
density	O
range	O
of	O
NOR	O
Flash	B-Device
memory	I-Device
past	O
that	O
of	O
conventional	O
NOR	O
flash	O
and	O
to	O
match	O
the	O
cost	O
of	O
the	O
multi-level	B-Device
cell	I-Device
NOR	O
flash	O
being	O
manufactured	O
by	O
Intel	O
.	O
</s>
<s>
The	O
MirrorBit	O
cell	O
uses	O
a	O
charge	O
trapping	O
layer	O
not	O
only	O
as	O
a	O
substitute	O
for	O
a	O
conventional	O
floating	B-Algorithm
gate	I-Algorithm
,	O
but	O
it	O
also	O
takes	O
advantage	O
of	O
the	O
non-conducting	O
nature	O
of	O
the	O
charge	O
storage	O
nitride	O
to	O
allow	O
two	O
bits	O
to	O
share	O
the	O
same	O
memory	B-Algorithm
cell	I-Algorithm
.	O
</s>
<s>
Like	O
the	O
floating	B-Algorithm
gate	I-Algorithm
memory	B-Algorithm
cell	I-Algorithm
,	O
a	O
charge	O
trapping	O
cell	O
uses	O
a	O
variable	O
charge	O
between	O
the	O
control	O
gate	O
and	O
the	O
channel	O
to	O
change	O
the	O
threshold	O
voltage	O
of	O
the	O
transistor	O
.	O
</s>
<s>
The	O
mechanisms	O
to	O
modify	O
this	O
charge	O
are	O
relatively	O
similar	O
between	O
the	O
floating	B-Algorithm
gate	I-Algorithm
and	O
the	O
charge	O
trap	O
,	O
and	O
the	O
read	O
mechanisms	O
are	O
also	O
very	O
similar	O
.	O
</s>
<s>
In	O
a	O
charge	O
trapping	O
flash	O
,	O
electrons	O
are	O
stored	O
in	O
a	O
trapping	O
layer	O
just	O
as	O
they	O
are	O
stored	O
in	O
the	O
floating	B-Algorithm
gate	I-Algorithm
in	O
a	O
standard	O
flash	B-Device
memory	I-Device
,	O
EEPROM	B-General_Concept
,	O
or	O
EPROM	B-General_Concept
.	O
</s>
<s>
The	O
key	O
difference	O
is	O
that	O
the	O
charge	O
trapping	O
layer	O
is	O
an	O
insulator	O
,	O
while	O
the	O
floating	B-Algorithm
gate	I-Algorithm
is	O
a	O
conductor	O
.	O
</s>
<s>
High	O
write	O
loads	O
in	O
a	O
flash	B-Device
memory	I-Device
cause	O
stress	O
on	O
the	O
tunnel	O
oxide	O
layer	O
creating	O
small	O
disruptions	O
in	O
the	O
crystal	O
lattice	O
called	O
"	O
oxide	O
defects	O
"	O
.	O
</s>
<s>
If	O
a	O
large	O
number	O
of	O
such	O
disruptions	O
are	O
created	O
a	O
short	O
circuit	O
develops	O
between	O
the	O
floating	B-Algorithm
gate	I-Algorithm
and	O
the	O
transistor	O
's	O
channel	O
and	O
the	O
floating	B-Algorithm
gate	I-Algorithm
can	O
no	O
longer	O
hold	O
a	O
charge	O
.	O
</s>
<s>
This	O
is	O
the	O
root	O
cause	O
of	O
flash	O
wear-out	O
(	O
see	O
Flash	B-Device
memory	I-Device
#Memory	O
wear	O
)	O
,	O
which	O
is	O
specified	O
as	O
the	O
chip	O
's	O
“	O
endurance.	O
”	O
In	O
order	O
to	O
reduce	O
the	O
occurrence	O
of	O
such	O
short	O
circuits	O
,	O
floating	B-Algorithm
gate	I-Algorithm
flash	O
is	O
manufactured	O
using	O
a	O
thick	O
tunnel	O
oxide	O
(	O
~	O
100Å	O
)	O
,	O
but	O
this	O
slows	O
erase	O
when	O
Fowler-Nordheim	O
tunneling	O
is	O
used	O
and	O
forces	O
the	O
design	O
to	O
use	O
a	O
higher	O
tunneling	O
voltage	O
,	O
which	O
puts	O
new	O
burdens	O
on	O
other	O
parts	O
of	O
the	O
chip	O
.	O
</s>
<s>
Electrons	O
are	O
moved	O
onto	O
the	O
charge	O
trapping	O
layer	O
similarly	O
to	O
the	O
way	O
that	O
floating	B-Algorithm
gate	I-Algorithm
NOR	O
flash	O
is	O
programmed	O
,	O
through	O
channel	O
hot	O
electron	O
(	O
CHE	O
)	O
injection	O
mechanism	O
also	O
known	O
as	O
Hot-carrier	O
injection	O
.	O
</s>
<s>
Charge	O
trapping	O
flash	O
is	O
similar	O
in	O
manufacture	O
to	O
floating	B-Algorithm
gate	I-Algorithm
flash	O
with	O
certain	O
exceptions	O
that	O
serve	O
to	O
simplify	O
manufacturing	O
.	O
</s>
<s>
Both	O
floating	B-Algorithm
gate	I-Algorithm
flash	O
and	O
charge	O
trapping	O
flash	O
use	O
a	O
stacked	O
gate	O
structure	O
in	O
which	O
a	O
floating	B-Algorithm
gate	I-Algorithm
or	O
charge	O
trapping	O
layer	O
lies	O
immediately	O
above	O
the	O
channel	O
,	O
and	O
below	O
a	O
control	O
gate	O
.	O
</s>
<s>
The	O
floating	B-Algorithm
gate	I-Algorithm
or	O
charge	O
trapping	O
layer	O
is	O
insulated	O
from	O
the	O
channel	O
by	O
a	O
tunnel	O
oxide	O
layer	O
and	O
from	O
the	O
control	O
gate	O
by	O
a	O
gate	O
oxide	O
layer	O
.	O
</s>
<s>
Materials	O
for	O
all	O
of	O
these	O
layers	O
are	O
the	O
same	O
with	O
the	O
exception	O
of	O
the	O
storage	O
layer	O
,	O
which	O
is	O
conductive	O
polysilicon	O
for	O
the	O
floating	B-Algorithm
gate	I-Algorithm
structure	O
and	O
is	O
typically	O
silicon	O
nitride	O
for	O
the	O
charge	O
trap	O
.	O
</s>
<s>
Freescale	O
Semiconductor	O
manufactures	O
a	O
somewhat	O
similar	O
technology	O
the	O
company	O
calls	O
"	O
Thin	O
Film	O
Storage	O
"	O
in	O
its	O
microcontroller	B-Architecture
or	O
MCU	O
line	O
.	O
</s>
<s>
Like	O
the	O
more	O
conventional	O
silicon	O
nitride	O
charge	O
trap	O
,	O
electrons	O
do	O
not	O
flow	O
from	O
one	O
side	O
of	O
the	O
floating	B-Algorithm
gate	I-Algorithm
to	O
the	O
other	O
,	O
extending	O
the	O
cell	O
's	O
wear	O
.	O
</s>
<s>
Floating	B-Algorithm
gate	I-Algorithm
structures	O
have	O
required	O
more	O
elaborate	O
gate	O
dielectrics	O
for	O
the	O
past	O
few	O
process	O
generations	O
and	O
today	O
commonly	O
use	O
an	O
ONO	O
(	O
oxide-nitride-oxide	O
)	O
structure	O
which	O
is	O
more	O
complex	O
to	O
manufacture	O
and	O
is	O
unnecessary	O
in	O
a	O
charge-trapping	O
flash	O
.	O
</s>
<s>
One	O
advantage	O
of	O
the	O
nitride	O
layer	O
is	O
that	O
it	O
is	O
less	O
sensitive	O
to	O
high	O
temperature	O
fabrication	O
processing	O
than	O
is	O
the	O
polysilicon	O
used	O
in	O
a	O
floating	B-Algorithm
gate	I-Algorithm
.	O
</s>
<s>
In	O
a	O
marketing	O
brochure	O
Spansion	O
has	O
claimed	O
that	O
the	O
processing	O
cost	O
of	O
a	O
MirrorBit	O
NOR	O
flash	O
wafer	O
is	O
lower	O
than	O
that	O
of	O
a	O
conventional	O
floating	B-Algorithm
gate	I-Algorithm
wafer	O
since	O
there	O
are	O
10%	O
fewer	O
photolithography	O
mask	O
steps	O
,	O
and	O
40%	O
fewer	O
"	O
critical	O
"	O
steps	O
(	O
those	O
requiring	O
the	O
finest	O
resolution	O
,	O
and	O
therefore	O
the	O
most	O
expensive	O
photolithographic	O
equipment	O
)	O
.	O
</s>
<s>
Infineon	O
's	O
marketing	O
materials	O
showed	O
that	O
15%	O
fewer	O
mask	O
steps	O
were	O
required	O
to	O
make	O
charge	O
trapping	O
NAND	O
flash	O
than	O
to	O
manufacture	O
the	O
equivalent	O
floating	B-Algorithm
gate	I-Algorithm
product	O
.	O
</s>
<s>
Spansion	O
's	O
MirrorBit	O
Flash	O
and	O
Saifun	O
's	O
NROM	B-Algorithm
are	O
two	O
flash	B-Device
memories	I-Device
that	O
use	O
a	O
charge	O
trapping	O
mechanism	O
in	O
nitride	O
to	O
store	O
two	O
bits	O
onto	O
the	O
same	O
cell	O
effectively	O
doubling	O
the	O
memory	O
capacity	O
of	O
a	O
chip	O
.	O
</s>
<s>
The	O
technology	O
depends	O
on	O
a	O
SONOS	B-Algorithm
(	O
silicon	O
–	O
oxide	O
–	O
nitride	O
–	O
oxide	O
–	O
silicon	O
)	O
or	O
MONOS	O
(	O
metal-ONOS	O
)	O
capacitor	O
structure	O
,	O
storing	O
the	O
information	O
in	O
charge	O
traps	O
in	O
the	O
nitride	O
layer	O
.	O
</s>
<s>
Samsung	O
disclosed	O
two	O
cell	O
structures	O
:	O
TANOS	O
(	O
Titanium	O
,	O
Alumina	O
,	O
Nitride	O
,	O
Oxide	O
,	O
Silicon	O
)	O
for	O
40nm	O
,	O
where	O
researchers	O
believed	O
that	O
the	O
existing	O
3D	O
cap	O
structure	O
(	O
described	O
in	O
detail	O
later	O
in	O
this	O
article	O
)	O
could	O
not	O
be	O
manufactured	O
,	O
and	O
THNOS	O
,	O
in	O
which	O
the	O
aluminum	O
oxide	O
would	O
be	O
replaced	O
with	O
an	O
undisclosed	O
high-k	B-Algorithm
dielectric	I-Algorithm
material	O
.	O
</s>
<s>
The	O
high-k	B-Algorithm
material	O
was	O
expected	O
to	O
yield	O
longer	O
retention	O
times	O
than	O
the	O
aluminum	O
oxide	O
structure	O
.	O
</s>
<s>
In	O
a	O
cap	O
structure	O
the	O
control	O
gate	O
is	O
extended	O
to	O
form	O
a	O
barrier	O
between	O
adjacent	O
floating	B-Algorithm
gates	I-Algorithm
in	O
a	O
conventional	O
floating	B-Algorithm
gate	I-Algorithm
cell	O
.	O
</s>
<s>
As	O
processes	O
migrate	O
,	O
the	O
width	O
of	O
the	O
interface	O
of	O
the	O
control	O
gate	O
and	O
the	O
floating	B-Algorithm
gate	I-Algorithm
shrinks	O
in	O
proportion	O
to	O
the	O
square	O
of	O
the	O
shrink	O
,	O
and	O
the	O
spacing	O
between	O
floating	B-Algorithm
gates	I-Algorithm
shrinks	O
in	O
proportion	O
to	O
the	O
process	O
shrink	O
,	O
but	O
the	O
floating	B-Algorithm
gate	I-Algorithm
's	O
thickness	O
remains	O
the	O
same	O
(	O
the	O
thinner	O
the	O
floating	B-Algorithm
gate	I-Algorithm
is	O
made	O
the	O
less	O
tolerant	O
the	O
cell	O
becomes	O
to	O
electron	O
loss	O
)	O
.	O
</s>
<s>
This	O
means	O
that	O
the	O
coupling	O
between	O
adjacent	O
floating	B-Algorithm
gates	I-Algorithm
becomes	O
larger	O
than	O
the	O
coupling	O
between	O
the	O
control	O
gate	O
and	O
the	O
floating	B-Algorithm
gate	I-Algorithm
,	O
leading	O
to	O
data	O
corruption	O
between	O
adjacent	O
bits	O
.	O
</s>
<s>
For	O
this	O
reason	O
the	O
control	O
gate	O
in	O
modern	O
NAND	O
flash	O
has	O
been	O
reconfigured	O
to	O
cap	O
the	O
floating	B-Algorithm
gate	I-Algorithm
.	O
</s>
<s>
In	O
a	O
cap	O
structure	O
the	O
control	O
gate	O
is	O
extended	O
to	O
form	O
a	O
barrier	O
between	O
adjacent	O
floating	B-Algorithm
gates	I-Algorithm
in	O
a	O
conventional	O
floating	B-Algorithm
gate	I-Algorithm
cell	O
(	O
see	O
figure	O
5	O
)	O
.	O
</s>
<s>
This	O
serves	O
to	O
reduce	O
coupling	O
to	O
the	O
adjacent	O
floating	B-Algorithm
gate	I-Algorithm
while	O
increasing	O
the	O
coupling	O
between	O
the	O
floating	B-Algorithm
gate	I-Algorithm
and	O
the	O
control	O
gate	O
.	O
</s>
<s>
It	O
was	O
believed	O
in	O
2006	O
that	O
the	O
existing	O
floating	B-Algorithm
gate	I-Algorithm
cap	O
structure	O
could	O
not	O
be	O
manufactured	O
at	O
processes	O
smaller	O
than	O
the	O
50nm	O
node	O
due	O
to	O
difficulties	O
in	O
producing	O
the	O
complex	O
three-layer	O
ONO	O
gate	O
oxide	O
that	O
these	O
devices	O
require	O
.	O
</s>
<s>
This	O
implies	O
that	O
standard	O
device	O
structures	O
could	O
stay	O
in	O
place	O
until	O
the	O
industry	O
reaches	O
10nm	O
,	O
however	O
the	O
challenges	O
of	O
producing	O
a	O
reliable	O
floating	B-Algorithm
gate	I-Algorithm
become	O
more	O
severe	O
with	O
each	O
process	O
shrink	O
.	O
</s>
<s>
SONOS	B-Algorithm
using	O
a	O
simple	O
tunnel	O
oxide	O
,	O
however	O
,	O
is	O
not	O
suitable	O
for	O
NAND	O
application-once	O
electrons	O
are	O
trapped	O
in	O
deep	O
SiN	O
trap	O
levels	O
they	O
are	O
difficult	O
to	O
detrap	O
even	O
under	O
high	O
electric	O
field	O
.	O
</s>
<s>
Several	O
variations	O
of	O
SONOS	B-Algorithm
have	O
been	O
proposed	O
.	O
</s>
<s>
For	O
example	O
,	O
triple	O
ultra-thin	O
(	O
1	O
–	O
2	O
nm	O
)	O
layers	O
of	O
ONO	O
are	O
introduced	O
to	O
replace	O
the	O
single	O
oxide	O
(	O
BE-SONOS	O
)	O
[	O
H	O
.	O
T	O
.	O
Lue	O
,	O
et	O
al	O
,	O
IEDM	O
2005 ]	O
.	O
</s>
<s>
Later	O
BE-SONOS	O
is	O
added	O
high-K	B-Algorithm
(	O
Al2O3	O
)	O
and	O
metal	O
gate	O
to	O
enhance	O
the	O
erase	O
performances	O
,	O
the	O
so-called	O
BE-MANOS	O
[	O
S	O
.	O
C	O
.	O
Lai	O
,	O
et	O
al	O
,	O
NVSMW	O
2007 ]	O
.	O
</s>
<s>
It	O
is	O
suggested	O
to	O
add	O
a	O
buffer	O
oxide	O
in	O
between	O
high-K	B-Algorithm
Al2O3	O
and	O
SiN	O
to	O
improve	O
the	O
retention	O
.	O
</s>
