<s>
Channel	B-Algorithm
length	I-Algorithm
modulation	I-Algorithm
(	O
CLM	O
)	O
is	O
an	O
effect	O
in	O
field	O
effect	O
transistors	O
,	O
a	O
shortening	O
of	O
the	O
length	O
of	O
the	O
inverted	O
channel	O
region	O
with	O
increase	O
in	O
drain	O
bias	O
for	O
large	O
drain	O
biases	O
.	O
</s>
<s>
It	O
is	O
one	O
of	O
several	O
short-channel	O
effects	O
in	O
MOSFET	B-Architecture
scaling	O
.	O
</s>
<s>
Because	O
resistance	O
is	O
proportional	O
to	O
length	O
,	O
shortening	O
the	O
channel	O
decreases	O
its	O
resistance	O
,	O
causing	O
an	O
increase	O
in	O
current	O
with	O
increase	O
in	O
drain	O
bias	O
for	O
a	O
MOSFET	B-Architecture
operating	O
in	O
saturation	O
.	O
</s>
<s>
In	O
the	O
weak	O
inversion	O
region	O
,	O
the	O
influence	O
of	O
the	O
drain	O
analogous	O
to	O
channel-length	O
modulation	O
leads	O
to	O
poorer	O
device	O
turn	O
off	O
behavior	O
known	O
as	O
drain-induced	B-Algorithm
barrier	I-Algorithm
lowering	I-Algorithm
,	O
a	O
drain	O
induced	O
lowering	O
of	O
threshold	O
voltage	O
.	O
</s>
<s>
The	O
similarity	O
in	O
effect	O
upon	O
the	O
current	O
has	O
led	O
to	O
use	O
of	O
the	O
term	O
"	O
Early	O
effect	O
"	O
for	O
MOSFETs	B-Architecture
as	O
well	O
,	O
as	O
an	O
alternative	O
name	O
for	O
"	O
channel-length	O
modulation	O
"	O
.	O
</s>
<s>
In	O
textbooks	O
,	O
channel	B-Algorithm
length	I-Algorithm
modulation	I-Algorithm
in	O
active	O
mode	O
usually	O
is	O
described	O
using	O
the	O
Shichman	O
–	O
Hodges	O
model	O
,	O
accurate	O
only	O
for	O
old	O
technology	O
:	O
</s>
<s>
technology	O
parameter	O
sometimes	O
called	O
the	O
transconductance	O
coefficient	O
,	O
W	O
,	O
L	O
=	O
MOSFET	B-Architecture
width	O
and	O
length	O
,	O
=	O
gate-to-source	O
voltage	O
,	O
=	O
threshold	O
voltage	O
,	O
=	O
drain-to-source	O
voltage	O
,	O
,	O
and	O
λ	O
=	O
channel-length	O
modulation	O
parameter	O
.	O
</s>
<s>
Channel-length	O
modulation	O
is	O
important	O
because	O
it	O
decides	O
the	O
MOSFET	B-Architecture
output	O
resistance	O
,	O
an	O
important	O
parameter	O
in	O
circuit	O
design	O
of	O
current	O
mirrors	O
and	O
amplifiers	O
.	O
</s>
<s>
The	O
channel-length	O
modulation	O
parameter	O
usually	O
is	O
taken	O
to	O
be	O
inversely	O
proportional	O
to	O
MOSFET	B-Architecture
channel	O
length	O
L	O
,	O
as	O
shown	O
in	O
the	O
last	O
form	O
above	O
for	O
rO	O
:	O
</s>
<s>
For	O
a	O
65	B-Algorithm
nm	I-Algorithm
process	I-Algorithm
,	O
roughly	O
VE	O
≈	O
4	O
V/μm	O
.	O
</s>
<s>
The	O
effect	O
of	O
channel-length	O
modulation	O
upon	O
the	O
MOSFET	B-Architecture
output	O
resistance	O
varies	O
both	O
with	O
the	O
device	O
,	O
particularly	O
its	O
channel	O
length	O
,	O
and	O
with	O
the	O
applied	O
bias	O
.	O
</s>
<s>
The	O
main	O
factor	O
affecting	O
the	O
output	O
resistance	O
in	O
longer	O
MOSFETs	B-Architecture
is	O
channel	B-Algorithm
length	I-Algorithm
modulation	I-Algorithm
as	O
just	O
described	O
.	O
</s>
<s>
In	O
shorter	O
MOSFETs	B-Architecture
additional	O
factors	O
arise	O
such	O
as	O
:	O
drain-induced	B-Algorithm
barrier	I-Algorithm
lowering	I-Algorithm
(	O
which	O
lowers	O
the	O
threshold	O
voltage	O
,	O
increasing	O
the	O
current	O
and	O
decreasing	O
the	O
output	O
resistance	O
)	O
,	O
velocity	O
saturation	O
(	O
which	O
tends	O
to	O
limit	O
the	O
increase	O
in	O
channel	O
current	O
with	O
drain	O
voltage	O
,	O
thereby	O
increasing	O
the	O
output	O
resistance	O
)	O
and	O
ballistic	O
transport	O
(	O
which	O
modifies	O
the	O
collection	O
of	O
current	O
by	O
the	O
drain	O
,	O
and	O
modifies	O
drain-induced	B-Algorithm
barrier	I-Algorithm
lowering	I-Algorithm
so	O
as	O
to	O
increase	O
supply	O
of	O
carriers	O
to	O
the	O
pinch-off	O
region	O
,	O
increasing	O
the	O
current	O
and	O
decreasing	O
the	O
output	O
resistance	O
)	O
.	O
</s>
