<s>
Cell	O
is	O
a	O
multi-core	B-Architecture
microprocessor	B-Architecture
microarchitecture	O
that	O
combines	O
a	O
general-purpose	O
PowerPC	B-Architecture
core	B-General_Concept
of	O
modest	O
performance	O
with	O
streamlined	O
coprocessing	B-General_Concept
elements	O
which	O
greatly	O
accelerate	O
multimedia	O
and	O
vector	B-Operating_System
processing	I-Operating_System
applications	O
,	O
as	O
well	O
as	O
many	O
other	O
forms	O
of	O
dedicated	O
computation	O
.	O
</s>
<s>
The	O
first	O
major	O
commercial	O
application	O
of	O
Cell	O
was	O
in	O
Sony	O
's	O
PlayStation	B-Operating_System
3	I-Operating_System
game	B-Device
console	I-Device
,	O
released	O
in	O
2006	O
.	O
</s>
<s>
In	O
May	O
2008	O
,	O
the	O
Cell-based	O
IBM	B-General_Concept
Roadrunner	I-General_Concept
supercomputer	B-Architecture
became	O
the	O
first	O
TOP500	B-Operating_System
LINPACK	B-Device
sustained	O
1.0	O
petaflops	O
system	O
.	O
</s>
<s>
Mercury	B-Application
Computer	I-Application
Systems	I-Application
also	O
developed	O
designs	O
based	O
on	O
the	O
Cell	O
.	O
</s>
<s>
The	O
Cell	O
architecture	O
includes	O
a	O
memory	B-Operating_System
coherence	I-Operating_System
architecture	O
that	O
emphasizes	O
power	O
efficiency	O
,	O
prioritizes	O
bandwidth	O
over	O
low	O
latency	O
,	O
and	O
favors	O
peak	O
computational	O
throughput	O
over	O
simplicity	O
of	O
program	O
code	O
.	O
</s>
<s>
For	O
these	O
reasons	O
,	O
Cell	O
is	O
widely	O
regarded	O
as	O
a	O
challenging	O
environment	O
for	O
software	B-General_Concept
development	I-General_Concept
.	O
</s>
<s>
IBM	O
provides	O
a	O
Linux-based	O
development	O
platform	O
to	O
help	O
developers	O
program	O
for	O
Cell	O
chips	O
.	O
</s>
<s>
The	O
Cell	O
was	O
designed	O
over	O
a	O
period	O
of	O
four	O
years	O
,	O
using	O
enhanced	O
versions	O
of	O
the	O
design	O
tools	O
for	O
the	O
POWER4	B-Device
processor	O
.	O
</s>
<s>
An	O
early	O
patent	O
version	O
of	O
the	O
Broadband	O
Engine	O
was	O
shown	O
to	O
be	O
a	O
chip	O
package	O
comprising	O
four	O
"	O
Processing	O
Elements	O
"	O
,	O
which	O
was	O
the	O
patent	O
's	O
description	O
for	O
what	O
is	O
now	O
known	O
as	O
the	O
Power	B-General_Concept
Processing	I-General_Concept
Element	I-General_Concept
(	O
PPE	O
)	O
.	O
</s>
<s>
This	O
smaller	O
design	O
,	O
the	O
Cell	O
Broadband	O
Engine	O
or	O
Cell/BE	O
was	O
fabricated	O
using	O
a	O
90	O
nm	O
SOI	B-Algorithm
process	O
.	O
</s>
<s>
In	O
March	O
2007	O
,	O
IBM	O
announced	O
that	O
the	O
65	O
nm	O
version	O
of	O
Cell/BE	O
is	O
in	O
production	O
at	O
its	O
plant	O
(	O
at	O
the	O
time	O
,	O
now	O
GlobalFoundries	O
 '	O
)	O
in	O
East	O
Fishkill	O
,	O
New	O
York	O
,	O
with	O
Bandai	O
Namco	O
Entertainment	O
using	O
the	O
Cell/BE	O
processor	O
for	O
their	O
357	B-General_Concept
arcade	O
board	O
as	O
well	O
as	O
the	O
subsequent	O
369	O
.	O
</s>
<s>
In	O
May	O
2008	O
,	O
IBM	O
introduced	O
the	O
high-performance	O
double-precision	O
floating-point	O
version	O
of	O
the	O
Cell	O
processor	O
,	O
the	O
PowerXCell	O
8i	O
,	O
at	O
the	O
65nm	B-Algorithm
feature	O
size	O
.	O
</s>
<s>
In	O
May	O
2008	O
,	O
an	O
Opteron	B-General_Concept
-	O
and	O
PowerXCell	O
8i-based	O
supercomputer	B-Architecture
,	O
the	O
IBM	B-General_Concept
Roadrunner	I-General_Concept
system	O
,	O
became	O
the	O
world	O
's	O
first	O
system	O
to	O
achieve	O
one	O
petaFLOPS	O
,	O
and	O
was	O
the	O
fastest	B-Operating_System
computer	I-Operating_System
in	O
the	O
world	O
until	O
third	O
quarter	O
2009	O
.	O
</s>
<s>
The	O
world	O
's	O
three	O
most	O
energy-efficient	O
supercomputers	B-Architecture
,	O
as	O
represented	O
by	O
the	O
Green500	B-Application
list	O
,	O
are	O
similarly	O
based	O
on	O
the	O
PowerXCell	O
8i	O
.	O
</s>
<s>
In	O
August	O
2009	O
the	O
45nm	B-Algorithm
Cell	O
processor	O
was	O
introduced	O
in	O
concert	O
with	O
Sony	O
's	O
PlayStation	B-Operating_System
3	I-Operating_System
Slim	O
.	O
</s>
<s>
On	O
May	O
17	O
,	O
2005	O
,	O
Sony	O
Computer	O
Entertainment	O
confirmed	O
some	O
specifications	O
of	O
the	O
Cell	O
processor	O
that	O
would	O
be	O
shipping	O
in	O
the	O
then-forthcoming	O
PlayStation	B-Operating_System
3	I-Operating_System
console	O
.	O
</s>
<s>
This	O
Cell	O
configuration	O
has	O
one	O
PPE	O
on	O
the	O
core	B-General_Concept
,	O
with	O
eight	O
physical	O
SPEs	O
in	O
silicon	O
.	O
</s>
<s>
In	O
the	O
PlayStation	B-Operating_System
3	I-Operating_System
,	O
one	O
SPE	O
is	O
locked-out	O
during	O
the	O
test	O
process	O
,	O
a	O
practice	O
which	O
helps	O
to	O
improve	O
manufacturing	O
yields	O
,	O
and	O
another	O
one	O
is	O
reserved	O
for	O
the	O
OS	O
,	O
leaving	O
6	O
free	O
SPEs	O
to	O
be	O
used	O
by	O
games	O
 '	O
code	O
.	O
</s>
<s>
The	O
introductory	O
design	O
is	O
fabricated	O
using	O
a	O
90nm	O
SOI	B-Algorithm
process	O
,	O
with	O
initial	O
volume	O
production	O
slated	O
for	O
IBM	O
's	O
facility	O
in	O
East	O
Fishkill	O
,	O
New	O
York	O
.	O
</s>
<s>
The	O
relationship	O
between	O
cores	B-Architecture
and	O
threads	B-Operating_System
is	O
a	O
common	O
source	O
of	O
confusion	O
.	O
</s>
<s>
The	O
PPE	O
core	B-General_Concept
is	O
dual	B-Operating_System
threaded	I-Operating_System
and	O
manifests	O
in	O
software	O
as	O
two	O
independent	O
threads	B-Operating_System
of	O
execution	O
while	O
each	O
active	O
SPE	O
manifests	O
as	O
a	O
single	B-Operating_System
thread	I-Operating_System
.	O
</s>
<s>
In	O
the	O
PlayStation	B-Operating_System
3	I-Operating_System
configuration	O
as	O
described	O
by	O
Sony	O
,	O
the	O
Cell	O
processor	O
provides	O
nine	O
independent	O
threads	B-Operating_System
of	O
execution	O
.	O
</s>
<s>
On	O
June	O
28	O
,	O
2005	O
,	O
IBM	O
and	O
Mercury	B-Application
Computer	I-Application
Systems	I-Application
announced	O
a	O
partnership	O
agreement	O
to	O
build	O
Cell-based	O
computer	O
systems	O
for	O
embedded	B-Architecture
applications	O
such	O
as	O
medical	B-Application
imaging	I-Application
,	O
industrial	O
inspection	O
,	O
aerospace	O
and	O
defense	O
,	O
seismic	O
processing	O
,	O
and	O
telecommunications	O
.	O
</s>
<s>
Mercury	O
has	O
since	O
then	O
released	O
blades	B-Architecture
,	O
conventional	O
rack	B-Application
servers	I-Application
and	O
PCI	O
Express	O
accelerator	O
boards	O
with	O
Cell	O
processors	O
.	O
</s>
<s>
In	O
the	O
fall	O
of	O
2006	O
,	O
IBM	O
released	O
the	O
QS20	O
blade	B-Architecture
module	I-Architecture
using	O
double	O
Cell	O
BE	O
processors	O
for	O
tremendous	O
performance	O
in	O
certain	O
applications	O
,	O
reaching	O
a	O
peak	O
of	O
410gigaFLOPS	O
in	O
FP8	O
quarter	O
precision	O
per	O
module	O
.	O
</s>
<s>
The	O
QS22	B-General_Concept
based	O
on	O
the	O
PowerXCell	O
8i	O
processor	O
was	O
used	O
for	O
the	O
IBM	B-General_Concept
Roadrunner	I-General_Concept
supercomputer	B-Architecture
.	O
</s>
<s>
Sony	O
's	O
high-performance	O
media	O
computing	O
server	O
ZEGO	B-General_Concept
uses	O
a	O
3.2GHz	O
Cell/B.E	O
processor	O
.	O
</s>
<s>
The	O
Cell	O
Broadband	O
Engine	O
,	O
or	O
Cell	O
as	O
it	O
is	O
more	O
commonly	O
known	O
,	O
is	O
a	O
microprocessor	B-Architecture
intended	O
as	O
a	O
hybrid	O
of	O
conventional	O
desktop	O
processors	O
(	O
such	O
as	O
the	O
Athlon	O
64	O
,	O
and	O
Core	B-Device
2	I-Device
families	O
)	O
and	O
more	O
specialized	O
high-performance	O
processors	O
,	O
such	O
as	O
the	O
NVIDIA	O
and	O
ATI	O
graphics-processors	O
(	O
GPUs	B-Architecture
)	O
.	O
</s>
<s>
The	O
longer	O
name	O
indicates	O
its	O
intended	O
use	O
,	O
namely	O
as	O
a	O
component	O
in	O
current	O
and	O
future	O
online	O
distribution	O
systems	O
;	O
as	O
such	O
it	O
may	O
be	O
utilized	O
in	O
high-definition	B-Device
displays	I-Device
and	O
recording	O
equipment	O
,	O
as	O
well	O
as	O
HDTV	B-Device
systems	O
.	O
</s>
<s>
Additionally	O
the	O
processor	O
may	O
be	O
suited	O
to	O
digital	B-Algorithm
imaging	I-Algorithm
systems	O
(	O
medical	O
,	O
scientific	O
,	O
etc	O
.	O
)	O
</s>
<s>
and	O
physical	B-Algorithm
simulation	I-Algorithm
(	O
e.g.	O
,	O
scientific	O
and	O
structural	O
engineering	O
modeling	O
)	O
.	O
</s>
<s>
In	O
a	O
simple	O
analysis	O
,	O
the	O
Cell	O
processor	O
can	O
be	O
split	O
into	O
four	O
components	O
:	O
external	O
input	O
and	O
output	O
structures	O
,	O
the	O
main	O
processor	O
called	O
the	O
Power	B-General_Concept
Processing	I-General_Concept
Element	I-General_Concept
(	O
PPE	O
)	O
(	O
a	O
two-way	O
simultaneous-multithreaded	B-Operating_System
PowerPC	B-Architecture
2.02	I-Architecture
core	B-General_Concept
)	O
,	O
eight	O
fully	O
functional	O
co-processors	B-General_Concept
called	O
the	O
Synergistic	O
Processing	O
Elements	O
,	O
or	O
SPEs	O
,	O
and	O
a	O
specialized	O
high-bandwidth	O
circular	B-Architecture
data	I-Architecture
bus	I-Architecture
connecting	O
the	O
PPE	O
,	O
input/output	O
elements	O
and	O
the	O
SPEs	O
,	O
called	O
the	O
Element	O
Interconnect	B-General_Concept
Bus	B-General_Concept
or	O
EIB	O
.	O
</s>
<s>
To	O
achieve	O
the	O
high	O
performance	O
needed	O
for	O
mathematically	O
intensive	O
tasks	O
,	O
such	O
as	O
decoding/encoding	O
MPEG	O
streams	O
,	O
generating	O
or	O
transforming	O
three-dimensional	O
data	O
,	O
or	O
undertaking	O
Fourier	O
analysis	O
of	O
data	O
,	O
the	O
Cell	O
processor	O
marries	O
the	O
SPEs	O
and	O
the	O
PPE	O
via	O
EIB	O
to	O
give	O
access	O
,	O
via	O
fully	O
cache	B-General_Concept
coherent	O
DMA	B-General_Concept
(	O
direct	B-General_Concept
memory	I-General_Concept
access	I-General_Concept
)	O
,	O
to	O
both	O
main	O
memory	O
and	O
to	O
other	O
external	O
data	O
storage	O
.	O
</s>
<s>
To	O
make	O
the	O
best	O
of	O
EIB	O
,	O
and	O
to	O
overlap	O
computation	O
and	O
data	O
transfer	O
,	O
each	O
of	O
the	O
nine	O
processing	O
elements	O
(	O
PPE	O
and	O
SPEs	O
)	O
is	O
equipped	O
with	O
a	O
DMA	B-General_Concept
engine	I-General_Concept
.	O
</s>
<s>
Since	O
the	O
SPE	O
's	O
load/store	B-General_Concept
instructions	I-General_Concept
can	O
only	O
access	O
its	O
own	O
local	O
scratchpad	B-General_Concept
memory	I-General_Concept
,	O
each	O
SPE	O
entirely	O
depends	O
on	O
DMAs	O
to	O
transfer	O
data	O
to	O
and	O
from	O
the	O
main	O
memory	O
and	O
other	O
SPEs	O
 '	O
local	O
memories	O
.	O
</s>
<s>
A	O
DMA	B-General_Concept
operation	O
can	O
transfer	O
either	O
a	O
single	O
block	O
area	O
of	O
size	O
up	O
to	O
16KB	O
,	O
or	O
a	O
list	O
of	O
2	O
to	O
2048	O
such	O
blocks	O
.	O
</s>
<s>
One	O
of	O
the	O
major	O
design	O
decisions	O
in	O
the	O
architecture	O
of	O
Cell	O
is	O
the	O
use	O
of	O
DMAs	O
as	O
a	O
central	O
means	O
of	O
intra-chip	O
data	O
transfer	O
,	O
with	O
a	O
view	O
to	O
enabling	O
maximal	O
asynchrony	O
and	O
concurrency	B-Operating_System
in	O
data	O
processing	O
inside	O
a	O
chip	O
.	O
</s>
<s>
The	O
PPE	O
,	O
which	O
is	O
capable	O
of	O
running	O
a	O
conventional	O
operating	B-General_Concept
system	I-General_Concept
,	O
has	O
control	O
over	O
the	O
SPEs	O
and	O
can	O
start	O
,	O
stop	O
,	O
interrupt	O
,	O
and	O
schedule	O
processes	O
running	O
on	O
the	O
SPEs	O
.	O
</s>
<s>
Unlike	O
SPEs	O
,	O
the	O
PPE	O
can	O
read	O
and	O
write	O
the	O
main	O
memory	O
and	O
the	O
local	O
memories	O
of	O
SPEs	O
through	O
the	O
standard	O
load/store	B-General_Concept
instructions	I-General_Concept
.	O
</s>
<s>
Despite	O
having	O
Turing	B-Algorithm
complete	I-Algorithm
architectures	O
,	O
the	O
SPEs	O
are	O
not	O
fully	O
autonomous	O
and	O
require	O
the	O
PPE	O
to	O
prime	O
them	O
before	O
they	O
can	O
do	O
any	O
useful	O
work	O
.	O
</s>
<s>
As	O
most	O
of	O
the	O
"	O
horsepower	O
"	O
of	O
the	O
system	O
comes	O
from	O
the	O
synergistic	O
processing	O
elements	O
,	O
the	O
use	O
of	O
DMA	B-General_Concept
as	O
a	O
method	O
of	O
data	O
transfer	O
and	O
the	O
limited	O
local	O
memory	O
footprint	O
of	O
each	O
SPE	O
pose	O
a	O
major	O
challenge	O
to	O
software	O
developers	O
who	O
wish	O
to	O
make	O
the	O
most	O
of	O
this	O
horsepower	O
,	O
demanding	O
careful	O
hand-tuning	O
of	O
programs	O
to	O
extract	O
maximal	O
performance	O
from	O
this	O
CPU	B-Device
.	O
</s>
<s>
The	O
PPE	O
and	O
bus	B-General_Concept
architecture	O
includes	O
various	O
modes	O
of	O
operation	O
giving	O
different	O
levels	O
of	O
memory	B-General_Concept
protection	I-General_Concept
,	O
allowing	O
areas	O
of	O
memory	O
to	O
be	O
protected	O
from	O
access	O
by	O
specific	O
processes	O
running	O
on	O
the	O
SPEs	O
or	O
the	O
PPE	O
.	O
</s>
<s>
Both	O
the	O
PPE	O
and	O
SPE	O
are	O
RISC	B-Architecture
architectures	I-Architecture
with	O
a	O
fixed-width	O
32-bit	O
instruction	O
format	O
.	O
</s>
<s>
The	O
PPE	O
contains	O
a	O
64-bit	O
general	O
purpose	O
register	O
set	O
(	O
GPR	O
)	O
,	O
a	O
64-bit	O
floating-point	O
register	O
set	O
(	O
FPR	O
)	O
,	O
and	O
a	O
128-bit	O
Altivec	B-General_Concept
register	O
set	O
.	O
</s>
<s>
These	O
can	O
be	O
used	O
for	O
scalar	O
data	O
types	O
ranging	O
from	O
8-bits	O
to	O
64-bits	O
in	O
size	O
or	O
for	O
SIMD	B-Device
computations	O
on	O
a	O
variety	O
of	O
integer	O
and	O
floating-point	O
formats	O
.	O
</s>
<s>
In	O
2008	O
,	O
IBM	O
announced	O
a	O
revised	O
variant	O
of	O
the	O
Cell	O
called	O
the	O
PowerXCell	O
8i	O
,	O
which	O
is	O
available	O
in	O
QS22	B-General_Concept
Blade	B-General_Concept
Servers	I-General_Concept
from	O
IBM	O
.	O
</s>
<s>
The	O
PowerXCell	O
is	O
manufactured	O
on	O
a	O
65	O
nm	O
process	O
,	O
and	O
adds	O
support	O
for	O
up	O
to	O
32GB	O
of	O
slotted	O
DDR2	O
memory	O
,	O
as	O
well	O
as	O
dramatically	O
improving	O
double-precision	O
floating-point	O
performance	O
on	O
the	O
SPEs	O
from	O
a	O
peak	O
of	O
about	O
12.8GFLOPS	O
to	O
102.4GFLOPS	O
total	O
for	O
eight	O
SPEs	O
,	O
which	O
,	O
coincidentally	O
,	O
is	O
the	O
same	O
peak	O
performance	O
as	O
the	O
NEC	B-Device
SX-9	I-Device
vector	B-Operating_System
processor	I-Operating_System
released	O
around	O
the	O
same	O
time	O
.	O
</s>
<s>
The	O
IBM	B-General_Concept
Roadrunner	I-General_Concept
supercomputer	B-Architecture
,	O
the	O
world	O
's	O
fastest	O
during	O
2008	O
–	O
2009	O
,	O
consisted	O
of	O
12,240	O
PowerXCell	O
8i	O
processors	O
,	O
along	O
with	O
6,562	O
AMD	B-General_Concept
Opteron	I-General_Concept
processors	O
.	O
</s>
<s>
The	O
PowerXCell	O
8i	O
powered	O
super	B-Architecture
computers	I-Architecture
also	O
dominated	O
all	O
of	O
the	O
top	O
6	O
"	O
greenest	O
"	O
systems	O
in	O
the	O
Green500	B-Application
list	O
,	O
with	O
highest	O
MFLOPS/Watt	O
ratio	O
supercomputers	B-Architecture
in	O
the	O
world	O
.	O
</s>
<s>
Beside	O
the	O
QS22	B-General_Concept
and	O
supercomputers	B-Architecture
,	O
the	O
PowerXCell	O
processor	O
is	O
also	O
available	O
as	O
an	O
accelerator	O
on	O
a	O
PCI	O
Express	O
card	O
and	O
is	O
used	O
as	O
the	O
core	B-General_Concept
processor	O
in	O
the	O
QPACE	B-General_Concept
project	O
.	O
</s>
<s>
While	O
the	O
Cell	O
chip	O
can	O
have	O
a	O
number	O
of	O
different	O
configurations	O
,	O
the	O
basic	O
configuration	O
is	O
a	O
multi-core	B-Architecture
chip	O
composed	O
of	O
one	O
"	O
Power	O
Processor	O
Element	O
"	O
(	O
"	O
PPE	O
"	O
)	O
(	O
sometimes	O
called	O
"	O
Processing	O
Element	O
"	O
,	O
or	O
"	O
PE	O
"	O
)	O
,	O
and	O
multiple	O
"	O
Synergistic	O
Processing	O
Elements	O
"	O
(	O
"	O
SPE	O
"	O
)	O
.	O
</s>
<s>
The	O
PPE	O
and	O
SPEs	O
are	O
linked	O
together	O
by	O
an	O
internal	O
high	O
speed	O
bus	B-General_Concept
dubbed	O
"	O
Element	O
Interconnect	B-General_Concept
Bus	B-General_Concept
"	O
(	O
"	O
EIB	O
"	O
)	O
.	O
</s>
<s>
The	O
PPE	O
is	O
the	O
PowerPC	B-Architecture
based	O
,	O
dual-issue	O
in-order	O
two-way	O
simultaneous-multithreaded	B-Operating_System
CPU	B-Architecture
core	I-Architecture
with	O
a	O
23-stage	O
pipeline	O
acting	O
as	O
the	O
controller	O
for	O
the	O
eight	O
SPEs	O
,	O
which	O
handle	O
most	O
of	O
the	O
computational	O
workload	O
.	O
</s>
<s>
The	O
PPE	O
will	O
work	O
with	O
conventional	O
operating	B-General_Concept
systems	I-General_Concept
due	O
to	O
its	O
similarity	O
to	O
other	O
64-bit	O
PowerPC	B-Architecture
processors	I-Architecture
,	O
while	O
the	O
SPEs	O
are	O
designed	O
for	O
vectorized	O
floating	O
point	O
code	O
execution	O
.	O
</s>
<s>
The	O
PPE	O
contains	O
a	O
32	O
KiB	O
level	O
1	O
instruction	O
cache	B-General_Concept
,	O
a	O
32	O
KiB	O
level	O
1	O
data	B-General_Concept
cache	I-General_Concept
,	O
and	O
a	O
512	O
KiB	O
level	O
2	O
cache	B-General_Concept
.	O
</s>
<s>
The	O
size	O
of	O
a	O
cache	B-General_Concept
line	O
is	O
128	O
bytes	O
in	O
all	O
caches	O
.	O
</s>
<s>
Additionally	O
,	O
IBM	O
has	O
included	O
an	O
AltiVec	B-General_Concept
(	O
VMX	O
)	O
unit	O
which	O
is	O
fully	O
pipelined	O
for	O
single	O
precision	O
floating	O
point	O
(	O
Altivec	B-General_Concept
1	O
does	O
not	O
support	O
double	O
precision	O
floating-point	O
vectors	O
.	O
</s>
<s>
)	O
,	O
32-bit	O
Fixed	O
Point	O
Unit	O
(	O
FXU	O
)	O
with	O
64-bit	O
register	B-General_Concept
file	I-General_Concept
per	O
thread	B-Operating_System
,	O
Load	B-Architecture
and	I-Architecture
Store	I-Architecture
Unit	O
(	O
LSU	O
)	O
,	O
64-bit	O
Floating-Point	B-General_Concept
Unit	I-General_Concept
(	O
FPU	O
)	O
,	O
Branch	O
Unit	O
(	O
BRU	O
)	O
and	O
Branch	O
Execution	O
Unit(BXU )	O
.	O
</s>
<s>
IU	O
contains	O
L1	O
instruction	O
cache	B-General_Concept
,	O
branch	B-General_Concept
prediction	I-General_Concept
hardware	O
,	O
instruction	O
buffers	O
,	O
and	O
dependency	O
checking	O
logic	O
.	O
</s>
<s>
XU	O
contains	O
integer	O
execution	O
units	O
(	O
FXU	O
)	O
and	O
load-store	B-Architecture
unit	I-Architecture
(	O
LSU	O
)	O
.	O
</s>
<s>
The	O
PPE	O
was	O
designed	O
specifically	O
for	O
the	O
Cell	O
processor	O
but	O
during	O
development	O
,	O
Microsoft	O
approached	O
IBM	O
wanting	O
a	O
high-performance	O
processor	O
core	B-General_Concept
for	O
its	O
Xbox	B-Operating_System
360	I-Operating_System
.	O
</s>
<s>
IBM	O
complied	O
and	O
made	O
the	O
tri-core	B-Architecture
Xenon	B-Device
processor	I-Device
,	O
based	O
on	O
a	O
slightly	O
modified	O
version	O
of	O
the	O
PPE	O
with	O
added	O
VMX128	B-General_Concept
extensions	O
.	O
</s>
<s>
Each	O
SPE	O
is	O
a	O
dual	O
issue	O
in	O
order	O
processor	O
composed	O
of	O
a	O
"	O
Synergistic	O
Processing	O
Unit	O
"	O
,	O
SPU	O
,	O
and	O
a	O
"	O
Memory	O
Flow	O
Controller	O
"	O
,	O
MFC	O
(	O
DMA	B-General_Concept
,	O
MMU	B-General_Concept
,	O
and	O
bus	B-General_Concept
interface	O
)	O
.	O
</s>
<s>
SPEs	O
do	O
not	O
have	O
any	O
branch	B-General_Concept
prediction	I-General_Concept
hardware	O
(	O
hence	O
there	O
is	O
a	O
heavy	O
burden	O
on	O
the	O
compiler	O
)	O
.	O
</s>
<s>
Each	O
SPE	O
has	O
6	O
execution	O
units	O
divided	O
among	O
odd	O
and	O
even	O
pipelines	O
on	O
each	O
SPE	O
:	O
The	O
SPU	O
runs	O
a	O
specially	O
developed	O
instruction	B-General_Concept
set	I-General_Concept
(	O
ISA	O
)	O
with	O
128-bit	O
SIMD	B-Device
organization	O
for	O
single	O
and	O
double	O
precision	O
instructions	O
.	O
</s>
<s>
With	O
the	O
current	O
generation	O
of	O
the	O
Cell	O
,	O
each	O
SPE	O
contains	O
a	O
256KiB	O
embedded	B-Architecture
SRAM	O
for	O
instruction	O
and	O
data	O
,	O
called	O
"	B-General_Concept
Local	I-General_Concept
Storage	I-General_Concept
"	I-General_Concept
(	O
not	O
to	O
be	O
mistaken	O
for	O
"	O
Local	O
Memory	O
"	O
in	O
Sony	O
's	O
documents	O
that	O
refer	O
to	O
the	O
VRAM	O
)	O
which	O
is	O
visible	O
to	O
the	O
PPE	O
and	O
can	O
be	O
addressed	O
directly	O
by	O
software	O
.	O
</s>
<s>
The	O
local	O
store	O
does	O
not	O
operate	O
like	O
a	O
conventional	O
CPU	B-General_Concept
cache	I-General_Concept
since	O
it	O
is	O
neither	O
transparent	O
to	O
software	O
nor	O
does	O
it	O
contain	O
hardware	O
structures	O
that	O
predict	O
which	O
data	O
to	O
load	O
.	O
</s>
<s>
The	O
SPEs	O
contain	O
a	O
128-bit	O
,	O
128-entry	O
register	B-General_Concept
file	I-General_Concept
and	O
measures	O
14.5mm2	O
on	O
a	O
90nm	O
process	O
.	O
</s>
<s>
Note	O
that	O
the	O
SPU	O
cannot	O
directly	O
access	O
system	O
memory	O
;	O
the	O
64-bit	O
virtual	O
memory	O
addresses	O
formed	O
by	O
the	O
SPU	O
must	O
be	O
passed	O
from	O
the	O
SPU	O
to	O
the	O
SPE	O
memory	O
flow	O
controller	O
(	O
MFC	O
)	O
to	O
set	O
up	O
a	O
DMA	B-General_Concept
operation	O
within	O
the	O
system	O
address	O
space	O
.	O
</s>
<s>
In	O
one	O
typical	O
usage	O
scenario	O
,	O
the	O
system	O
will	O
load	O
the	O
SPEs	O
with	O
small	O
programs	O
(	O
similar	O
to	O
threads	B-Operating_System
)	O
,	O
chaining	O
the	O
SPEs	O
together	O
to	O
handle	O
each	O
step	O
in	O
a	O
complex	O
operation	O
.	O
</s>
<s>
Compared	O
to	O
its	O
personal	B-Device
computer	I-Device
contemporaries	O
,	O
the	O
relatively	O
high	O
overall	O
floating-point	O
performance	O
of	O
a	O
Cell	O
processor	O
seemingly	O
dwarfs	O
the	O
abilities	O
of	O
the	O
SIMD	B-Device
unit	O
in	O
CPUs	B-Device
like	O
the	O
Pentium	B-General_Concept
4	I-General_Concept
and	O
the	O
Athlon	O
64	O
.	O
</s>
<s>
Unlike	O
a	O
Cell	O
processor	O
,	O
such	O
desktop	O
CPUs	B-Device
are	O
more	O
suited	O
to	O
the	O
general-purpose	O
software	O
usually	O
run	O
on	O
personal	B-Device
computers	I-Device
.	O
</s>
<s>
In	O
addition	O
to	O
executing	O
multiple	O
instructions	O
per	O
clock	O
,	O
processors	O
from	O
Intel	O
and	O
AMD	O
feature	O
branch	B-General_Concept
predictors	I-General_Concept
.	O
</s>
<s>
For	O
double-precision	O
floating-point	O
operations	O
,	O
as	O
sometimes	O
used	O
in	O
personal	B-Device
computers	I-Device
and	O
often	O
used	O
in	O
scientific	O
computing	O
,	O
Cell	O
performance	O
drops	O
by	O
an	O
order	O
of	O
magnitude	O
,	O
but	O
still	O
reaches	O
20.8GFLOPS	O
(	O
1.8GFLOPS	O
per	O
SPE	O
,	O
6.4GFLOPS	O
per	O
PPE	O
)	O
.	O
</s>
<s>
Toshiba	O
has	O
developed	O
a	O
co-processor	B-General_Concept
powered	O
by	O
four	O
SPEs	O
,	O
but	O
no	O
PPE	O
,	O
called	O
the	O
SpursEngine	B-General_Concept
designed	O
to	O
accelerate	O
3D	O
and	O
movie	O
effects	O
in	O
consumer	O
electronics	O
.	O
</s>
<s>
The	O
EIB	O
is	O
a	O
communication	O
bus	B-General_Concept
internal	O
to	O
the	O
Cell	O
processor	O
which	O
connects	O
the	O
various	O
on-chip	O
system	O
elements	O
:	O
the	O
PPE	O
processor	O
,	O
the	O
memory	O
controller	O
(	O
MIC	O
)	O
,	O
the	O
eight	O
SPE	O
coprocessors	B-General_Concept
,	O
and	O
two	O
off-chip	O
I/O	O
interfaces	O
,	O
for	O
a	O
total	O
of	O
12	O
participants	O
in	O
the	B-Operating_System
PS3	I-Operating_System
(	O
the	O
number	O
of	O
SPU	O
can	O
vary	O
in	O
industrial	O
applications	O
)	O
.	O
</s>
<s>
At	O
maximum	O
concurrency	B-Operating_System
,	O
with	O
three	O
active	O
transactions	O
on	O
each	O
of	O
the	O
four	O
rings	O
,	O
the	O
peak	O
instantaneous	O
EIB	O
bandwidth	O
is	O
96	O
bytes	O
per	O
clock	O
(	O
12	O
concurrent	O
transactions	O
×	O
16	O
bytes	O
wide	O
/	O
2	O
system	O
clocks	O
per	O
transfer	O
)	O
.	O
</s>
<s>
IBM	O
Senior	O
Engineer	O
David	O
Krolak	O
,	O
EIB	O
lead	O
designer	O
,	O
explains	O
the	O
concurrency	B-Operating_System
model	O
:	O
</s>
<s>
Each	O
SPU	O
processor	O
contains	O
a	O
dedicated	O
DMA	B-General_Concept
management	O
queue	O
capable	O
of	O
scheduling	O
long	O
sequences	O
of	O
transactions	O
to	O
various	O
endpoints	O
without	O
interfering	O
with	O
the	O
SPU	O
's	O
ongoing	O
computations	O
;	O
these	O
DMA	B-General_Concept
queues	O
can	O
be	O
managed	O
locally	O
or	O
remotely	O
as	O
well	O
,	O
providing	O
additional	O
flexibility	O
in	O
the	O
control	O
model	O
.	O
</s>
<s>
However	O
,	O
longer	O
communication	O
distances	O
are	O
detrimental	O
to	O
the	O
overall	O
performance	O
of	O
the	O
EIB	O
as	O
they	O
reduce	O
available	O
concurrency	B-Operating_System
.	O
</s>
<s>
In	O
the	O
worst	O
case	O
,	O
the	O
programmer	O
must	O
take	O
extra	O
care	O
to	O
schedule	O
communication	O
patterns	O
where	O
the	O
EIB	O
is	O
able	O
to	O
function	O
at	O
high	O
concurrency	B-Operating_System
levels	O
.	O
</s>
<s>
However	O
,	O
other	O
technical	O
restrictions	O
are	O
involved	O
in	O
the	O
arbitration	O
mechanism	O
for	O
packets	O
accepted	O
onto	O
the	O
bus	B-General_Concept
.	O
</s>
<s>
While	O
each	O
of	O
the	O
nine	O
processing	O
cores	B-Architecture
can	O
sustain	O
25.6GB/s	O
read	O
and	O
write	O
concurrently	O
,	O
the	O
memory	O
interface	O
controller	O
(	O
MIC	O
)	O
is	O
tied	O
to	O
a	O
pair	O
of	O
XDR	O
memory	O
channels	O
permitting	O
a	O
maximum	O
flow	O
of	O
25.6GB/s	O
for	O
reads	O
and	O
writes	O
combined	O
and	O
the	O
two	O
IO	O
controllers	O
are	O
documented	O
as	O
supporting	O
a	O
peak	O
combined	O
input	O
speed	O
of	O
25.6GB/s	O
and	O
a	O
peak	O
combined	O
output	O
speed	O
of	O
35GB/s	O
.	O
</s>
<s>
4	O
inbound	O
+	O
4	O
outbound	O
lanes	O
are	O
supporting	O
memory	B-Operating_System
coherency	I-Operating_System
.	O
</s>
<s>
Some	O
companies	O
,	O
such	O
as	O
Leadtek	O
,	O
have	O
released	O
PCI-E	O
cards	O
based	O
upon	O
the	O
Cell	O
to	O
allow	O
for	O
"	O
faster	O
than	O
real	O
time	O
"	O
transcoding	O
of	O
H.264	B-Application
,	O
MPEG-2	B-Algorithm
and	O
MPEG-4	B-Algorithm
video	O
.	O
</s>
<s>
On	O
August	O
29	O
,	O
2007	O
,	O
IBM	O
announced	O
the	O
BladeCenter	B-General_Concept
QS21	O
.	O
</s>
<s>
A	O
single	O
BladeCenter	B-General_Concept
chassis	O
can	O
achieve	O
6.4	O
tera	O
–	O
floating	O
point	O
operations	O
per	O
second	O
(	O
teraFLOPS	O
)	O
and	O
over	O
25.8	O
teraFLOPS	O
in	O
a	O
standard	O
42U	O
rack	O
.	O
</s>
<s>
On	O
May	O
13	O
,	O
2008	O
,	O
IBM	O
announced	O
the	O
BladeCenter	B-General_Concept
QS22	B-General_Concept
.	O
</s>
<s>
The	O
QS22	B-General_Concept
introduces	O
the	O
PowerXCell	O
8i	O
processor	O
with	O
five	O
times	O
the	O
double-precision	O
floating	O
point	O
performance	O
of	O
the	O
QS21	O
,	O
and	O
the	O
capacity	O
for	O
up	O
to	O
32GB	O
of	O
DDR2	O
memory	O
on-blade	O
.	O
</s>
<s>
IBM	O
has	O
discontinued	O
the	O
Blade	B-Architecture
server	I-Architecture
line	O
based	O
on	O
Cell	O
processors	O
as	O
of	O
January	O
12	O
,	O
2012	O
.	O
</s>
<s>
Sony	O
's	O
PlayStation	B-Operating_System
3	I-Operating_System
video	B-Device
game	I-Device
console	I-Device
was	O
the	O
first	O
production	O
application	O
of	O
the	O
Cell	O
processor	O
,	O
clocked	O
at	O
3.2GHz	O
and	O
containing	O
seven	O
out	O
of	O
eight	O
operational	O
SPEs	O
,	O
to	O
allow	O
Sony	O
to	O
increase	O
the	O
yield	O
on	O
the	O
processor	O
manufacture	O
.	O
</s>
<s>
Toshiba	O
has	O
produced	O
HDTVs	B-Device
using	O
Cell	O
.	O
</s>
<s>
They	O
presented	O
a	O
system	O
to	O
decode	O
48	O
standard	B-Device
definition	I-Device
MPEG-2	B-Algorithm
streams	O
simultaneously	O
on	O
a	O
1920×1080	O
screen	O
.	O
</s>
<s>
IBM	O
's	O
supercomputer	B-Architecture
,	O
IBM	B-General_Concept
Roadrunner	I-General_Concept
,	O
was	O
a	O
hybrid	O
of	O
General	O
Purpose	O
x86-64	O
Opteron	B-General_Concept
as	O
well	O
as	O
Cell	O
processors	O
.	O
</s>
<s>
This	O
system	O
assumed	O
the	O
#1	O
spot	O
on	O
the	O
June	O
2008	O
Top	B-Operating_System
500	I-Operating_System
list	O
as	O
the	O
first	O
supercomputer	B-Architecture
to	O
run	O
at	O
petaFLOPS	O
speeds	O
,	O
having	O
gained	O
a	O
sustained	O
1.026	O
petaFLOPS	O
speed	O
using	O
the	O
standard	O
LINPACK	B-Device
benchmark	I-Device
.	O
</s>
<s>
IBM	B-General_Concept
Roadrunner	I-General_Concept
used	O
the	O
PowerXCell	O
8i	O
version	O
of	O
the	O
Cell	O
processor	O
,	O
manufactured	O
using	O
65nm	B-Algorithm
technology	O
and	O
enhanced	O
SPUs	O
that	O
can	O
handle	O
double	O
precision	O
calculations	O
in	O
the	O
128-bit	O
registers	O
,	O
reaching	O
double	O
precision	O
102GFLOPs	O
per	O
chip	O
.	O
</s>
<s>
Clusters	O
of	O
PlayStation	B-Operating_System
3	I-Operating_System
consoles	O
are	O
an	O
attractive	O
alternative	O
to	O
high-end	O
systems	O
based	O
on	O
Cell	O
blades	B-Architecture
.	O
</s>
<s>
Terrasoft	O
Solutions	O
is	O
selling	O
8-node	O
and	O
32-node	O
PS3	B-Operating_System
clusters	O
with	O
Yellow	B-General_Concept
Dog	I-General_Concept
Linux	I-General_Concept
pre-installed	O
,	O
an	O
implementation	O
of	O
Dongarra	O
's	O
research	O
.	O
</s>
<s>
As	O
first	O
reported	O
by	O
Wired	O
on	O
October	O
17	O
,	O
2007	O
,	O
an	O
interesting	O
application	O
of	O
using	O
PlayStation	B-Operating_System
3	I-Operating_System
in	O
a	O
cluster	O
configuration	O
was	O
implemented	O
by	O
Astrophysicist	O
Gaurav	O
Khanna	O
,	O
from	O
the	O
Physics	O
department	O
of	O
University	O
of	O
Massachusetts	O
Dartmouth	O
,	O
who	O
replaced	O
time	O
used	O
on	O
supercomputers	B-Architecture
with	O
a	O
cluster	O
of	O
eight	O
PlayStation	B-Operating_System
3s	I-Operating_System
.	O
</s>
<s>
Subsequently	O
,	O
the	O
next	O
generation	O
of	O
this	O
machine	O
,	O
now	O
called	O
the	O
PlayStation	B-Operating_System
3	I-Operating_System
Gravity	O
Grid	O
,	O
uses	O
a	O
network	O
of	O
16	O
machines	O
,	O
and	O
exploits	O
the	O
Cell	O
processor	O
for	O
the	O
intended	O
application	O
which	O
is	O
binary	O
black	B-Application
hole	I-Application
coalescence	O
using	O
perturbation	O
theory	O
.	O
</s>
<s>
In	O
particular	O
,	O
the	O
cluster	O
performs	O
astrophysical	O
simulations	O
of	O
large	O
supermassive	O
black	B-Application
holes	I-Application
capturing	O
smaller	O
compact	O
objects	O
and	O
has	O
generated	O
numerical	O
data	O
that	O
has	O
been	O
published	O
multiple	O
times	O
in	O
the	O
relevant	O
scientific	O
research	O
literature	O
.	O
</s>
<s>
The	O
Cell	O
processor	O
version	O
used	O
by	O
the	O
PlayStation	B-Operating_System
3	I-Operating_System
has	O
a	O
main	O
CPU	B-Device
and	O
6	O
SPEs	O
available	O
to	O
the	O
user	O
,	O
giving	O
the	O
Gravity	O
Grid	O
machine	O
a	O
net	O
of	O
16	O
general-purpose	O
processors	O
and	O
96	O
vector	B-Operating_System
processors	I-Operating_System
.	O
</s>
<s>
The	O
machine	O
has	O
a	O
one-time	O
cost	O
of	O
$	O
9,000	O
to	O
build	O
and	O
is	O
adequate	O
for	O
black-hole	O
simulations	O
which	O
would	O
otherwise	O
cost	O
$	O
6,000	O
per	O
run	O
on	O
a	O
conventional	O
supercomputer	B-Architecture
.	O
</s>
<s>
The	O
black	B-Application
hole	I-Application
calculations	O
are	O
not	O
memory-intensive	O
and	O
are	O
highly	O
localizable	O
,	O
and	O
so	O
are	O
well-suited	O
to	O
this	O
architecture	O
.	O
</s>
<s>
Khanna	O
claims	O
that	O
the	O
cluster	O
's	O
performance	O
exceeds	O
that	O
of	O
a	O
100+	O
Intel	O
Xeon	O
core	B-General_Concept
based	O
traditional	O
Linux	B-Application
cluster	O
on	O
his	O
simulations	O
.	O
</s>
<s>
The	B-Operating_System
PS3	I-Operating_System
Gravity	O
Grid	O
gathered	O
significant	O
media	O
attention	O
through	O
2007	O
,	O
2008	O
,	O
2009	O
,	O
and	O
2010	O
.	O
</s>
<s>
The	O
computational	O
Biochemistry	O
and	O
Biophysics	O
lab	O
at	O
the	O
Universitat	O
Pompeu	O
Fabra	O
,	O
in	O
Barcelona	O
,	O
deployed	O
in	O
2007	O
a	O
BOINC	B-Operating_System
system	O
called	O
PS3GRID	B-Operating_System
for	O
collaborative	O
computing	O
based	O
on	O
the	O
CellMD	O
software	O
,	O
the	O
first	O
one	O
designed	O
specifically	O
for	O
the	O
Cell	O
processor	O
.	O
</s>
<s>
The	O
United	O
States	O
Air	O
Force	O
Research	O
Laboratory	O
has	O
deployed	O
a	O
PlayStation	B-Operating_System
3	I-Operating_System
cluster	O
of	O
over	O
1700	O
units	O
,	O
nicknamed	O
the	O
"	O
Condor	O
Cluster	O
"	O
,	O
for	O
analyzing	O
high-resolution	B-Algorithm
satellite	O
imagery	O
.	O
</s>
<s>
The	O
Air	O
Force	O
claims	O
the	O
Condor	O
Cluster	O
would	O
be	O
the	O
33rd	O
largest	O
supercomputer	B-Architecture
in	O
the	O
world	O
in	O
terms	O
of	O
capacity	O
.	O
</s>
<s>
The	O
lab	O
has	O
opened	O
up	O
the	O
supercomputer	B-Architecture
for	O
use	O
by	O
universities	O
for	O
research	O
.	O
</s>
<s>
With	O
the	O
help	O
of	O
the	O
computing	O
power	O
of	O
over	O
half	O
a	O
million	O
PlayStation	B-Operating_System
3	I-Operating_System
consoles	O
,	O
the	O
distributed	O
computing	O
project	O
Folding	B-Application
@home	I-Application
has	O
been	O
recognized	O
by	O
Guinness	O
World	O
Records	O
as	O
the	O
most	O
powerful	O
distributed	O
network	O
in	O
the	O
world	O
.	O
</s>
<s>
Additionally	O
,	O
the	O
collective	O
efforts	O
enabled	O
PS3	B-Operating_System
alone	O
to	O
reach	O
the	O
petaFLOPS	O
mark	O
on	O
September	O
23	O
,	O
2007	O
.	O
</s>
<s>
In	O
comparison	O
,	O
the	O
world	O
's	O
second-most	O
powerful	O
supercomputer	B-Architecture
at	O
the	O
time	O
,	O
IBM	O
's	O
Blue	B-Operating_System
Gene/L	I-Operating_System
,	O
performed	O
at	O
around	O
478.2teraFLOPS	O
,	O
which	O
means	O
home	O
's	O
computing	O
power	O
is	O
approximately	O
twice	O
Blue	B-Operating_System
Gene/L	I-Operating_System
'	O
s	O
(	O
although	O
the	O
CPU	B-Device
interconnect	B-General_Concept
in	O
Blue	B-Operating_System
Gene/L	I-Operating_System
is	O
more	O
than	O
one	O
million	O
times	O
faster	O
than	O
the	O
mean	O
network	O
speed	O
in	O
Folding	B-Application
@home	I-Application
)	O
.	O
</s>
<s>
As	O
of	O
May	O
7	O
,	O
2011	O
,	O
Folding	B-Application
@home	I-Application
runs	O
at	O
about	O
9.3	O
x86	O
petaFLOPS	O
,	O
with	O
1.6petaFLOPS	O
generated	O
by	O
26,000	O
active	O
PS3s	B-Operating_System
alone	O
.	O
</s>
<s>
IBM	O
announced	O
on	O
April	O
25	O
,	O
2007	O
,	O
that	O
it	O
would	O
begin	O
integrating	O
its	O
Cell	O
Broadband	O
Engine	O
Architecture	O
microprocessors	B-Architecture
into	O
the	O
company	O
's	O
System	B-Device
z	I-Device
line	O
of	O
mainframes	O
.	O
</s>
<s>
This	O
has	O
led	O
to	O
a	O
gameframe	B-Protocol
.	O
</s>
<s>
Each	O
SPE	O
runs	O
a	O
"	O
mini	O
kernel	B-Operating_System
"	O
whose	O
role	O
is	O
to	O
fetch	O
a	O
job	O
,	O
execute	O
it	O
,	O
and	O
synchronize	O
with	O
the	O
PPE	O
.	O
</s>
<s>
The	O
mini	O
kernel	B-Operating_System
and	O
scheduling	O
is	O
distributed	O
across	O
the	O
SPEs	O
.	O
</s>
<s>
Tasks	O
are	O
synchronized	O
using	O
mutexes	B-Operating_System
or	O
semaphores	B-Operating_System
as	O
in	O
a	O
conventional	O
operating	B-General_Concept
system	I-General_Concept
.	O
</s>
<s>
This	O
provides	O
a	O
flexible	O
and	O
powerful	O
architecture	O
for	O
stream	B-Application
processing	I-Application
,	O
and	O
allows	O
explicit	O
scheduling	O
for	O
each	O
SPE	O
separately	O
.	O
</s>
<s>
Other	O
processors	O
are	O
also	O
able	O
to	O
perform	O
streaming	O
tasks	O
but	O
are	O
limited	O
by	O
the	O
kernel	B-Operating_System
loaded	O
.	O
</s>
<s>
In	O
2005	O
,	O
patches	O
enabling	O
Cell	O
support	O
in	O
the	O
Linux	B-Application
kernel	B-Operating_System
were	O
submitted	O
for	O
inclusion	O
by	O
IBM	O
developers	O
.	O
</s>
<s>
Arnd	O
Bergmann	O
(	O
one	O
of	O
the	O
developers	O
of	O
the	O
aforementioned	O
patches	O
)	O
also	O
described	O
the	O
Linux-based	O
Cell	O
architecture	O
at	O
LinuxTag	O
2005	O
.	O
</s>
<s>
As	O
of	O
release	O
2.6.16	O
(	O
March	O
20	O
,	O
2006	O
)	O
,	O
the	O
Linux	B-Application
kernel	B-Operating_System
officially	O
supports	O
the	O
Cell	O
processor	O
.	O
</s>
<s>
Fixstars	O
Solutions	O
provides	O
Yellow	B-General_Concept
Dog	I-General_Concept
Linux	I-General_Concept
for	O
IBM	O
and	O
Mercury	O
Cell-based	O
systems	O
,	O
as	O
well	O
as	O
for	O
the	O
PlayStation	B-Operating_System
3	I-Operating_System
.	O
</s>
<s>
Terra	O
Soft	O
strategically	O
partnered	O
with	O
Mercury	O
to	O
provide	O
a	O
Linux	B-Application
Board	O
Support	O
Package	O
for	O
Cell	O
,	O
and	O
support	O
and	O
development	O
of	O
software	O
applications	O
on	O
various	O
other	O
Cell	O
platforms	O
,	O
including	O
the	O
IBM	B-General_Concept
BladeCenter	I-General_Concept
JS21	B-General_Concept
and	O
Cell	O
QS20	O
,	O
and	O
Mercury	O
Cell-based	O
solutions	O
.	O
</s>
<s>
Terra	O
Soft	O
also	O
maintains	O
the	O
Y-HPC	O
(	O
High	B-Architecture
Performance	I-Architecture
Computing	I-Architecture
)	O
Cluster	O
Construction	O
and	O
Management	O
Suite	O
and	O
Y-Bio	O
gene	O
sequencing	O
tools	O
.	O
</s>
<s>
Y-Bio	O
is	O
built	O
upon	O
the	O
RPM	O
Linux	B-Application
standard	O
for	O
package	O
management	O
,	O
and	O
offers	O
tools	O
which	O
help	O
bioinformatics	O
researchers	O
conduct	O
their	O
work	O
with	O
greater	O
efficiency	O
.	O
</s>
<s>
IBM	O
has	O
developed	O
a	O
pseudo-filesystem	O
for	O
Linux	B-Application
coined	O
"	O
Spufs	O
"	O
that	O
simplifies	O
access	O
to	O
and	O
use	O
of	O
the	O
SPE	O
resources	O
.	O
</s>
<s>
IBM	O
is	O
currently	O
maintaining	O
a	O
Linux	B-Application
kernel	B-Operating_System
and	O
GDB	B-Language
ports	O
,	O
while	O
Sony	O
maintains	O
the	O
GNU	B-Application
toolchain	I-Application
(	O
GCC	B-Application
,	O
binutils	B-Application
)	O
.	O
</s>
<s>
In	O
November	O
2005	O
,	O
IBM	O
released	O
a	O
"	O
Cell	O
Broadband	O
Engine	O
(	O
CBE	O
)	O
Software	B-General_Concept
Development	I-General_Concept
Kit	O
Version	O
1.0	O
"	O
,	O
consisting	O
of	O
a	O
simulator	O
and	O
assorted	O
tools	O
,	O
to	O
its	O
web	O
site	O
.	O
</s>
<s>
Development	O
versions	O
of	O
the	O
latest	O
kernel	B-Operating_System
and	O
tools	O
for	O
Fedora	O
Core	B-General_Concept
4	O
are	O
maintained	O
at	O
the	O
Barcelona	O
Supercomputing	B-Architecture
Center	O
website	O
.	O
</s>
<s>
In	O
August	O
2007	O
,	O
Mercury	B-Application
Computer	I-Application
Systems	I-Application
released	O
a	O
Software	B-General_Concept
Development	I-General_Concept
Kit	O
for	O
PlayStation	B-Operating_System
3	I-Operating_System
for	O
High-Performance	B-Architecture
Computing	I-Architecture
.	O
</s>
<s>
In	O
November	O
2007	O
,	O
Fixstars	O
Corporation	O
released	O
the	O
new	O
"	O
CVCell	O
"	O
module	O
aiming	O
to	O
accelerate	O
several	O
important	O
OpenCV	B-Language
APIs	O
for	O
Cell	O
.	O
</s>
<s>
In	O
a	O
series	O
of	O
software	O
calculation	O
tests	O
,	O
they	O
recorded	O
execution	O
times	O
on	O
a	O
3.2GHz	O
Cell	O
processor	O
that	O
were	O
between	O
6x	O
and	O
27x	O
faster	O
compared	O
with	O
the	O
same	O
software	O
on	O
a	O
2.4GHz	O
Intel	B-Device
Core	I-Device
2	I-Device
Duo	O
.	O
</s>
