<s>
Celeron	B-Device
is	O
a	O
series	O
of	O
low-end	O
IA-32	B-Device
and	O
x86-64	B-Device
computer	O
microprocessor	B-Architecture
models	O
targeted	O
at	O
low-cost	O
personal	O
computers	O
,	O
manufactured	O
by	O
Intel	O
.	O
</s>
<s>
The	O
first	O
Celeron-branded	O
CPU	O
was	O
introduced	O
in	O
April	O
15	O
,	O
1998	O
,	O
and	O
was	O
based	O
on	O
the	O
Pentium	B-General_Concept
II	I-General_Concept
.	O
</s>
<s>
Celeron-branded	O
processors	O
released	O
from	O
2009	O
to	O
2022	O
are	O
compatible	O
with	O
IA-32	B-Device
software	O
.	O
</s>
<s>
They	O
typically	O
offer	O
less	O
performance	O
per	O
clock	O
speed	O
compared	O
to	O
flagship	O
Intel	O
CPU	O
lines	O
,	O
such	O
as	O
the	O
Pentium	B-General_Concept
or	O
Core	B-Device
brands	O
.	O
</s>
<s>
They	O
often	O
have	O
less	O
cache	B-General_Concept
or	O
intentionally	O
disabled	O
advanced	O
features	O
,	O
with	O
variable	O
impact	O
on	O
performance	O
.	O
</s>
<s>
While	O
some	O
Celeron	B-Device
designs	O
have	O
achieved	O
strong	O
performance	O
for	O
their	O
segment	O
,	O
the	O
majority	O
of	O
the	O
Celeron	B-Device
line	O
has	O
exhibited	O
noticeably	O
degraded	O
performance	O
.	O
</s>
<s>
This	O
has	O
been	O
the	O
primary	O
justification	O
for	O
the	O
higher	O
cost	O
of	O
other	O
Intel	O
CPU	O
brands	O
versus	O
the	O
Celeron	B-Device
range	O
.	O
</s>
<s>
In	O
September	O
2022	O
,	O
Intel	O
announced	O
that	O
the	O
Celeron	B-Device
brand	O
,	O
along	O
with	O
Pentium	B-General_Concept
,	O
will	O
be	O
replaced	O
with	O
the	O
new	O
"	O
Intel	O
Processor	O
"	O
branding	O
for	O
low-end	O
processors	O
in	O
laptops	B-Device
,	O
beginning	O
in	O
2023	O
.	O
</s>
<s>
As	O
a	O
product	O
concept	O
,	O
the	O
Celeron	B-Device
was	O
introduced	O
in	O
response	O
to	O
Intel	O
's	O
loss	O
of	O
the	O
low-end	O
market	O
,	O
in	O
particular	O
to	O
the	O
Cyrix	B-General_Concept
6x86	I-General_Concept
,	O
the	O
AMD	B-Architecture
K6	I-Architecture
,	O
and	O
the	O
IDT	B-Device
Winchip	I-Device
.	O
</s>
<s>
Intel	O
's	O
existing	O
low-end	O
product	O
,	O
the	O
Pentium	B-General_Concept
MMX	O
,	O
was	O
no	O
longer	O
performance-competitive	O
at	O
233MHz	O
.	O
</s>
<s>
Although	O
a	O
faster	O
Pentium	B-General_Concept
MMX	O
would	O
have	O
been	O
a	O
lower-risk	O
strategy	O
,	O
the	O
industry-standard	O
Socket	B-General_Concept
7	I-General_Concept
platform	O
hosted	O
a	O
market	O
of	O
competitor	O
CPUs	O
that	O
could	O
be	O
drop-in	O
replacements	O
for	O
the	O
Pentium	B-General_Concept
MMX	O
.	O
</s>
<s>
Instead	O
,	O
Intel	O
pursued	O
a	O
budget	O
part	O
that	O
was	O
to	O
be	O
pin-compatible	O
with	O
their	O
high-end	O
Pentium	B-General_Concept
II	I-General_Concept
product	O
,	O
using	O
the	O
Pentium	B-General_Concept
II	I-General_Concept
's	O
proprietary	O
Slot	B-Device
1	I-Device
interface	O
.	O
</s>
<s>
The	O
Celeron	B-Device
also	O
effectively	O
killed	O
off	O
the	O
nine-year-old	O
80486	B-General_Concept
chip	O
,	O
which	O
had	O
been	O
the	O
low-end	O
processor	O
brand	O
for	O
entry-level	O
desktops	O
and	O
laptops	B-Device
until	O
1998	O
.	O
</s>
<s>
Intel	O
hired	O
marketing	O
firm	O
Lexicon	O
Branding	O
,	O
which	O
had	O
originally	O
come	O
up	O
with	O
the	O
name	O
"	O
Pentium	B-General_Concept
"	O
,	O
to	O
devise	O
a	O
name	O
for	O
the	O
new	O
product	O
as	O
well	O
.	O
</s>
<s>
Celeron	B-Device
is	O
seven	O
letters	O
and	O
three	O
syllables	O
,	O
like	O
Pentium	B-General_Concept
.	O
</s>
<s>
The	O
'	O
Cel	O
 '	O
of	O
Celeron	B-Device
rhymes	O
with	O
'	O
tel	O
 '	O
of	O
Intel.	O
"	O
</s>
<s>
Launched	O
in	O
April	O
1998	O
,	O
the	O
first	O
Covington	O
Celeron	B-Device
was	O
essentially	O
a	O
266MHz	O
Pentium	B-General_Concept
II	I-General_Concept
manufactured	O
without	O
any	O
secondary	B-General_Concept
cache	I-General_Concept
at	O
all	O
.	O
</s>
<s>
Although	O
clocked	O
at	O
266	O
or	O
300MHz	O
(	O
frequencies	O
33	O
or	O
66MHz	O
higher	O
than	O
the	O
desktop	B-Device
version	O
of	O
the	O
Pentium	B-General_Concept
w/MMX	O
)	O
,	O
the	O
cacheless	O
Celerons	B-Device
had	O
trouble	O
outcompeting	O
the	O
parts	O
they	O
were	O
designed	O
to	O
replace	O
.	O
</s>
<s>
Substantial	O
numbers	O
were	O
sold	O
on	O
first	O
release	O
,	O
largely	O
on	O
the	O
strength	O
of	O
the	O
Intel	O
name	O
,	O
but	O
the	O
Celeron	B-Device
quickly	O
achieved	O
a	O
poor	O
reputation	O
both	O
in	O
the	O
trade	O
press	O
and	O
among	O
computer	O
professionals	O
.	O
</s>
<s>
Nevertheless	O
,	O
the	O
first	O
Celerons	B-Device
were	O
quite	O
popular	O
among	O
some	O
overclockers	B-Application
,	O
for	O
their	O
flexible	O
overclockability	B-Application
and	O
reasonable	O
price	O
.	O
</s>
<s>
Covington	O
was	O
only	O
manufactured	O
in	O
Slot	B-Device
1	I-Device
SEPP	O
format	O
.	O
</s>
<s>
The	O
Mendocino	O
Celeron	B-Device
,	O
launched	O
August	O
24	O
,	O
1998	O
,	O
was	O
the	O
first	O
retail	O
CPU	O
to	O
use	O
on-die	O
L2	O
cache	B-General_Concept
.	O
</s>
<s>
Whereas	O
Covington	O
had	O
no	O
secondary	B-General_Concept
cache	I-General_Concept
at	O
all	O
,	O
Mendocino	O
included	O
128KB	O
of	O
L2	O
cache	B-General_Concept
running	O
at	O
full	O
clock	O
rate	O
.	O
</s>
<s>
The	O
first	O
Mendocino-core	O
Celeron	B-Device
was	O
clocked	O
at	O
a	O
then-modest	O
300MHz	O
but	O
offered	O
almost	O
twice	O
the	O
performance	O
of	O
the	O
old	O
cacheless	O
Covington	O
Celeron	B-Device
at	O
the	O
same	O
clock	O
rate	O
.	O
</s>
<s>
To	O
distinguish	O
it	O
from	O
the	O
older	O
Covington	O
300MHz	O
,	O
Intel	O
called	O
the	O
Mendocino	O
core	B-Device
Celeron	B-Device
300A	O
.	O
</s>
<s>
Although	O
the	O
other	O
Mendocino	O
Celerons	B-Device
(	O
the	O
333MHz	O
part	O
,	O
for	O
example	O
)	O
did	O
not	O
have	O
an	O
A	O
appended	O
,	O
some	O
people	O
call	O
all	O
Mendocino	O
processors	O
Celeron-A	O
regardless	O
of	O
clock	O
rate	O
.	O
</s>
<s>
The	O
new	O
Mendocino-core	O
Celeron	B-Device
was	O
a	O
good	O
performer	O
from	O
the	O
outset	O
.	O
</s>
<s>
Indeed	O
,	O
most	O
industry	O
analysts	O
regarded	O
the	O
first	O
Mendocino-based	O
Celerons	B-Device
as	O
too	O
successful	O
—	O
performance	O
was	O
sufficiently	O
high	O
to	O
not	O
only	O
compete	O
strongly	O
with	O
rival	O
parts	O
,	O
but	O
also	O
to	O
attract	O
buyers	O
away	O
from	O
Intel	O
's	O
high-profit	O
flagship	O
,	O
the	O
Pentium	B-General_Concept
II	I-General_Concept
.	O
</s>
<s>
Overclockers	B-Application
soon	O
discovered	O
that	O
,	O
given	O
a	O
high-end	O
motherboard	B-Device
,	O
many	O
Celeron	B-Device
300A	O
CPUs	O
could	O
run	O
reliably	O
at	O
450MHz	O
.	O
</s>
<s>
This	O
was	O
achieved	O
by	O
simply	O
increasing	O
the	O
front-side	B-Architecture
bus	I-Architecture
(	O
FSB	B-Architecture
)	O
clock	O
rate	O
from	O
the	O
stock	O
66MHz	O
to	O
the	O
100MHz	O
clock	O
of	O
the	O
Pentium	B-General_Concept
II	I-General_Concept
,	O
helped	O
by	O
several	O
facts	O
:	O
the	O
440BX	O
chipset	O
with	O
nominal	O
support	O
for	O
100MHz	O
and	O
correspondent	O
memory	O
had	O
already	O
been	O
on	O
the	O
market	O
,	O
and	O
the	O
internal	O
L2	O
cache	B-General_Concept
was	O
more	O
tolerant	O
to	O
overclocking	B-Application
than	O
external	O
cache	B-General_Concept
chips	O
,	O
which	O
already	O
had	O
to	O
run	O
at	O
half-CPU	O
speed	O
by	O
design	O
.	O
</s>
<s>
At	O
this	O
frequency	O
,	O
the	O
budget	O
Mendocino	O
Celeron	B-Device
rivaled	O
the	O
fastest	O
x86	B-Operating_System
processors	O
available	O
.	O
</s>
<s>
Some	O
motherboards	B-Device
were	O
designed	O
to	O
prevent	O
this	O
modification	O
,	O
by	O
restricting	O
the	O
Celeron	B-Device
's	O
front	B-Architecture
side	I-Architecture
bus	I-Architecture
to	O
66MHz	O
.	O
</s>
<s>
However	O
,	O
overclockers	B-Application
soon	O
found	O
that	O
putting	O
tape	O
over	O
pin	O
B21	O
of	O
the	O
Celeron	B-Device
's	O
interface	O
slot	O
circumvented	O
this	O
,	O
allowing	O
a	O
100MHz	O
bus	O
.	O
</s>
<s>
At	O
the	O
time	O
on-die	O
cache	B-General_Concept
was	O
difficult	O
to	O
manufacture	O
;	O
especially	O
L2	O
as	O
more	O
of	O
it	O
is	O
needed	O
to	O
attain	O
an	O
adequate	O
level	O
of	O
performance	O
.	O
</s>
<s>
A	O
benefit	O
of	O
on-die	O
cache	B-General_Concept
is	O
that	O
it	O
operates	O
at	O
the	O
same	O
clock	O
rate	O
as	O
the	O
CPU	O
.	O
</s>
<s>
All	O
other	O
Intel	O
CPUs	O
at	O
that	O
time	O
used	O
motherboard	B-Device
mounted	O
or	O
slot	O
mounted	O
secondary	O
L2	O
cache	B-General_Concept
,	O
which	O
was	O
very	O
easy	O
to	O
manufacture	O
,	O
cheap	O
,	O
and	O
simple	O
to	O
enlarge	O
to	O
any	O
desired	O
size	O
(	O
typical	O
cache	B-General_Concept
sizes	O
were	O
512KB	O
or	O
1MB	O
)	O
,	O
but	O
they	O
carried	O
the	O
performance	O
penalty	O
of	O
slower	O
cache	B-General_Concept
performance	O
,	O
typically	O
running	O
at	O
FSB	B-Architecture
frequency	O
of	O
60	O
to	O
100MHz	O
.	O
</s>
<s>
The	O
Pentium	B-General_Concept
II	I-General_Concept
's	O
512KB	O
of	O
L2	O
cache	B-General_Concept
was	O
implemented	O
with	O
a	O
pair	O
of	O
relatively	O
high-performance	O
L2	O
cache	B-General_Concept
chips	O
mounted	O
on	O
a	O
special-purpose	O
board	O
alongside	O
the	O
processor	O
itself	O
,	O
running	O
at	O
half	O
the	O
processor	O
's	O
clock	O
rate	O
and	O
communicating	O
with	O
the	O
CPU	O
through	O
a	O
special	O
back-side	B-Architecture
bus	I-Architecture
.	O
</s>
<s>
This	O
method	O
of	O
cache	B-General_Concept
placement	O
was	O
expensive	O
and	O
imposed	O
practical	O
cache-size	O
limits	O
,	O
but	O
allowed	O
the	O
Pentium	B-General_Concept
II	I-General_Concept
to	O
be	O
clocked	O
higher	O
and	O
avoided	O
front	B-Architecture
side	I-Architecture
bus	I-Architecture
RAM/L2	O
cache	B-General_Concept
contention	O
typical	O
with	O
motherboard-placed	O
L2	O
cache	B-General_Concept
configurations	O
.	O
</s>
<s>
The	O
Mendocino	O
Celeron	B-Device
CPU	O
came	O
only	O
designed	O
for	O
a	O
66MHz	O
front-side	B-Architecture
bus	I-Architecture
,	O
but	O
this	O
would	O
not	O
be	O
a	O
serious	O
performance	O
bottleneck	O
until	O
clock	O
rates	O
reached	O
higher	O
levels	O
.	O
</s>
<s>
The	O
Mendocino	O
Celerons	B-Device
also	O
introduced	O
new	O
packaging	O
.	O
</s>
<s>
When	O
the	O
Mendocinos	O
debuted	O
they	O
came	O
in	O
both	O
a	O
Slot	B-Device
1	I-Device
SEPP	O
and	O
Socket	B-Device
370	I-Device
PPGA	B-Algorithm
package	O
.	O
</s>
<s>
The	O
Slot	B-Device
1	I-Device
form	O
had	O
been	O
designed	O
to	O
accommodate	O
the	O
off-chip	O
cache	B-General_Concept
of	O
the	O
Pentium	B-General_Concept
II	I-General_Concept
and	O
had	O
mounting	O
problems	O
with	O
motherboards	B-Device
.	O
</s>
<s>
Because	O
all	O
Celerons	B-Device
are	O
a	O
single-chip	O
design	O
,	O
however	O
,	O
there	O
was	O
no	O
reason	O
to	O
retain	O
the	O
slot	O
packaging	O
for	O
L2	O
cache	B-General_Concept
storage	O
,	O
and	O
Intel	O
discontinued	O
the	O
Slot	B-Device
1	I-Device
variant	O
;	O
beginning	O
with	O
the	O
466MHz	O
part	O
,	O
only	O
the	O
PPGA	B-Algorithm
Socket	B-Device
370	I-Device
form	O
was	O
offered	O
.	O
</s>
<s>
(	O
Third-party	O
manufacturers	O
made	O
motherboard	B-Device
slot-to-socket	O
adapters	O
(	O
nicknamed	O
Slotkets	B-General_Concept
)	O
available	O
for	O
a	O
few	O
dollars	O
,	O
which	O
allowed	O
,	O
for	O
example	O
,	O
a	O
Celeron	B-Device
500	O
to	O
be	O
fitted	O
to	O
a	O
Slot	B-Device
1	I-Device
motherboard	B-Device
.	O
)	O
</s>
<s>
One	O
interesting	O
note	O
about	O
the	O
PPGA	B-Algorithm
Socket	B-Device
370	I-Device
Mendocinos	O
is	O
they	O
supported	O
symmetric	B-Operating_System
multiprocessing	I-Operating_System
(	O
SMP	O
)	O
,	O
and	O
there	O
was	O
at	O
least	O
one	O
motherboard	B-Device
released	O
(	O
the	O
ABIT	B-Operating_System
BP6	I-Operating_System
)	O
which	O
took	O
advantage	O
of	O
this	O
fact	O
.	O
</s>
<s>
These	O
identifiers	O
are	O
shared	O
with	O
the	O
related	O
Dixon	O
Mobile	B-General_Concept
Pentium	I-General_Concept
II	I-General_Concept
variant	O
.	O
</s>
<s>
The	O
next	O
generation	O
Celeron	B-Device
was	O
the	O
'	O
Coppermine-128	O
'	O
(	O
sometimes	O
known	O
as	O
the	O
Celeron	B-Device
II	O
)	O
.	O
</s>
<s>
These	O
were	O
a	O
derivative	O
of	O
Intel	O
's	O
Coppermine	O
Pentium	B-General_Concept
III	I-General_Concept
and	O
were	O
released	O
on	O
March	O
29	O
,	O
2000	O
.	O
</s>
<s>
This	O
Celeron	B-Device
used	O
a	O
Coppermine	O
core	B-Device
with	O
half	O
of	O
its	O
L2	O
cache	B-General_Concept
switched	O
off	O
,	O
resulting	O
in	O
128KB	O
of	O
4-way	O
associative	O
on-chip	O
L2	O
cache	B-General_Concept
as	O
on	O
the	O
Mendocino	O
,	O
and	O
was	O
initially	O
likewise	O
restricted	O
to	O
a	O
66MHz	O
Front	B-Architecture
Side	I-Architecture
Bus	I-Architecture
speed	O
.	O
</s>
<s>
Despite	O
the	O
halved	O
associativity	O
on	O
the	O
L2	O
cache	B-General_Concept
,	O
which	O
reduced	O
hit	O
rates	O
compared	O
to	O
the	O
full	O
Coppermine	O
design	O
,	O
it	O
kept	O
the	O
256-bit	O
wide	O
L2	O
cache	B-General_Concept
bus	O
,	O
which	O
meant	O
an	O
advantage	O
compared	O
to	O
Mendocino	O
and	O
older	O
Katmai/Pentium	O
II	O
designs	O
,	O
which	O
all	O
had	O
a	O
64-bit	O
datapath	O
to	O
their	O
L2	O
caches	O
.	O
</s>
<s>
SSE	B-General_Concept
instructions	I-General_Concept
were	O
also	O
enabled	O
.	O
</s>
<s>
All	O
Coppermine-128s	O
were	O
produced	O
in	O
the	O
same	O
FCPGA	B-Algorithm
Socket	B-Device
370	I-Device
format	O
that	O
most	O
Coppermine	O
Pentium	B-General_Concept
III	I-General_Concept
CPUs	O
used	O
.	O
</s>
<s>
These	O
Celeron	B-Device
processors	O
began	O
at	O
533MHz	O
and	O
continued	O
through	O
566	O
,	O
600	O
,	O
633	O
,	O
667	O
,	O
700	O
,	O
733	O
,	O
and	O
766MHz	O
.	O
</s>
<s>
On	O
January	O
3	O
,	O
2001	O
,	O
Intel	O
switched	O
to	O
a	O
100MHz	O
bus	O
with	O
the	O
launch	O
of	O
the	O
800MHz	O
Celeron	B-Device
,	O
resulting	O
in	O
a	O
significant	O
performance-per-clock	O
improvement	O
.	O
</s>
<s>
All	O
Coppermine-128	O
CPUs	O
from	O
800MHz	O
and	O
higher	O
use	O
the	O
100MHz	O
front	B-Architecture
side	I-Architecture
bus	I-Architecture
.	O
</s>
<s>
In	O
Intel	O
's	O
"	O
Family/Model/Stepping	O
"	O
scheme	O
,	O
Coppermine	O
Celerons	B-Device
and	O
Pentium	B-General_Concept
IIIs	I-General_Concept
are	O
family	O
6	O
,	O
model	O
8	O
and	O
their	O
Intel	O
product	O
code	O
is	O
80526	O
.	O
</s>
<s>
These	O
Celeron	B-Device
processors	O
,	O
released	O
initially	O
at	O
1.2GHz	O
on	O
October	O
2	O
,	O
2001	O
,	O
were	O
based	O
on	O
the	O
Pentium	B-General_Concept
III	I-General_Concept
'	O
Tualatin	O
 '	O
core	B-Device
and	O
made	O
with	O
a	O
0.13	O
micrometer	O
process	O
for	O
the	O
FCPGA	B-Algorithm
2	I-Algorithm
Socket	B-Device
370	I-Device
.	O
</s>
<s>
They	O
were	O
nicknamed	O
"	O
Tualeron	O
"	O
by	O
some	O
enthusiasts	O
—	O
a	O
portmanteau	O
of	O
the	O
words	O
Tualatin	O
and	O
Celeron	B-Device
.	O
</s>
<s>
Some	O
software	O
and	O
users	O
refer	O
to	O
the	O
chips	O
as	O
Celeron-S	O
,	O
referring	O
to	O
the	O
chip	O
's	O
lineage	O
with	O
the	O
Pentium	O
III-S	O
,	O
but	O
this	O
is	O
not	O
an	O
official	O
designation	O
.	O
</s>
<s>
A	O
1.3GHz	O
chip	O
,	O
launched	O
January	O
4	O
,	O
2002	O
,	O
and	O
finally	O
a	O
1.4GHz	O
chip	O
,	O
launched	O
May	O
15	O
,	O
2002	O
(	O
the	O
same	O
day	O
as	O
the	O
1.7GHz	O
Willamette-based	O
Celeron	B-Device
launch	O
)	O
,	O
marked	O
the	O
end	O
of	O
the	O
Tualatin-256	O
line	O
.	O
</s>
<s>
The	O
most	O
significant	O
differences	O
compared	O
to	O
the	O
Pentium	B-General_Concept
III	I-General_Concept
Tualatin	O
are	O
a	O
lower	O
100MHz	O
bus	O
and	O
fixed	O
256KB	O
of	O
L2	O
cache	B-General_Concept
(	O
whereas	O
the	O
Pentium	B-General_Concept
III	I-General_Concept
was	O
offered	O
with	O
either	O
256KB	O
or	O
512KB	O
L2	O
cache	B-General_Concept
)	O
;	O
cache	B-General_Concept
associativity	O
stayed	O
at	O
8-way	O
,	O
although	O
the	O
newly	O
introduced	O
data	O
prefetching	O
appears	O
to	O
have	O
been	O
disabled	O
.	O
</s>
<s>
Furthermore	O
,	O
the	O
Tualatin-256	O
'	O
s	O
L2	O
cache	B-General_Concept
has	O
a	O
higher	O
latency	O
which	O
boosted	O
manufacturing	O
yields	O
for	O
this	O
budget	O
CPU	O
.	O
</s>
<s>
On	O
the	O
other	O
hand	O
,	O
this	O
improved	O
stability	O
when	O
overclocking	B-Application
and	O
most	O
of	O
them	O
had	O
no	O
problem	O
working	O
at	O
133MHz	O
FSB	B-Architecture
for	O
a	O
substantial	O
performance	O
increase	O
.	O
</s>
<s>
Despite	O
offering	O
much	O
improved	O
performance	O
over	O
the	O
Coppermine	O
Celeron	B-Device
it	O
superseded	O
,	O
the	O
Tualatin	O
Celeron	B-Device
still	O
suffered	O
stiff	O
competition	O
from	O
AMD	O
's	O
Duron	O
budget	O
processor	O
.	O
</s>
<s>
Intel	O
later	O
responded	O
by	O
releasing	O
the	O
NetBurst	B-Device
Willamette	O
Celeron	B-Device
,	O
and	O
for	O
some	O
time	O
Tualatin	O
Celerons	B-Device
were	O
manufactured	O
and	O
sold	O
in	O
parallel	O
with	O
the	O
Pentium	O
4-based	O
Celerons	B-Device
that	O
replaced	O
them	O
.	O
</s>
<s>
In	O
Intel	O
's	O
"	O
Family/Model/Stepping	O
"	O
scheme	O
,	O
Tualatin	O
Celerons	B-Device
and	O
Pentium	B-General_Concept
IIIs	I-General_Concept
are	O
family	O
6	O
,	O
model	O
11	O
and	O
their	O
Intel	O
product	O
code	O
is	O
80530	O
.	O
</s>
<s>
These	O
Celerons	B-Device
were	O
for	O
socket	B-Device
478	I-Device
and	O
were	O
based	O
on	O
the	O
Willamette	O
Pentium	B-General_Concept
4	I-General_Concept
core	B-Device
,	O
being	O
a	O
completely	O
different	O
design	O
compared	O
to	O
the	O
previous	O
Tualatin	O
Celeron	B-Device
.	O
</s>
<s>
These	O
are	O
often	O
known	O
as	O
the	O
Celeron	B-Device
4	O
.	O
</s>
<s>
Their	O
L2	O
cache	B-General_Concept
(	O
128KB	O
)	O
is	O
half	O
that	O
of	O
the	O
Willamette-based	O
Pentium	B-General_Concept
4	I-General_Concept
's	O
256KB	O
of	O
L2	O
cache	B-General_Concept
,	O
but	O
otherwise	O
the	O
two	O
are	O
very	O
similar	O
.	O
</s>
<s>
With	O
the	O
transition	O
to	O
the	O
Pentium	B-General_Concept
4	I-General_Concept
core	B-Device
the	O
Celeron	B-Device
now	O
featured	O
SSE2	O
instructions	O
.	O
</s>
<s>
The	O
ability	O
to	O
share	O
the	O
same	O
socket	O
as	O
the	O
Pentium	B-General_Concept
4	I-General_Concept
meant	O
that	O
the	O
Celeron	B-Device
now	O
had	O
the	O
option	O
to	O
use	O
RDRAM	O
,	O
DDR	O
SDRAM	O
,	O
or	O
traditional	O
SDRAM	O
.	O
</s>
<s>
Willamette	O
Celerons	B-Device
were	O
launched	O
May	O
15	O
,	O
2002	O
,	O
initially	O
at	O
1.7GHz	O
,	O
and	O
offered	O
a	O
noticeable	O
performance	O
improvement	O
over	O
the	O
older	O
1.3GHz	O
Tualatin-based	O
Celeron	B-Device
part	O
,	O
being	O
able	O
to	O
finally	O
outperform	O
a	O
1.3GHz	O
AMD	O
Duron	O
,	O
which	O
at	O
the	O
time	O
was	O
AMD	O
's	O
top	O
competing	O
budget	O
processor	O
.	O
</s>
<s>
On	O
June	O
12	O
,	O
2002	O
,	O
Intel	O
launched	O
the	O
last	O
Willamette	O
Celeron	B-Device
,	O
a	O
1.8GHz	O
model	O
.	O
</s>
<s>
In	O
Intel	O
's	O
"	O
Family/Model/Stepping	O
"	O
scheme	O
,	O
Willamette	O
Celerons	B-Device
and	O
Pentium	B-General_Concept
4s	I-General_Concept
are	O
family	O
15	O
,	O
model	O
1	O
,	O
and	O
their	O
Intel	O
product	O
code	O
is	O
80531	O
.	O
</s>
<s>
These	O
socket	B-Device
478	I-Device
Celerons	B-Device
are	O
based	O
on	O
the	O
Northwood	O
Pentium	B-General_Concept
4	I-General_Concept
core	B-Device
,	O
and	O
also	O
have	O
128KB	O
of	O
L2cache	O
.	O
</s>
<s>
The	O
only	O
difference	O
between	O
the	O
Northwood-128-based	O
and	O
the	O
Willamette-128-based	O
Celeron	B-Device
is	O
the	O
fact	O
that	O
it	O
was	O
built	O
on	O
the	O
new	O
130nm	O
process	O
which	O
shrank	O
the	O
die	O
size	O
,	O
increased	O
the	O
transistor	O
count	O
,	O
and	O
lowered	O
the	O
core	B-Device
voltage	O
from	O
1.7V	O
on	O
the	O
Willamette-128	O
to	O
1.52V	O
for	O
the	O
Northwood-128	O
.	O
</s>
<s>
Despite	O
these	O
differences	O
,	O
they	O
are	O
functionally	O
the	O
same	O
as	O
the	O
Willamette-128	O
Celeron	B-Device
,	O
and	O
perform	O
largely	O
the	O
same	O
clock-for-clock	O
.	O
</s>
<s>
The	O
Northwood-128	O
family	O
of	O
processors	O
were	O
initially	O
released	O
as	O
a	O
2GHz	O
core	B-Device
(	O
a	O
1.9GHz	O
model	O
was	O
announced	O
earlier	O
,	O
but	O
never	O
launched	O
)	O
on	O
September	O
18	O
,	O
2002	O
.	O
</s>
<s>
Since	O
that	O
time	O
Intel	O
has	O
released	O
at	O
total	O
of	O
10	O
different	O
clock	O
speeds	O
ranging	O
from	O
1.8GHz	O
to	O
2.8GHz	O
,	O
before	O
being	O
surpassed	O
by	O
the	O
Celeron	B-Device
D	O
.	O
Although	O
the	O
Northwood-based	O
Celerons	B-Device
suffer	O
considerably	O
from	O
their	O
small	O
L2cache	O
,	O
some	O
clock	O
rates	O
have	O
been	O
favored	O
in	O
the	O
enthusiast	O
market	O
because	O
,	O
like	O
the	O
old	O
300A	O
,	O
they	O
can	O
run	O
well	O
above	O
their	O
specified	O
clock	O
rate	O
.	O
</s>
<s>
In	O
Intel	O
's	O
"	O
Family/Model/Stepping	O
"	O
scheme	O
,	O
Northwood	O
Celerons	B-Device
and	O
Pentium	B-General_Concept
4s	I-General_Concept
are	O
family	O
15	O
,	O
model	O
2	O
,	O
and	O
their	O
Intel	O
product	O
code	O
is	O
80532	O
.	O
</s>
<s>
Prescott-256	O
Celeron	B-Device
D	O
processors	O
,	O
initially	O
launched	O
June	O
25	O
,	O
2004	O
,	O
featuring	O
double	O
the	O
L1	O
cache	B-General_Concept
(	O
16KB	O
)	O
and	O
L2	O
cache	B-General_Concept
(	O
256KB	O
)	O
as	O
compared	O
to	O
the	O
previous	O
Willamette	O
and	O
Northwood	O
desktop	B-Device
Celerons	B-Device
,	O
by	O
virtue	O
of	O
being	O
based	O
on	O
the	O
Prescott	O
Pentium	B-General_Concept
4	I-General_Concept
core	B-Device
.	O
</s>
<s>
It	O
also	O
features	O
a	O
533MT/s	O
bus	O
and	O
SSE3	B-General_Concept
,	O
and	O
a	O
3xx	O
model	O
number	O
(	O
compared	O
to	O
5xx	O
for	O
Pentium	B-General_Concept
4s	I-General_Concept
and	O
7xx	O
for	O
Pentium	B-Architecture
Ms	I-Architecture
)	O
.	O
</s>
<s>
The	O
Prescott-256	O
Celeron	B-Device
D	O
was	O
manufactured	O
for	O
Socket	B-Device
478	I-Device
and	O
LGA	B-Device
775	I-Device
,	O
with	O
3x0	O
and	O
3x5	O
designations	O
from	O
310	O
through	O
to	O
355	O
at	O
clock	O
speeds	O
of	O
2.13GHz	O
to	O
3.33GHz	O
.	O
</s>
<s>
The	O
Intel	B-Device
Celeron	I-Device
D	O
processor	O
works	O
with	O
the	O
Intel	O
845	O
and	O
865	O
chipset	O
families	O
.	O
</s>
<s>
The	O
D	O
suffix	O
actually	O
has	O
no	O
official	O
designation	O
,	O
and	O
does	O
not	O
indicate	O
that	O
these	O
models	O
are	O
dual-core	B-Architecture
.	O
</s>
<s>
It	O
is	O
used	O
simply	O
to	O
distinguish	O
this	O
line	O
of	O
Celeron	B-Device
from	O
the	O
previous	O
,	O
lower	O
performing	O
Northwood	O
and	O
Willamette	O
series	O
,	O
and	O
also	O
from	O
the	O
mobile	O
series	O
,	O
the	O
Celeron	B-Device
M	O
(	O
which	O
also	O
uses	O
3xx	O
model	O
numbers	O
)	O
.	O
</s>
<s>
Unlike	O
the	O
Pentium	B-Device
D	I-Device
,	O
the	O
Celeron	B-Device
D	O
is	O
not	O
a	O
dual	B-Architecture
core	I-Architecture
processor	I-Architecture
.	O
</s>
<s>
The	O
Celeron	B-Device
D	O
was	O
a	O
major	O
performance	O
improvement	O
over	O
previous	O
NetBurst-based	O
Celerons	B-Device
.	O
</s>
<s>
A	O
test	O
using	O
a	O
variety	O
of	O
applications	O
,	O
run	O
by	O
Derek	O
Wilson	O
at	O
Anandtech.com,	O
showed	O
that	O
the	O
new	O
Celeron	B-Device
D	O
architecture	O
alone	O
offered	O
up	O
performance	O
improvements	O
on	O
average	O
of	O
>10	O
%	O
over	O
a	O
Northwood	O
Celeron	B-Device
when	O
both	O
CPUs	O
were	O
run	O
at	O
the	O
same	O
bus	O
and	O
clock	O
rate	O
.	O
</s>
<s>
This	O
CPU	O
also	O
had	O
the	O
addition	O
of	O
SSE3	B-General_Concept
instructions	O
and	O
the	O
higher	O
FSB	B-Architecture
which	O
only	O
contributed	O
to	O
this	O
already	O
impressive	O
gain	O
.	O
</s>
<s>
Despite	O
its	O
many	O
improvements	O
,	O
the	O
Prescott	O
core	B-Device
of	O
the	O
Celeron	B-Device
D	O
had	O
at	O
least	O
one	O
major	O
drawback	O
heat	O
.	O
</s>
<s>
Unlike	O
the	O
fairly	O
cool-running	O
Northwood	O
Celeron	B-Device
,	O
the	O
Prescott-256	O
had	O
a	O
class-rated	O
TDP	B-General_Concept
of	O
73W	O
,	O
which	O
prompted	O
Intel	O
to	O
include	O
a	O
more	O
intricate	O
copper	O
core/aluminum	O
finned	O
cooler	O
to	O
help	O
handle	O
the	O
additional	O
heat	O
.	O
</s>
<s>
In	O
mid-2005	O
,	O
Intel	O
refreshed	O
the	O
Celeron	B-Device
D	O
with	O
Intel	O
64	O
and	O
XD	B-General_Concept
Bit	I-General_Concept
(	O
eXecute	O
Disable	O
)	O
enabled	O
.	O
</s>
<s>
This	O
only	O
applied	O
to	O
LGA	B-Device
775	I-Device
Celeron	B-Device
Ds	O
.	O
</s>
<s>
There	O
are	O
no	O
Socket	B-Device
478	I-Device
CPUs	O
with	O
XD	B-General_Concept
Bit	I-General_Concept
capabilities	O
.	O
</s>
<s>
In	O
Intel	O
's	O
"	O
Family/Model/Stepping	O
"	O
scheme	O
,	O
Prescott	O
Celeron	B-Device
Ds	O
and	O
Pentium	B-General_Concept
4s	I-General_Concept
are	O
family	O
15	O
,	O
model	O
3	O
(	O
up	O
to	O
stepping	O
E0	O
)	O
or	O
4	O
(	O
stepping	O
E0	O
onwards	O
)	O
,	O
and	O
their	O
Intel	O
product	O
code	O
is	O
80546	O
or	O
80547	O
,	O
depending	O
on	O
socket	O
type	O
.	O
</s>
<s>
Based	O
on	O
the	O
Cedar	O
Mill	O
Pentium	B-General_Concept
4	I-General_Concept
core	B-Device
,	O
this	O
version	O
of	O
the	O
Celeron	B-Device
D	O
was	O
launched	O
May	O
28	O
,	O
2006	O
,	O
and	O
continued	O
the	O
3xx	O
naming	O
scheme	O
with	O
the	O
Celeron	B-Device
D	O
347	O
(	O
3.06GHz	O
)	O
,	O
352	O
(	O
3.2GHz	O
)	O
,	O
356	O
(	O
3.33GHz	O
)	O
,	O
360	O
(	O
3.46GHz	O
)	O
,	O
and	O
365	O
(	O
3.6GHz	O
)	O
.	O
</s>
<s>
The	O
Cedar	O
Mill	O
Celeron	B-Device
D	O
is	O
largely	O
the	O
same	O
as	O
the	O
Prescott-256	O
,	O
except	O
with	O
double	O
the	O
L2	O
cache	B-General_Concept
(	O
512KB	O
)	O
and	O
based	O
on	O
a	O
65nm	O
manufacturing	O
process	O
.	O
</s>
<s>
The	O
Cedar	O
Mill-512	O
Celeron	B-Device
D	O
is	O
LGA	B-Device
775	I-Device
exclusive	O
.	O
</s>
<s>
The	O
main	O
benefits	O
of	O
the	O
Cedar	O
Mill	O
Celerons	B-Device
over	O
the	O
Prescott	O
Celerons	B-Device
are	O
the	O
slightly	O
increased	O
performance	O
due	O
to	O
the	O
larger	O
L2	O
cache	B-General_Concept
,	O
higher	O
clock	O
rates	O
,	O
and	O
less	O
heat	O
dissipation	O
,	O
with	O
several	O
models	O
having	O
a	O
TDP	B-General_Concept
lowered	O
to	O
65W	O
from	O
Prescott	O
's	O
lowest	O
offering	O
of	O
73W	O
.	O
</s>
<s>
In	O
Intel	O
's	O
"	O
Family/Model/Stepping	O
"	O
scheme	O
,	O
Cedar	O
Mill	O
Celeron	B-Device
Ds	O
and	O
Pentium	B-General_Concept
4s	I-General_Concept
are	O
family	O
15	O
,	O
model	O
6	O
,	O
and	O
their	O
Intel	O
product	O
code	O
is	O
80552	O
.	O
</s>
<s>
The	O
Conroe-L	O
Celeron	B-Device
is	O
a	O
single-core	O
processor	O
built	O
on	O
the	O
Core	B-Device
microarchitecture	I-Device
and	O
is	O
thus	O
clocked	O
much	O
lower	O
than	O
the	O
Cedar	O
Mill	O
Celerons	B-Device
,	O
but	O
still	O
outperforms	O
them	O
.	O
</s>
<s>
It	O
is	O
based	O
on	O
the	O
65nm	O
Conroe-L	O
core	B-Device
,	O
and	O
uses	O
a	O
400-series	O
model	O
number	O
sequence	O
.	O
</s>
<s>
The	O
FSB	B-Architecture
was	O
increased	O
to	O
800MT/s	O
from	O
533MT/s	O
in	O
this	O
generation	O
,	O
and	O
the	O
TDP	B-General_Concept
was	O
decreased	O
from	O
65W	O
to	O
35W	O
.	O
</s>
<s>
As	O
is	O
traditional	O
with	O
Celerons	B-Device
,	O
it	O
does	O
not	O
have	O
Intel	O
VT-x	B-General_Concept
instruction	O
support	O
or	O
SpeedStep	B-Device
(	O
although	O
Enhanced	O
Halt	O
State	O
is	O
enabled	O
,	O
allowing	O
the	O
Celerons	B-Device
to	O
lower	O
the	O
multiplier	O
to	O
6×	O
and	O
decrease	O
core	B-Device
voltage	O
while	O
idle	O
)	O
.	O
</s>
<s>
All	O
Conroe-L	O
models	O
are	O
single-core	O
processors	O
for	O
the	O
value	O
segment	O
of	O
the	O
market	O
,	O
much	O
like	O
the	O
AMD	O
K8-based	O
Sempron	O
.	O
</s>
<s>
The	O
full	O
name	O
of	O
the	O
processor	O
is	O
Celeron	B-Device
220	O
and	O
is	O
soldered	O
on	O
the	O
D201GLY2	O
motherboard	B-Device
.	O
</s>
<s>
With	O
1.2GHz	O
and	O
a	O
512KB	O
L2cache	O
it	O
has	O
a	O
TDP	B-General_Concept
of	O
19W	O
and	O
can	O
be	O
cooled	O
passively	O
.	O
</s>
<s>
The	O
Celeron	B-Device
220	O
is	O
the	O
successor	O
of	O
the	O
Celeron	B-Device
215	O
which	O
is	O
based	O
on	O
a	O
Yonah	B-Device
core	B-Device
and	O
used	O
on	O
the	O
D201GLY	O
motherboard	B-Device
.	O
</s>
<s>
Intel	O
launched	O
the	O
dual	B-Architecture
core	I-Architecture
Celeron	B-Device
E1xxx	O
processor	O
line	O
on	O
January	O
20	O
,	O
2008	O
,	O
based	O
on	O
the	O
Allendale	O
core	B-Device
.	O
</s>
<s>
The	O
CPU	O
has	O
800MT/s	O
FSB	B-Architecture
,	O
65W	O
TDP	B-General_Concept
and	O
uses	O
512KB	O
of	O
the	O
chip	O
's	O
2MB	O
L2cache	O
,	O
significantly	O
limiting	O
performance	O
for	O
uses	O
such	O
as	O
gaming	O
.	O
</s>
<s>
New	O
features	O
to	O
the	O
Celeron	B-Device
family	O
included	O
full	O
enhanced	O
halt	O
state	O
and	O
enhanced	O
Intel	B-Device
SpeedStep	I-Device
technology	O
.	O
</s>
<s>
It	O
is	O
compatible	O
with	O
other	O
Allendale-based	O
CPUs	O
such	O
as	O
the	O
Core	B-Device
2	I-Device
Duo	O
E4xxx	O
and	O
Pentium	B-Device
Dual-Core	I-Device
E2xxx	O
.	O
</s>
<s>
The	O
Celeron	B-Device
E3000	O
series	O
,	O
starting	O
with	O
E3200	O
and	O
E3300	O
,	O
was	O
released	O
in	O
August	O
2009	O
,	O
featuring	O
the	O
Wolfdale-3M	O
core	B-Device
used	O
in	O
Pentium	B-Device
Dual-Core	I-Device
E5000	O
,	O
Pentium	B-General_Concept
E6000	O
and	O
Core	B-Device
2	I-Device
Duo	O
E7000	O
series	O
.	O
</s>
<s>
The	O
main	O
difference	O
to	O
Allendale-based	O
Celeron	B-Device
processors	O
is	O
the	O
support	O
for	O
Intel	O
VT-x	B-General_Concept
and	O
increased	O
performance	O
due	O
to	O
the	O
double	O
L2	O
Cache	B-General_Concept
of	O
1MB	O
.	O
</s>
<s>
With	O
the	O
introduction	O
of	O
the	O
Desktop	B-Device
Core	B-Device
i3	O
and	O
Core	B-Device
i5	O
processor	O
code	O
named	O
Clarkdale	O
in	O
January	O
2010	O
,	O
Intel	O
also	O
added	O
a	O
new	O
Celeron	B-Device
line	O
,	O
starting	O
with	O
the	O
Celeron	B-Device
G1101	O
.	O
</s>
<s>
This	O
is	O
the	O
first	O
Celeron	B-Device
to	O
come	O
with	O
on-chip	O
PCI	O
Express	O
and	O
integrated	O
graphics	O
.	O
</s>
<s>
Despite	O
using	O
the	O
same	O
Clarkdale	O
chip	O
as	O
the	O
Core	B-Device
i5-6xx	O
line	O
,	O
it	O
does	O
not	O
support	O
Turbo	B-Device
Boost	I-Device
,	O
HyperThreading	B-Operating_System
,	O
VT-d	O
,	O
SMT	B-Operating_System
,	O
Trusted	B-Device
Execution	I-Device
Technology	I-Device
or	O
AES	B-Algorithm
new	I-Algorithm
instructions	I-Algorithm
,	O
and	O
it	O
comes	O
with	O
only	O
2MB	O
of	O
third-level	O
cache	B-General_Concept
enabled	O
.	O
</s>
<s>
The	O
Celeron	B-Device
P1053	O
is	O
an	O
embedded	O
processor	O
for	O
Socket	B-Device
1366	I-Device
from	O
the	O
Jasper	O
Forest	O
family	O
.	O
</s>
<s>
The	O
Jasper	O
Forest	O
chip	O
is	O
closely	O
related	O
to	O
Lynnfield	B-Device
and	O
contains	O
four	O
cores	O
,	O
8MB	O
of	O
L3cache	O
and	O
a	O
QPI	O
interface	O
,	O
but	O
most	O
of	O
these	O
are	O
disabled	O
in	O
the	O
Celeron	B-Device
version	O
,	O
leaving	O
a	O
single	O
core	B-Device
with	O
2MB	O
of	O
L3cache	O
.	O
</s>
<s>
The	O
Sandy	O
Bridge-based	O
Celeron	B-Device
processors	O
were	O
released	O
in	O
2011	O
.	O
</s>
<s>
They	O
are	O
LGA	B-Device
1155	I-Device
processors	O
(	O
available	O
in	O
single	O
-	O
and	O
dual-core	B-Architecture
versions	O
)	O
with	O
integrated	O
Intel	O
HD	O
Graphics	O
GPU	O
and	O
containing	O
up	O
to	O
2MB	O
of	O
L3cache	O
.	O
</s>
<s>
Hyper-Threading	B-Operating_System
is	O
available	O
on	O
some	O
single-core	O
models	O
,	O
namely	O
G460	O
,	O
G465	O
and	O
G470	O
.	O
</s>
<s>
All	O
Celerons	B-Device
of	O
this	O
generation	O
belong	O
in	O
the	O
G16xx	O
series	O
.	O
</s>
<s>
They	O
give	O
some	O
boost	O
in	O
performance	O
over	O
Sandy	O
Bridge-based	O
Celerons	B-Device
due	O
to	O
a	O
22nm	O
die	O
shrink	O
,	O
as	O
well	O
as	O
some	O
other	O
minor	O
improvements	O
.	O
</s>
<s>
All	O
Celerons	B-Device
of	O
this	O
generation	O
added	O
AES-NI	O
and	O
RDRAND	B-Language
instruction	O
set	O
.	O
</s>
<s>
Similar	O
to	O
the	O
Mendocino	O
(	O
Celeron-A	O
)	O
:	O
0.25μm	O
,	O
32KB	O
L1	O
cache	B-General_Concept
and	O
128KB	O
L2	O
cache	B-General_Concept
,	O
but	O
uses	O
a	O
lower	O
voltage	O
(	O
1.5	O
–	O
1.9V	O
)	O
and	O
two	O
power-saving	O
modes	O
:	O
Quick	O
Start	O
,	O
and	O
Deep	O
Sleep	O
.	O
</s>
<s>
Packaged	O
in	O
the	O
small	O
,	O
615-pin	O
BGA2	B-Algorithm
or	O
Micro-PGA2	B-Device
package	O
.	O
</s>
<s>
These	O
were	O
the	O
first	O
Mobile	B-Device
Celerons	I-Device
based	O
on	O
the	O
Tualatin	O
core	B-Device
.	O
</s>
<s>
They	O
differed	O
from	O
their	O
desktop	B-Device
counterparts	O
in	O
that	O
the	O
Mobile	O
series	O
were	O
offered	O
in	O
both	O
100MHz	O
and	O
133MHz	O
FSB	B-Architecture
.	O
</s>
<s>
Like	O
the	O
desktop	B-Device
Tualatins	O
,	O
these	O
chips	O
had	O
256KB	O
of	O
L2	O
cache	B-General_Concept
.	O
</s>
<s>
These	O
are	O
the	O
Mobile	B-Device
Celeron	I-Device
range	O
used	O
in	O
laptops	B-Device
.	O
</s>
<s>
Also	O
based	O
on	O
the	O
Northwood	O
core	B-Device
,	O
they	O
feature	O
a	O
256KB	O
L2	O
cache	B-General_Concept
.	O
</s>
<s>
These	O
Celeron	B-Device
processors	O
were	O
a	O
good	O
deal	O
higher	O
performing	O
than	O
the	O
desktop	B-Device
counterparts	O
because	O
of	O
their	O
larger	O
L2	O
cache	B-General_Concept
sizes	O
.	O
</s>
<s>
They	O
were	O
eventually	O
replaced	O
by	O
the	O
Celeron	B-Device
M	O
brand	O
which	O
is	O
built	O
around	O
the	O
Pentium	B-Architecture
M	I-Architecture
processor	O
design	O
.	O
</s>
<s>
This	O
Celeron	B-Device
(	O
sold	O
under	O
the	O
Celeron	B-Device
M	O
brand	O
)	O
is	O
based	O
on	O
the	O
Banias	O
Pentium	B-Architecture
M	I-Architecture
,	O
and	O
differs	O
from	O
its	O
parent	O
in	O
that	O
it	O
has	O
half	O
the	O
L2	O
cache	B-General_Concept
,	O
and	O
does	O
not	O
support	O
the	O
clock-varying	O
SpeedStep	B-Device
technology	O
.	O
</s>
<s>
It	O
performs	O
reasonably	O
well	O
compared	O
to	O
the	O
Pentium	B-Architecture
M	I-Architecture
,	O
but	O
battery	O
life	O
is	O
noticeably	O
shorter	O
on	O
a	O
Celeron	B-Device
M	O
–	O
based	O
notebook	B-Device
than	O
it	O
is	O
on	O
a	O
comparable	O
Pentium	B-Architecture
M	I-Architecture
notebook	B-Device
.	O
</s>
<s>
A	O
system	O
based	O
on	O
the	O
Celeron	B-Device
M	O
processor	O
may	O
not	O
use	O
the	O
Centrino	B-Device
brand	O
name	O
,	O
regardless	O
of	O
what	O
chipset	O
and	O
Wi-Fi	O
components	O
are	O
used	O
.	O
</s>
<s>
In	O
Intel	O
's	O
"	O
Family/Model/Stepping	O
"	O
scheme	O
,	O
Banias	O
Celeron	B-Device
Ms	O
and	O
Pentium	B-Architecture
Ms	I-Architecture
are	O
family	O
6	O
,	O
model	O
9	O
and	O
their	O
Intel	O
product	O
code	O
is	O
80535	O
.	O
</s>
<s>
The	O
Shelton	O
core	B-Device
is	I-Device
a	O
Banias	O
core	B-Device
without	O
any	O
L2	O
cache	B-General_Concept
and	O
SpeedStep	B-Device
.	O
</s>
<s>
It	O
is	O
used	O
in	O
Intel	O
's	O
small	O
form	O
factor	O
D845GVSH	O
motherboard	B-Device
,	O
intended	O
for	O
Asian	O
and	O
South	O
American	O
markets	O
.	O
</s>
<s>
The	O
processor	O
identifies	O
itself	O
as	O
a	O
"	O
Intel	B-Device
Celeron	I-Device
1.0B	O
GHz	O
"	O
,	O
to	O
differentiate	O
it	O
from	O
the	O
previous	O
Coppermine-128	O
and	O
Tualatin	O
1.0GHz	O
processors	O
.	O
</s>
<s>
The	O
Shelton'08	O
is	O
a	O
basic	O
platform	O
for	O
a	O
low	O
cost	O
notebook	B-Device
released	O
by	O
Intel	O
at	O
January	O
2008	O
.	O
</s>
<s>
The	O
platform	O
uses	O
Intel	O
's	O
single-core	O
Diamondville	O
CPU	O
with	O
a	O
clock	O
frequency	O
of	O
1.6GHz	O
and	O
a	O
533MT/s	O
FSB	B-Architecture
and	O
power	O
consumption	O
of	O
3.5W	O
.	O
</s>
<s>
A	O
90nm	O
Celeron	B-Device
M	O
with	O
half	O
of	O
the	O
L2	O
cache	B-General_Concept
of	O
the	O
90nm	O
Dothan	O
Pentium	B-Architecture
Ms	I-Architecture
(	O
twice	O
the	O
L2	O
cache	B-General_Concept
of	O
the	O
130nm	O
Celeron	B-Device
Ms	O
,	O
though	O
)	O
,	O
and	O
,	O
like	O
its	O
predecessor	O
,	O
lacking	O
SpeedStep	B-Device
.	O
</s>
<s>
The	O
first	O
Celeron	B-Device
Ms	O
that	O
supports	O
the	O
XD	B-General_Concept
bit	I-General_Concept
was	O
released	O
in	O
January	O
2005	O
,	O
in	O
general	O
any	O
Celeron	B-Device
M	O
released	O
after	O
that	O
supports	O
the	O
XD	B-General_Concept
bit	I-General_Concept
.	O
</s>
<s>
There	O
is	O
also	O
a	O
512KB	O
low	O
voltage	O
version	O
that	O
was	O
used	O
in	O
the	O
early	O
ASUS	B-Device
Eee	I-Device
PC	I-Device
models	O
.	O
</s>
<s>
In	O
Intel	O
's	O
"	O
Family/Model/Stepping	O
"	O
scheme	O
,	O
Dothan	O
Celeron	B-Device
Ms	O
and	O
Pentium	B-Architecture
Ms	I-Architecture
are	O
family	O
6	O
,	O
model	O
13	O
and	O
their	O
Intel	O
product	O
code	O
is	O
80536	O
.	O
</s>
<s>
The	O
Celeron	B-Device
M	O
400-series	O
is	O
a	O
65nm	O
Celeron	B-Device
M	O
based	O
on	O
the	O
single-core	O
Yonah	B-Device
chip	O
,	O
like	O
the	O
Core	B-Device
Solo	O
.	O
</s>
<s>
Like	O
its	O
predecessors	O
in	O
the	O
Celeron	B-Device
M	O
series	O
,	O
this	O
Celeron	B-Device
M	O
has	O
half	O
of	O
the	O
L2	O
cache	B-General_Concept
(	O
1MB	O
)	O
of	O
Core	B-Device
Solo	O
and	O
lacks	O
SpeedStep	B-Device
.	O
</s>
<s>
This	O
core	B-Device
also	O
brings	O
new	O
features	O
to	O
Celeron	B-Device
M	O
including	O
a	O
higher	O
front	B-Architecture
side	I-Architecture
bus	I-Architecture
(	O
533MT/s	O
)	O
,	O
SSE3	B-General_Concept
instructions	O
.	O
</s>
<s>
September	O
2006	O
and	O
January	O
4	O
,	O
2008	O
,	O
mark	O
a	O
discontinuation	O
of	O
many	O
Celeron	B-Device
M	O
branded	O
CPUs	O
.	O
</s>
<s>
The	O
Celeron	B-Device
M	O
523	O
(	O
933MHz	O
ULV	O
)	O
,	O
M520	O
(	O
1.6GHz	O
)	O
,	O
M530	O
(	O
1.73GHz	O
)	O
,	O
530	O
(	O
1.73GHz	O
)	O
,	O
540	O
(	O
1.86GHz	O
)	O
,	O
550	O
(	O
2.0GHz	O
)	O
,	O
560	O
(	O
2.13GHz	O
)	O
,	O
570	O
(	O
2.26GHz	O
)	O
are	O
single-core	O
65nm	O
CPUs	O
based	O
on	O
the	O
Merom	B-Device
Core	B-Device
2	I-Device
architecture	O
.	O
</s>
<s>
They	O
feature	O
a	O
533MT/s	O
FSB	B-Architecture
,	O
1MB	O
of	O
L2	O
cache	B-General_Concept
(	O
half	O
that	O
of	O
the	O
low	O
end	O
Core	B-Device
2	I-Device
Duo	O
's	O
2MB	O
cache	B-General_Concept
)	O
,	O
XD-bit	O
support	O
,	O
and	O
Intel	O
64	O
technology	O
,	O
but	O
lack	O
SpeedStep	B-Device
and	O
Virtualization	B-General_Concept
Technology	I-General_Concept
.	O
</s>
<s>
Two	O
different	O
processor	O
models	O
are	O
used	O
with	O
identical	O
part	O
numbers	O
with	O
the	O
same	O
part	O
numbers	O
,	O
single-core	O
Merom-L	O
with	O
1MB	O
cache	B-General_Concept
and	O
dual-core	B-Architecture
Merom	B-Device
with	O
4MB	O
L2cache	O
that	O
have	O
the	O
extra	O
cache	B-General_Concept
and	O
core	B-Device
disabled	O
.	O
</s>
<s>
Celeron	B-Device
M	O
523	O
,	O
M	O
520	O
and	O
M	O
530	O
are	O
Socket	O
M-based	O
,	O
while	O
Celeron	B-Device
530	O
through	O
570	O
(	O
without	O
the	O
M	O
)	O
are	O
for	O
Socket	B-Device
P	I-Device
.	O
January	O
4	O
,	O
2008	O
,	O
marked	O
the	O
discontinuation	O
of	O
Merom	B-Device
CPUs	O
.	O
</s>
<s>
The	O
Celeron	B-Device
573	O
(	O
1GHz	O
,	O
ULV	O
)	O
,	O
575	O
(	O
2GHz	O
)	O
and	O
585	O
(	O
2.16GHz	O
)	O
are	O
based	O
on	O
the	O
Merom-2M	O
core	B-Device
with	O
only	O
one	O
core	B-Device
and	O
1MB	O
L2cache	O
enabled	O
.	O
</s>
<s>
They	O
are	O
similar	O
to	O
the	O
Merom	B-Device
and	O
Merom-L	O
based	O
Celerons	B-Device
but	O
have	O
a	O
faster	O
667MT/s	O
FSB	B-Architecture
.	O
</s>
<s>
The	O
Celeron	B-Device
T1xxx	O
processors	O
are	O
also	O
based	O
on	O
the	O
Merom-2M	O
chips	O
but	O
have	O
both	O
cores	O
enabled	O
.	O
</s>
<s>
The	O
earlier	O
T1400	O
(	O
1.73GHz	O
)	O
and	O
T1500	O
(	O
1.86GHz	O
)	O
versions	O
have	O
a	O
533MT/s	O
FSB	B-Architecture
and	O
512B	O
L2cache	O
,	O
while	O
the	O
more	O
recent	O
T1600	O
(	O
1.66GHz	O
)	O
and	O
T1700	O
(	O
1.83GHz	O
)	O
versions	O
have	O
667MT/s	O
and	O
1MB	O
L2cache	O
enabled	O
but	O
come	O
with	O
a	O
lower	O
clock	O
frequency	O
.	O
</s>
<s>
At	O
the	O
same	O
time	O
as	O
the	O
dual-core	B-Architecture
Merom-2M	O
,	O
Intel	O
introduced	O
the	O
first	O
45nm	O
Celeron	B-Device
processor	O
based	O
on	O
the	O
Penryn-3M	O
core	B-Device
with	O
800MT/s	O
FSB	B-Architecture
,	O
1MB	O
L2	O
cache	B-General_Concept
and	O
one	O
core	B-Device
enabled	O
.	O
</s>
<s>
This	O
includes	O
the	O
Celeron	B-Device
M	O
7xx	O
Consumer	B-Device
Ultra-Low	I-Device
Voltage	I-Device
(	O
CULV	B-Device
)	O
series	O
starting	O
at	O
1.2GHz	O
and	O
the	O
later	O
Celeron	B-Device
900	O
(	O
2.2GHz	O
)	O
.	O
</s>
<s>
The	O
initial	O
45nm	O
dual-core	B-Architecture
Celeron	B-Device
processor	O
was	O
released	O
in	O
June	O
2009	O
and	O
is	O
also	O
based	O
on	O
Penryn-3M	O
.	O
</s>
<s>
The	O
Celeron	B-Device
T3000	O
(	O
1.8GHz	O
)	O
and	O
T3100	O
(	O
1.9GHz	O
)	O
again	O
come	O
with	O
1MB	O
of	O
L2	O
cache	B-General_Concept
enabled	O
and	O
an	O
800MT/s	O
FSB	B-Architecture
.	O
</s>
<s>
In	O
September	O
2009	O
,	O
Intel	O
also	O
started	O
the	O
dual-core	B-Architecture
CULV	B-Device
Celeron	B-Device
SU2000	O
series	O
,	O
again	O
with	O
1MB	O
L2	O
cache	B-General_Concept
.	O
</s>
<s>
Despite	O
the	O
similar	O
name	O
,	O
they	O
are	O
very	O
different	O
from	O
Pentium	B-General_Concept
SU2000	O
(	O
with	O
2MB	O
L2	O
cache	B-General_Concept
and	O
one	O
active	O
core	B-Device
)	O
and	O
Pentium	B-General_Concept
T3000	O
(	O
based	O
on	O
the	O
65nm	O
Merom	B-Device
processor	O
)	O
.	O
</s>
<s>
The	O
Arrandale-based	O
Celeron	B-Device
P4xxx	O
and	O
U3xxx	O
lines	O
are	O
low-end	O
versions	O
of	O
the	O
Pentium	B-General_Concept
P6xxx	O
and	O
U5xxx	O
lines	O
,	O
originally	O
released	O
as	O
the	O
mobile	O
dual-core	B-Architecture
lines	O
of	O
Core	B-Device
i3/i5/i7	O
.	O
</s>
<s>
Like	O
the	O
Clarkdale-based	O
Celeron	B-Device
G1xxx	O
,	O
they	O
use	O
2MB	O
of	O
L3cache	O
,	O
which	O
is	O
the	O
amount	O
that	O
the	O
earlier	O
"	O
Penryn	O
"	O
based	O
CPUs	O
used	O
in	O
the	O
Pentium	B-General_Concept
brand	O
as	O
their	O
L2cache	O
.	O
</s>
<s>
Like	O
all	O
Arrandale	O
processors	O
,	O
the	O
Celeron	B-Device
P4xxx	O
and	O
U3xxx	O
use	O
an	O
integrated	O
graphics	O
core	B-Device
.	O
</s>
<s>
The	O
Celeron	B-Device
B8xx	O
processors	O
released	O
in	O
2011	O
follow	O
the	O
Arrandale	O
line	O
.	O
</s>
<s>
They	O
are	O
Dual-Core	B-Architecture
processors	I-Architecture
with	O
integrated	O
graphics	O
and	O
use	O
the	O
same	O
chips	O
as	O
the	O
Pentium	B-General_Concept
B9xx	O
and	O
Core	B-Device
i3/i5/i7	O
-2xxx	O
mobile	O
processors	O
,	O
but	O
with	O
Turbo-Boost	O
,	O
Hyper-Threading	B-Operating_System
,	O
VT-d	O
,	O
TXT	O
and	O
AES-NI	O
disabled	O
and	O
the	O
L3	O
cache	B-General_Concept
reduced	O
to	O
2MB	O
.	O
</s>
<s>
As	O
a	O
budget	O
processor	O
,	O
the	O
Celeron	B-Device
does	O
not	O
support	O
a	O
dual-processor	B-Operating_System
configuration	O
using	O
multiple	O
CPU	O
sockets	O
,	O
however	O
it	O
has	O
been	O
discovered	O
that	O
multiprocessing	B-Operating_System
could	O
be	O
enabled	O
on	O
Slot	B-Device
1	I-Device
Celeron	B-Device
processors	O
by	O
connecting	O
a	O
pin	O
on	O
the	O
CPU	B-Architecture
core	I-Architecture
to	O
a	O
contact	O
on	O
the	O
processor	O
card	O
's	O
connector	O
.	O
</s>
<s>
In	O
addition	O
,	O
Mendocino	O
Socket	B-Device
370	I-Device
processors	O
can	O
use	O
multiprocessing	B-Operating_System
when	O
used	O
on	O
specific	O
dual	O
Slot	B-Device
1	I-Device
motherboards	B-Device
by	O
using	O
a	O
slot	O
adapter	O
.	O
</s>
<s>
The	O
unofficial	O
SMP	O
support	O
was	O
removed	O
in	O
the	O
Coppermine	O
Celerons	B-Device
,	O
and	O
dual-socket	O
support	O
is	O
now	O
limited	O
to	O
higher-end	O
Xeon	O
server-class	O
processors	O
.	O
</s>
<s>
Conroe/Allendale	O
based	O
Celeron	B-Device
processors	O
and	O
later	O
support	O
multiprocessing	B-Operating_System
using	O
multi-core	B-Architecture
chips	O
,	O
but	O
are	O
still	O
limited	O
to	O
one	O
socket	O
.	O
</s>
<s>
The	O
ABIT	B-Operating_System
BP6	I-Operating_System
motherboard	B-Device
also	O
allows	O
two	O
Mendocino	O
Socket	B-Device
370	I-Device
Celeron	B-Device
processors	O
to	O
operate	O
in	O
a	O
symmetric	B-Operating_System
multiprocessing	I-Operating_System
(	O
SMP	O
)	O
configuration	O
without	O
any	O
modification	O
to	O
the	O
CPUs	O
or	O
the	O
motherboard	B-Device
.	O
</s>
