<s>
Cache	B-General_Concept
prefetching	I-General_Concept
is	O
a	O
technique	O
used	O
by	O
computer	O
processors	O
to	O
boost	O
execution	O
performance	O
by	O
fetching	O
instructions	O
or	O
data	O
from	O
their	O
original	O
storage	O
in	O
slower	O
memory	O
to	O
a	O
faster	O
local	O
memory	O
before	O
it	O
is	O
actually	O
needed	O
(	O
hence	O
the	O
term	O
'	O
prefetch	O
 '	O
)	O
.	O
</s>
<s>
Most	O
modern	O
computer	O
processors	O
have	O
fast	O
and	O
local	O
cache	B-General_Concept
memory	I-General_Concept
in	O
which	O
prefetched	O
data	O
is	O
held	O
until	O
it	O
is	O
required	O
.	O
</s>
<s>
Because	O
of	O
their	O
design	O
,	O
accessing	O
cache	B-General_Concept
memories	I-General_Concept
is	O
typically	O
much	O
faster	O
than	O
accessing	O
main	O
memory	O
,	O
so	O
prefetching	O
data	O
and	O
then	O
accessing	O
it	O
from	O
caches	B-General_Concept
is	O
usually	O
many	O
orders	O
of	O
magnitude	O
faster	O
than	O
accessing	O
it	O
directly	O
from	O
main	O
memory	O
.	O
</s>
<s>
Prefetching	O
can	O
be	O
done	O
with	O
non-blocking	O
cache	B-Architecture
control	I-Architecture
instructions	I-Architecture
.	O
</s>
<s>
Cache	B-General_Concept
prefetching	I-General_Concept
can	O
either	O
fetch	O
data	O
or	O
instructions	O
into	O
cache	B-General_Concept
.	O
</s>
<s>
The	O
first	O
mainstream	O
microprocessors	O
to	O
use	O
some	O
form	O
of	O
instruction	B-General_Concept
prefetch	I-General_Concept
were	O
the	O
Intel	B-General_Concept
8086	I-General_Concept
(	O
six	O
bytes	O
)	O
and	O
the	O
Motorola	B-Device
68000	I-Device
(	O
four	O
bytes	O
)	O
.	O
</s>
<s>
Cache	B-General_Concept
prefetching	I-General_Concept
can	O
be	O
accomplished	O
either	O
by	O
hardware	O
or	O
by	O
software	O
.	O
</s>
<s>
Hardware	O
based	O
prefetching	O
is	O
typically	O
accomplished	O
by	O
having	O
a	O
dedicated	O
hardware	O
mechanism	O
in	O
the	O
processor	O
that	O
watches	O
the	O
stream	O
of	O
instructions	O
or	O
data	O
being	O
requested	O
by	O
the	O
executing	O
program	O
,	O
recognizes	O
the	O
next	O
few	O
elements	O
that	O
the	O
program	O
might	O
need	O
based	O
on	O
this	O
stream	O
and	O
prefetches	O
into	O
the	O
processor	O
's	O
cache	B-General_Concept
.	O
</s>
<s>
Software	O
based	O
prefetching	O
is	O
typically	O
accomplished	O
by	O
having	O
the	O
compiler	B-Language
analyze	O
the	O
code	O
and	O
insert	O
additional	O
"	O
prefetch	O
"	O
instructions	O
in	O
the	O
program	O
during	O
compilation	B-Language
itself	O
.	O
</s>
<s>
Stream	O
buffers	B-General_Concept
were	O
developed	O
based	O
on	O
the	O
concept	O
of	O
"	O
one	O
block	O
lookahead	O
(	O
OBL	O
)	O
scheme	O
"	O
proposed	O
by	O
Alan	O
Jay	O
Smith	O
.	O
</s>
<s>
Stream	O
buffers	B-General_Concept
are	O
one	O
of	O
the	O
most	O
common	O
hardware	O
based	O
prefetching	O
techniques	O
in	O
use	O
.	O
</s>
<s>
The	O
basic	O
idea	O
is	O
that	O
the	O
cache	B-General_Concept
miss	O
address	O
(	O
and	O
subsequent	O
addresses	O
)	O
are	O
fetched	O
into	O
a	O
separate	O
buffer	B-General_Concept
of	O
depth	O
.	O
</s>
<s>
This	O
buffer	B-General_Concept
is	O
called	O
a	O
stream	O
buffer	B-General_Concept
and	O
is	O
separate	O
from	O
cache	B-General_Concept
.	O
</s>
<s>
The	O
processor	O
then	O
consumes	O
data/instructions	O
from	O
the	O
stream	O
buffer	B-General_Concept
if	O
the	O
address	O
associated	O
with	O
the	O
prefetched	O
blocks	O
match	O
the	O
requested	O
address	O
generated	O
by	O
the	O
program	O
executing	O
on	O
the	O
processor	O
.	O
</s>
<s>
If	O
the	O
stream	O
buffer	B-General_Concept
can	O
hold	O
4	O
blocks	O
,	O
then	O
we	O
would	O
prefetch	O
A+1	O
,	O
A+2	O
,	O
A+3	O
,	O
A+4	O
and	O
hold	O
those	O
in	O
the	O
allocated	O
stream	O
buffer	B-General_Concept
.	O
</s>
<s>
If	O
the	O
processor	O
consumes	O
A+1	O
next	O
,	O
then	O
it	O
shall	O
be	O
moved	O
"	O
up	O
"	O
from	O
the	O
stream	O
buffer	B-General_Concept
to	O
the	O
processor	O
's	O
cache	B-General_Concept
.	O
</s>
<s>
The	O
first	O
entry	O
of	O
the	O
stream	O
buffer	B-General_Concept
would	O
now	O
be	O
A+2	O
and	O
so	O
on	O
.	O
</s>
<s>
This	O
mechanism	O
can	O
be	O
scaled	O
up	O
by	O
adding	O
multiple	O
such	O
'	O
stream	O
buffers	B-General_Concept
 '	O
-	O
each	O
of	O
which	O
would	O
maintain	O
a	O
separate	O
prefetch	O
stream	O
.	O
</s>
<s>
For	O
each	O
new	O
miss	O
,	O
there	O
would	O
be	O
a	O
new	O
stream	O
buffer	B-General_Concept
allocated	O
and	O
it	O
would	O
operate	O
in	O
a	O
similar	O
way	O
as	O
described	O
above	O
.	O
</s>
<s>
The	O
ideal	O
depth	O
of	O
the	O
stream	O
buffer	B-General_Concept
is	O
something	O
that	O
is	O
subject	O
to	O
experimentation	O
against	O
various	O
benchmarks	O
and	O
depends	O
on	O
the	O
rest	O
of	O
the	O
microarchitecture	B-General_Concept
involved	O
.	O
</s>
<s>
Compiler	B-Language
directed	O
prefetching	O
is	O
widely	O
used	O
within	O
loops	O
with	O
a	O
large	O
number	O
of	O
iterations	O
.	O
</s>
<s>
In	O
this	O
technique	O
,	O
the	O
compiler	B-Language
predicts	O
future	O
cache	B-General_Concept
misses	O
and	O
inserts	O
a	O
prefetch	O
instruction	O
based	O
on	O
the	O
miss	B-General_Concept
penalty	I-General_Concept
and	O
execution	B-Library
time	I-Library
of	O
the	O
instructions	O
.	O
</s>
<s>
One	O
main	O
advantage	O
of	O
software	O
prefetching	O
is	O
that	O
it	O
reduces	O
the	O
number	O
of	O
compulsory	O
cache	B-General_Concept
misses	O
.	O
</s>
<s>
The	O
following	O
example	O
shows	O
how	O
a	O
prefetch	O
instruction	O
would	O
be	O
added	O
into	O
code	O
to	O
improve	O
cache	B-General_Concept
performance	I-General_Concept
.	O
</s>
<s>
Therefore	O
,	O
we	O
can	O
prefetch	O
the	O
elements	O
that	O
are	O
going	O
to	O
be	O
accessed	O
in	O
future	O
iterations	O
by	O
inserting	O
a	O
"	O
prefetch	O
"	O
instruction	O
as	O
shown	O
below:Here	O
,	O
the	O
prefetch	O
stride	O
,	O
depends	O
on	O
two	O
factors	O
,	O
the	O
cache	B-General_Concept
miss	B-General_Concept
penalty	I-General_Concept
and	O
the	O
time	O
it	O
takes	O
to	O
execute	O
a	O
single	O
iteration	O
of	O
the	O
for	O
loop	O
.	O
</s>
<s>
For	O
instance	O
,	O
if	O
one	O
iteration	O
of	O
the	O
loop	O
takes	O
7	O
cycles	O
to	O
execute	O
,	O
and	O
the	O
cache	B-General_Concept
miss	B-General_Concept
penalty	I-General_Concept
is	O
49	O
cycles	O
then	O
we	O
should	O
have	O
-	O
which	O
means	O
that	O
we	O
prefetch	O
7	O
elements	O
ahead	O
.	O
</s>
<s>
Now	O
,	O
with	O
this	O
arrangement	O
,	O
the	O
first	O
7	O
accesses	O
(	O
i	O
=	O
0->6	O
)	O
will	O
still	O
be	O
misses	O
(	O
under	O
the	O
simplifying	O
assumption	O
that	O
each	O
element	O
of	O
array1	O
is	O
in	O
a	O
separate	O
cache	B-General_Concept
line	O
of	O
its	O
own	O
)	O
.	O
</s>
<s>
While	O
software	O
prefetching	O
requires	O
programmer	O
or	O
compiler	B-Language
intervention	O
,	O
hardware	O
prefetching	O
requires	O
special	O
hardware	O
mechanisms	O
.	O
</s>
<s>
Software	O
prefetching	O
works	O
well	O
only	O
with	O
loops	O
where	O
there	O
is	O
regular	O
array	O
access	O
as	O
the	O
programmer	O
has	O
to	O
hand	O
code	O
the	O
prefetch	O
instructions	O
,	O
whereas	O
hardware	O
prefetchers	O
work	O
dynamically	O
based	O
on	O
the	O
program	O
's	O
behavior	O
at	B-Library
runtime	I-Library
.	O
</s>
<s>
The	O
prefetches	O
themselves	O
might	O
result	O
in	O
new	O
misses	O
if	O
the	O
prefetched	O
blocks	O
are	O
placed	O
directly	O
into	O
the	O
cache	B-General_Concept
.	O
</s>
