<s>
A	O
CPU	O
cache	B-General_Concept
is	O
a	O
hardware	O
cache	B-General_Concept
used	O
by	O
the	O
central	B-General_Concept
processing	I-General_Concept
unit	I-General_Concept
(	O
CPU	O
)	O
of	O
a	O
computer	O
to	O
reduce	O
the	O
average	O
cost	O
(	O
time	O
or	O
energy	O
)	O
to	O
access	O
data	B-General_Concept
from	O
the	O
main	O
memory	O
.	O
</s>
<s>
A	O
cache	B-General_Concept
is	O
a	O
smaller	O
,	O
faster	O
memory	O
,	O
located	O
closer	O
to	O
a	O
processor	O
core	O
,	O
which	O
stores	O
copies	O
of	O
the	O
data	B-General_Concept
from	O
frequently	O
used	O
main	O
memory	B-General_Concept
locations	I-General_Concept
.	O
</s>
<s>
Most	O
CPUs	O
have	O
a	O
hierarchy	O
of	O
multiple	O
cache	B-General_Concept
levels	O
(	O
L1	O
,	O
L2	O
,	O
often	O
L3	O
,	O
and	O
rarely	O
even	O
L4	O
)	O
,	O
with	O
different	O
instruction-specific	O
and	O
data-specific	O
caches	B-General_Concept
at	O
level	O
1	O
.	O
</s>
<s>
The	O
cache	B-General_Concept
memory	I-General_Concept
is	O
typically	O
implemented	O
with	O
static	B-Architecture
random-access	I-Architecture
memory	I-Architecture
(	O
SRAM	B-Architecture
)	O
,	O
in	O
modern	O
CPUs	O
by	O
far	O
the	O
largest	O
part	O
of	O
them	O
by	O
chip	O
area	O
,	O
but	O
SRAM	B-Architecture
is	O
not	O
always	O
used	O
for	O
all	O
levels	O
(	O
of	O
I	O
-	O
or	O
D-cache	O
)	O
,	O
or	O
even	O
any	O
level	O
,	O
sometimes	O
some	O
latter	O
or	O
all	O
levels	O
are	O
implemented	O
with	O
eDRAM	O
.	O
</s>
<s>
Other	O
types	O
of	O
caches	B-General_Concept
exist	O
(	O
that	O
are	O
not	O
counted	O
towards	O
the	O
"	O
cache	B-General_Concept
size	O
"	O
of	O
the	O
most	O
important	O
caches	B-General_Concept
mentioned	O
above	O
)	O
,	O
such	O
as	O
the	O
translation	B-Architecture
lookaside	I-Architecture
buffer	I-Architecture
(	O
TLB	B-Architecture
)	O
which	O
is	O
part	O
of	O
the	O
memory	B-General_Concept
management	I-General_Concept
unit	I-General_Concept
(	O
MMU	O
)	O
which	O
most	O
CPUs	O
have	O
.	O
</s>
<s>
When	O
trying	O
to	O
read	O
from	O
or	O
write	O
to	O
a	O
location	O
in	O
the	O
main	O
memory	O
,	O
the	O
processor	O
checks	O
whether	O
the	O
data	B-General_Concept
from	O
that	O
location	O
is	O
already	O
in	O
the	O
cache	B-General_Concept
.	O
</s>
<s>
If	O
so	O
,	O
the	O
processor	O
will	O
read	O
from	O
or	O
write	O
to	O
the	O
cache	B-General_Concept
instead	O
of	O
the	O
much	O
slower	O
main	O
memory	O
.	O
</s>
<s>
Many	O
modern	O
desktop	B-Device
,	O
server	B-Application
,	O
and	O
industrial	O
CPUs	O
have	O
at	O
least	O
three	O
independent	O
caches	B-General_Concept
:	O
</s>
<s>
Data	B-General_Concept
cache	B-General_Concept
Used	O
to	O
speed	O
up	O
data	B-General_Concept
fetch	O
and	O
store	O
;	O
the	O
data	B-General_Concept
cache	B-General_Concept
is	O
usually	O
organized	O
as	O
a	O
hierarchy	O
of	O
more	O
cache	B-General_Concept
levels	O
(	O
L1	O
,	O
L2	O
,	O
etc	O
.	O
</s>
<s>
;	O
see	O
also	O
multi-level	O
caches	B-General_Concept
below	O
)	O
.	O
</s>
<s>
Translation	B-Architecture
lookaside	I-Architecture
buffer	I-Architecture
(	O
TLB	B-Architecture
)	O
Used	O
to	O
speed	O
up	O
virtual-to-physical	B-Architecture
address	O
translation	O
for	O
both	O
executable	O
instructions	O
and	O
data	B-General_Concept
.	O
</s>
<s>
A	O
single	O
TLB	B-Architecture
can	O
be	O
provided	O
for	O
access	O
to	O
both	O
instructions	O
and	O
data	B-General_Concept
,	O
or	O
a	O
separate	O
Instruction	O
TLB	B-Architecture
(	O
ITLB	B-Architecture
)	O
and	O
data	B-General_Concept
TLB	B-Architecture
(	O
DTLB	B-Architecture
)	O
can	O
be	O
provided	O
.	O
</s>
<s>
However	O
,	O
the	O
TLB	B-Architecture
cache	B-General_Concept
is	O
part	O
of	O
the	O
memory	B-General_Concept
management	I-General_Concept
unit	I-General_Concept
(	O
MMU	O
)	O
and	O
not	O
directly	O
related	O
to	O
the	O
CPU	O
caches	B-General_Concept
.	O
</s>
<s>
Early	O
examples	O
of	O
CPU	O
caches	B-General_Concept
include	O
the	O
Atlas	B-Device
2	I-Device
and	O
the	O
IBM	B-Device
System/360	I-Device
Model	I-Device
85	I-Device
in	O
the	O
1960s	O
.	O
</s>
<s>
The	O
first	O
CPUs	O
that	O
used	O
a	O
cache	B-General_Concept
had	O
only	O
one	O
level	O
of	O
cache	B-General_Concept
;	O
unlike	O
later	O
level	O
1	O
cache	B-General_Concept
,	O
it	O
was	O
not	O
split	O
into	O
L1d	O
(	O
for	O
data	B-General_Concept
)	O
and	O
L1i	O
(	O
for	O
instructions	O
)	O
.	O
</s>
<s>
Split	O
L1	O
cache	B-General_Concept
started	O
in	O
1976	O
with	O
the	O
IBM	B-Device
801	I-Device
CPU	O
,	O
became	O
mainstream	O
in	O
the	O
late	O
1980s	O
,	O
and	O
in	O
1997	O
entered	O
the	O
embedded	O
CPU	O
market	O
with	O
the	O
ARMv5TE	O
.	O
</s>
<s>
In	O
2015	O
,	O
even	O
sub-dollar	O
SoCs	O
split	O
the	O
L1	O
cache	B-General_Concept
.	O
</s>
<s>
They	O
also	O
have	O
L2	O
caches	B-General_Concept
and	O
,	O
for	O
larger	O
processors	O
,	O
L3	O
caches	B-General_Concept
as	O
well	O
.	O
</s>
<s>
The	O
L2	O
cache	B-General_Concept
is	O
usually	O
not	O
split	O
,	O
and	O
acts	O
as	O
a	O
common	O
repository	O
for	O
the	O
already	O
split	O
L1	O
cache	B-General_Concept
.	O
</s>
<s>
Every	O
core	O
of	O
a	O
multi-core	B-Architecture
processor	I-Architecture
has	O
a	O
dedicated	O
L1	O
cache	B-General_Concept
and	O
is	O
usually	O
not	O
shared	O
between	O
the	O
cores	O
.	O
</s>
<s>
The	O
L2	O
cache	B-General_Concept
,	O
and	O
higher-level	O
caches	B-General_Concept
,	O
may	O
be	O
shared	O
between	O
the	O
cores	O
.	O
</s>
<s>
L4	O
cache	B-General_Concept
is	O
currently	O
uncommon	O
,	O
and	O
is	O
generally	O
dynamic	O
random-access	B-Architecture
memory	I-Architecture
(	O
DRAM	O
)	O
on	O
a	O
separate	O
die	O
or	O
chip	O
,	O
rather	O
than	O
static	B-Architecture
random-access	I-Architecture
memory	I-Architecture
(	O
SRAM	B-Architecture
)	O
.	O
</s>
<s>
An	O
exception	O
to	O
this	O
is	O
when	O
eDRAM	O
is	O
used	O
for	O
all	O
levels	O
of	O
cache	B-General_Concept
,	O
down	O
to	O
L1	O
.	O
</s>
<s>
Historically	O
L1	O
was	O
also	O
on	O
a	O
separate	O
die	O
,	O
however	O
bigger	O
die	O
sizes	O
have	O
allowed	O
integration	O
of	O
it	O
as	O
well	O
as	O
other	O
cache	B-General_Concept
levels	O
,	O
with	O
the	O
possible	O
exception	O
of	O
the	O
last	O
level	O
.	O
</s>
<s>
Each	O
extra	O
level	O
of	O
cache	B-General_Concept
tends	O
to	O
be	O
bigger	O
and	O
optimized	O
differently	O
.	O
</s>
<s>
Caches	B-General_Concept
(	O
like	O
for	O
RAM	B-Architecture
historically	O
)	O
have	O
generally	O
been	O
sized	O
in	O
powers	O
of	O
:	O
2	O
,	O
4	B-General_Concept
,	O
8	O
,	O
16	O
etc	O
.	O
</s>
<s>
for	O
larger	O
non-L1	O
)	O
,	O
very	O
early	O
on	O
the	O
pattern	O
broke	O
down	O
,	O
to	O
allow	O
for	O
larger	O
caches	B-General_Concept
without	O
being	O
forced	O
into	O
the	O
doubling-in-size	O
paradigm	O
,	O
with	O
e.g.	O
</s>
<s>
Intel	O
Core	O
2	O
Duo	O
with	O
3MiB	O
L2	O
cache	B-General_Concept
in	O
April	O
2008	O
.	O
</s>
<s>
This	O
happened	O
much	O
later	O
for	O
L1	O
caches	B-General_Concept
,	O
as	O
their	O
size	O
is	O
generally	O
still	O
a	O
small	O
number	O
of	O
KiB	O
.	O
</s>
<s>
The	O
IBM	B-Device
zEC12	I-Device
from	O
2012	O
is	O
an	O
exception	O
however	O
,	O
to	O
gain	O
unusually	O
large	O
96KiB	O
L1	O
data	B-General_Concept
cache	B-General_Concept
for	O
its	O
time	O
,	O
and	O
e.g.	O
</s>
<s>
the	O
IBM	B-Device
z13	I-Device
having	O
a	O
96KiB	O
L1	O
instruction	O
cache	B-General_Concept
(	O
and	O
128KiB	O
L1	O
data	B-General_Concept
cache	B-General_Concept
)	O
,	O
and	O
Intel	O
Ice	O
Lake-based	O
processors	O
from	O
2018	O
,	O
having	O
48KiB	O
L1	O
data	B-General_Concept
cache	B-General_Concept
and	O
48KiB	O
L1	O
instruction	O
cache	B-General_Concept
.	O
</s>
<s>
In	O
2020	O
,	O
some	O
Intel	B-Device
Atom	I-Device
CPUs	I-Device
(	O
with	O
up	O
to	O
24	O
cores	O
)	O
have	O
(	O
multiple	O
of	O
)	O
4.5MiB	O
and	O
15MiB	O
cache	B-General_Concept
sizes	O
.	O
</s>
<s>
Data	B-General_Concept
is	O
transferred	O
between	O
memory	O
and	O
cache	B-General_Concept
in	O
blocks	O
of	O
fixed	O
size	O
,	O
called	O
cache	B-General_Concept
lines	I-General_Concept
or	O
cache	B-General_Concept
blocks	O
.	O
</s>
<s>
When	O
a	O
cache	B-General_Concept
line	I-General_Concept
is	O
copied	O
from	O
memory	O
into	O
the	O
cache	B-General_Concept
,	O
a	O
cache	B-General_Concept
entry	O
is	O
created	O
.	O
</s>
<s>
The	O
cache	B-General_Concept
entry	O
will	O
include	O
the	O
copied	O
data	B-General_Concept
as	O
well	O
as	O
the	O
requested	O
memory	B-General_Concept
location	I-General_Concept
(	O
called	O
a	O
tag	O
)	O
.	O
</s>
<s>
When	O
the	O
processor	O
needs	O
to	O
read	O
or	O
write	O
a	O
location	O
in	O
memory	O
,	O
it	O
first	O
checks	O
for	O
a	O
corresponding	O
entry	O
in	O
the	O
cache	B-General_Concept
.	O
</s>
<s>
The	O
cache	B-General_Concept
checks	O
for	O
the	O
contents	O
of	O
the	O
requested	O
memory	B-General_Concept
location	I-General_Concept
in	O
any	O
cache	B-General_Concept
lines	I-General_Concept
that	O
might	O
contain	O
that	O
address	O
.	O
</s>
<s>
If	O
the	O
processor	O
finds	O
that	O
the	O
memory	B-General_Concept
location	I-General_Concept
is	O
in	O
the	O
cache	B-General_Concept
,	O
a	O
cache	B-General_Concept
hit	O
has	O
occurred	O
.	O
</s>
<s>
However	O
,	O
if	O
the	O
processor	O
does	O
not	O
find	O
the	O
memory	B-General_Concept
location	I-General_Concept
in	O
the	O
cache	B-General_Concept
,	O
a	O
cache	B-General_Concept
miss	O
has	O
occurred	O
.	O
</s>
<s>
In	O
the	O
case	O
of	O
a	O
cache	B-General_Concept
hit	O
,	O
the	O
processor	O
immediately	O
reads	O
or	O
writes	O
the	O
data	B-General_Concept
in	O
the	O
cache	B-General_Concept
line	I-General_Concept
.	O
</s>
<s>
For	O
a	O
cache	B-General_Concept
miss	O
,	O
the	O
cache	B-General_Concept
allocates	O
a	O
new	O
entry	O
and	O
copies	O
data	B-General_Concept
from	O
main	O
memory	O
,	O
then	O
the	O
request	O
is	O
fulfilled	O
from	O
the	O
contents	O
of	O
the	O
cache	B-General_Concept
.	O
</s>
<s>
To	O
make	O
room	O
for	O
the	O
new	O
entry	O
on	O
a	O
cache	B-General_Concept
miss	O
,	O
the	O
cache	B-General_Concept
may	O
have	O
to	O
evict	O
one	O
of	O
the	O
existing	O
entries	O
.	O
</s>
<s>
The	O
heuristic	B-Algorithm
it	O
uses	O
to	O
choose	O
the	O
entry	O
to	O
evict	O
is	O
called	O
the	O
replacement	O
policy	O
.	O
</s>
<s>
The	O
fundamental	O
problem	O
with	O
any	O
replacement	O
policy	O
is	O
that	O
it	O
must	O
predict	O
which	O
existing	O
cache	B-General_Concept
entry	O
is	O
least	O
likely	O
to	O
be	O
used	O
in	O
the	O
future	O
.	O
</s>
<s>
One	O
popular	O
replacement	O
policy	O
,	O
least-recently	O
used	O
(	O
LRU	B-General_Concept
)	O
,	O
replaces	O
the	O
least	O
recently	O
accessed	O
entry	O
.	O
</s>
<s>
Marking	O
some	O
memory	O
ranges	O
as	O
non-cacheable	O
can	O
improve	O
performance	O
,	O
by	O
avoiding	O
caching	B-General_Concept
of	O
memory	O
regions	O
that	O
are	O
rarely	O
re-accessed	O
.	O
</s>
<s>
This	O
avoids	O
the	O
overhead	O
of	O
loading	O
something	O
into	O
the	O
cache	B-General_Concept
without	O
having	O
any	O
reuse	O
.	O
</s>
<s>
Cache	B-General_Concept
entries	O
may	O
also	O
be	O
disabled	O
or	O
locked	O
depending	O
on	O
the	O
context	O
.	O
</s>
<s>
If	O
data	B-General_Concept
is	O
written	O
to	O
the	O
cache	B-General_Concept
,	O
at	O
some	O
point	O
it	O
must	O
also	O
be	O
written	O
to	O
main	O
memory	O
;	O
the	O
timing	O
of	O
this	O
write	O
is	O
known	O
as	O
the	O
write	O
policy	O
.	O
</s>
<s>
In	O
a	O
write-through	O
cache	B-General_Concept
,	O
every	O
write	O
to	O
the	O
cache	B-General_Concept
causes	O
a	O
write	O
to	O
main	O
memory	O
.	O
</s>
<s>
Alternatively	O
,	O
in	O
a	O
write-back	O
or	O
copy-back	O
cache	B-General_Concept
,	O
writes	O
are	O
not	O
immediately	O
mirrored	O
to	O
the	O
main	O
memory	O
,	O
and	O
the	O
cache	B-General_Concept
instead	O
tracks	O
which	O
locations	O
have	O
been	O
written	O
over	O
,	O
marking	O
them	O
as	O
dirty	B-Operating_System
.	O
</s>
<s>
The	O
data	B-General_Concept
in	O
these	O
locations	O
is	O
written	O
back	O
to	O
the	O
main	O
memory	O
only	O
when	O
that	O
data	B-General_Concept
is	O
evicted	O
from	O
the	O
cache	B-General_Concept
.	O
</s>
<s>
For	O
this	O
reason	O
,	O
a	O
read	O
miss	O
in	O
a	O
write-back	O
cache	B-General_Concept
may	O
sometimes	O
require	O
two	O
memory	O
accesses	O
to	O
service	O
:	O
one	O
to	O
first	O
write	O
the	O
dirty	B-Operating_System
location	O
to	O
main	O
memory	O
,	O
and	O
then	O
another	O
to	O
read	O
the	O
new	O
location	O
from	O
memory	O
.	O
</s>
<s>
Also	O
,	O
a	O
write	O
to	O
a	O
main	O
memory	B-General_Concept
location	I-General_Concept
that	O
is	O
not	O
yet	O
mapped	O
in	O
a	O
write-back	O
cache	B-General_Concept
may	O
evict	O
an	O
already	O
dirty	B-Operating_System
location	O
,	O
thereby	O
freeing	O
that	O
cache	B-General_Concept
space	O
for	O
the	O
new	O
memory	B-General_Concept
location	I-General_Concept
.	O
</s>
<s>
The	O
cache	B-General_Concept
may	O
be	O
write-through	O
,	O
but	O
the	O
writes	O
may	O
be	O
held	O
in	O
a	O
store	O
data	B-General_Concept
queue	O
temporarily	O
,	O
usually	O
so	O
multiple	O
stores	O
can	O
be	O
processed	O
together	O
(	O
which	O
can	O
reduce	O
bus	O
turnarounds	O
and	O
improve	O
bus	O
utilization	O
)	O
.	O
</s>
<s>
Cached	O
data	B-General_Concept
from	O
the	O
main	O
memory	O
may	O
be	O
changed	O
by	O
other	O
entities	O
(	O
e.g.	O
,	O
peripherals	O
using	O
direct	B-General_Concept
memory	I-General_Concept
access	I-General_Concept
(	O
DMA	O
)	O
or	O
another	O
core	O
in	O
a	O
multi-core	B-Architecture
processor	I-Architecture
)	O
,	O
in	O
which	O
case	O
the	O
copy	O
in	O
the	O
cache	B-General_Concept
may	O
become	O
out-of-date	O
or	O
stale	O
.	O
</s>
<s>
Alternatively	O
,	O
when	O
a	O
CPU	O
in	O
a	O
multiprocessor	B-Operating_System
system	O
updates	O
data	B-General_Concept
in	O
the	O
cache	B-General_Concept
,	O
copies	O
of	O
data	B-General_Concept
in	O
caches	B-General_Concept
associated	O
with	O
other	O
CPUs	O
become	O
stale	O
.	O
</s>
<s>
Communication	O
protocols	O
between	O
the	O
cache	B-General_Concept
managers	O
that	O
keep	O
the	O
data	B-General_Concept
consistent	O
are	O
known	O
as	O
cache	B-General_Concept
coherence	I-General_Concept
protocols	O
.	O
</s>
<s>
Cache	B-General_Concept
performance	I-General_Concept
measurement	I-General_Concept
has	O
become	O
important	O
in	O
recent	O
times	O
where	O
the	O
speed	O
gap	O
between	O
the	O
memory	O
performance	O
and	O
the	O
processor	O
performance	O
is	O
increasing	O
exponentially	O
.	O
</s>
<s>
The	O
cache	B-General_Concept
was	O
introduced	O
to	O
reduce	O
this	O
speed	O
gap	O
.	O
</s>
<s>
Thus	O
knowing	O
how	O
well	O
the	O
cache	B-General_Concept
is	O
able	O
to	O
bridge	O
the	O
gap	O
in	O
the	O
speed	O
of	O
processor	O
and	O
memory	O
becomes	O
important	O
,	O
especially	O
in	O
high-performance	O
systems	O
.	O
</s>
<s>
The	O
cache	B-General_Concept
hit	O
rate	O
and	O
the	O
cache	B-General_Concept
miss	O
rate	O
play	O
an	O
important	O
role	O
in	O
determining	O
this	O
performance	O
.	O
</s>
<s>
To	O
improve	O
the	O
cache	B-General_Concept
performance	O
,	O
reducing	O
the	O
miss	O
rate	O
becomes	O
one	O
of	O
the	O
necessary	O
steps	O
among	O
other	O
steps	O
.	O
</s>
<s>
Decreasing	O
the	O
access	O
time	O
to	O
the	O
cache	B-General_Concept
also	O
gives	O
a	O
boost	O
to	O
its	O
performance	O
.	O
</s>
<s>
The	O
time	O
taken	O
to	O
fetch	O
one	O
cache	B-General_Concept
line	I-General_Concept
from	O
memory	O
(	O
read	O
latency	O
due	O
to	O
a	O
cache	B-General_Concept
miss	O
)	O
matters	O
because	O
the	O
CPU	O
will	O
run	O
out	O
of	O
things	O
to	O
do	O
while	O
waiting	O
for	O
the	O
cache	B-General_Concept
line	I-General_Concept
.	O
</s>
<s>
As	O
CPUs	O
become	O
faster	O
compared	O
to	O
main	O
memory	O
,	O
stalls	O
due	O
to	O
cache	B-General_Concept
misses	O
displace	O
more	O
potential	O
computation	O
;	O
modern	O
CPUs	O
can	O
execute	O
hundreds	O
of	O
instructions	O
in	O
the	O
time	O
taken	O
to	O
fetch	O
a	O
single	O
cache	B-General_Concept
line	I-General_Concept
from	O
main	O
memory	O
.	O
</s>
<s>
Various	O
techniques	O
have	O
been	O
employed	O
to	O
keep	O
the	O
CPU	O
busy	O
during	O
this	O
time	O
,	O
including	O
out-of-order	B-General_Concept
execution	I-General_Concept
in	O
which	O
the	O
CPU	O
attempts	O
to	O
execute	O
independent	O
instructions	O
after	O
the	O
instruction	O
that	O
is	O
waiting	O
for	O
the	O
cache	B-General_Concept
miss	O
data	B-General_Concept
.	O
</s>
<s>
Another	O
technology	O
,	O
used	O
by	O
many	O
processors	O
,	O
is	O
simultaneous	B-Operating_System
multithreading	I-Operating_System
(	O
SMT	O
)	O
,	O
which	O
allows	O
an	O
alternate	O
thread	O
to	O
use	O
the	O
CPU	B-Architecture
core	I-Architecture
while	O
the	O
first	O
thread	O
waits	O
for	O
required	O
CPU	O
resources	O
to	O
become	O
available	O
.	O
</s>
<s>
The	O
placement	B-General_Concept
policy	I-General_Concept
decides	O
where	O
in	O
the	O
cache	B-General_Concept
a	O
copy	O
of	O
a	O
particular	O
entry	O
of	O
main	O
memory	O
will	O
go	O
.	O
</s>
<s>
If	O
the	O
placement	B-General_Concept
policy	I-General_Concept
is	O
free	O
to	O
choose	O
any	O
entry	O
in	O
the	O
cache	B-General_Concept
to	O
hold	O
the	O
copy	O
,	O
the	O
cache	B-General_Concept
is	O
called	O
fully	O
associative	O
.	O
</s>
<s>
At	O
the	O
other	O
extreme	O
,	O
if	O
each	O
entry	O
in	O
the	O
main	O
memory	O
can	O
go	O
in	O
just	O
one	O
place	O
in	O
the	O
cache	B-General_Concept
,	O
the	O
cache	B-General_Concept
is	O
direct-mapped	O
.	O
</s>
<s>
Many	O
caches	B-General_Concept
implement	O
a	O
compromise	O
in	O
which	O
each	O
entry	O
in	O
the	O
main	O
memory	O
can	O
go	O
to	O
any	O
one	O
of	O
N	O
places	O
in	O
the	O
cache	B-General_Concept
,	O
and	O
are	O
described	O
as	O
N-way	O
set	O
associative	O
.	O
</s>
<s>
For	O
example	O
,	O
the	O
level-1	O
data	B-General_Concept
cache	B-General_Concept
in	O
an	O
AMD	B-Architecture
Athlon	I-Architecture
is	O
two-way	O
set	O
associative	O
,	O
which	O
means	O
that	O
any	O
particular	O
location	O
in	O
main	O
memory	O
can	O
be	O
cached	O
in	O
either	O
of	O
two	O
locations	O
in	O
the	O
level-1	O
data	B-General_Concept
cache	B-General_Concept
.	O
</s>
<s>
If	O
there	O
are	O
ten	O
places	O
to	O
which	O
the	O
placement	B-General_Concept
policy	I-General_Concept
could	O
have	O
mapped	O
a	O
memory	B-General_Concept
location	I-General_Concept
,	O
then	O
to	O
check	O
if	O
that	O
location	O
is	O
in	O
the	O
cache	B-General_Concept
,	O
ten	O
cache	B-General_Concept
entries	O
must	O
be	O
searched	O
.	O
</s>
<s>
On	O
the	O
other	O
hand	O
,	O
caches	B-General_Concept
with	O
more	O
associativity	O
suffer	O
fewer	O
misses	O
(	O
see	O
conflict	O
misses	O
)	O
,	O
so	O
that	O
the	O
CPU	O
wastes	O
less	O
time	O
reading	O
from	O
the	O
slow	O
main	O
memory	O
.	O
</s>
<s>
The	O
general	O
guideline	O
is	O
that	O
doubling	O
the	O
associativity	O
,	O
from	O
direct	O
mapped	O
to	O
two-way	O
,	O
or	O
from	O
two-way	O
to	O
four-way	O
,	O
has	O
about	O
the	O
same	O
effect	O
on	O
raising	O
the	O
hit	O
rate	O
as	O
doubling	O
the	O
cache	B-General_Concept
size	O
.	O
</s>
<s>
Some	O
CPUs	O
can	O
dynamically	O
reduce	O
the	O
associativity	O
of	O
their	O
caches	B-General_Concept
in	O
low-power	O
states	O
,	O
which	O
acts	O
as	O
a	O
power-saving	O
measure	O
.	O
</s>
<s>
In	O
this	O
cache	B-General_Concept
organization	O
,	O
each	O
location	O
in	O
the	O
main	O
memory	O
can	O
go	O
in	O
only	O
one	O
entry	O
in	O
the	O
cache	B-General_Concept
.	O
</s>
<s>
Therefore	O
,	O
a	O
direct-mapped	O
cache	B-General_Concept
can	O
also	O
be	O
called	O
a	O
"	O
one-way	O
set	O
associative	O
"	O
cache	B-General_Concept
.	O
</s>
<s>
It	O
does	O
not	O
have	O
a	O
placement	B-General_Concept
policy	I-General_Concept
as	O
such	O
,	O
since	O
there	O
is	O
no	O
choice	O
of	O
which	O
cache	B-General_Concept
entry	O
's	O
contents	O
to	O
evict	O
.	O
</s>
<s>
Although	O
simpler	O
,	O
a	O
direct-mapped	O
cache	B-General_Concept
needs	O
to	O
be	O
much	O
larger	O
than	O
an	O
associative	O
one	O
to	O
give	O
comparable	O
performance	O
,	O
and	O
it	O
is	O
more	O
unpredictable	O
.	O
</s>
<s>
Let	O
be	O
block	O
number	O
in	O
cache	B-General_Concept
,	O
be	O
block	O
number	O
of	O
memory	O
,	O
and	O
be	O
number	O
of	O
blocks	O
in	O
cache	B-General_Concept
,	O
then	O
mapping	O
is	O
done	O
with	O
the	O
help	O
of	O
the	O
equation	O
.	O
</s>
<s>
If	O
each	O
location	O
in	O
the	O
main	O
memory	O
can	O
be	O
cached	O
in	O
either	O
of	O
two	O
locations	O
in	O
the	O
cache	B-General_Concept
,	O
one	O
logical	O
question	O
is	O
:	O
which	O
one	O
of	O
the	O
two	O
?	O
</s>
<s>
The	O
simplest	O
and	O
most	O
commonly	O
used	O
scheme	O
,	O
shown	O
in	O
the	O
right-hand	O
diagram	O
above	O
,	O
is	O
to	O
use	O
the	O
least	O
significant	O
bits	O
of	O
the	O
memory	B-General_Concept
location	I-General_Concept
's	O
index	O
as	O
the	O
index	O
for	O
the	O
cache	B-General_Concept
memory	I-General_Concept
,	O
and	O
to	O
have	O
two	O
entries	O
for	O
each	O
index	O
.	O
</s>
<s>
One	O
benefit	O
of	O
this	O
scheme	O
is	O
that	O
the	O
tags	O
stored	O
in	O
the	O
cache	B-General_Concept
do	O
not	O
have	O
to	O
include	O
that	O
part	O
of	O
the	O
main	O
memory	B-General_Concept
address	I-General_Concept
which	O
is	O
implied	O
by	O
the	O
cache	B-General_Concept
memory	I-General_Concept
's	O
index	O
.	O
</s>
<s>
Since	O
the	O
cache	B-General_Concept
tags	O
have	O
fewer	O
bits	O
,	O
they	O
require	O
fewer	O
transistors	O
,	O
take	O
less	O
space	O
on	O
the	O
processor	O
circuit	O
board	O
or	O
on	O
the	O
microprocessor	O
chip	O
,	O
and	O
can	O
be	O
read	O
and	O
compared	O
faster	O
.	O
</s>
<s>
Also	O
LRU	B-General_Concept
is	O
especially	O
simple	O
since	O
only	O
one	O
bit	O
needs	O
to	O
be	O
stored	O
for	O
each	O
pair	O
.	O
</s>
<s>
One	O
of	O
the	O
advantages	O
of	O
a	O
direct-mapped	O
cache	B-General_Concept
is	O
that	O
it	O
allows	O
simple	O
and	O
fast	O
speculation	B-General_Concept
.	O
</s>
<s>
Once	O
the	O
address	O
has	O
been	O
computed	O
,	O
the	O
one	O
cache	B-General_Concept
index	O
which	O
might	O
have	O
a	O
copy	O
of	O
that	O
location	O
in	O
memory	O
is	O
known	O
.	O
</s>
<s>
That	O
cache	B-General_Concept
entry	O
can	O
be	O
read	O
,	O
and	O
the	O
processor	O
can	O
continue	O
to	O
work	O
with	O
that	O
data	B-General_Concept
before	O
it	O
finishes	O
checking	O
that	O
the	O
tag	O
actually	O
matches	O
the	O
requested	O
address	O
.	O
</s>
<s>
The	O
idea	O
of	O
having	O
the	O
processor	O
use	O
the	O
cached	O
data	B-General_Concept
before	O
the	O
tag	O
match	O
completes	O
can	O
be	O
applied	O
to	O
associative	B-General_Concept
caches	I-General_Concept
as	O
well	O
.	O
</s>
<s>
A	O
subset	O
of	O
the	O
tag	O
,	O
called	O
a	O
hint	O
,	O
can	O
be	O
used	O
to	O
pick	O
just	O
one	O
of	O
the	O
possible	O
cache	B-General_Concept
entries	O
mapping	O
to	O
the	O
requested	O
address	O
.	O
</s>
<s>
Other	O
schemes	O
have	O
been	O
suggested	O
,	O
such	O
as	O
the	O
skewed	O
cache	B-General_Concept
,	O
where	O
the	O
index	O
for	O
way	O
0	O
is	O
direct	O
,	O
as	O
above	O
,	O
but	O
the	O
index	O
for	O
way	O
1	O
is	O
formed	O
with	O
a	O
hash	B-Error_Name
function	I-Error_Name
.	O
</s>
<s>
A	O
good	O
hash	B-Error_Name
function	I-Error_Name
has	O
the	O
property	O
that	O
addresses	O
which	O
conflict	O
with	O
the	O
direct	O
mapping	O
tend	O
not	O
to	O
conflict	O
when	O
mapped	O
with	O
the	O
hash	B-Error_Name
function	I-Error_Name
,	O
and	O
so	O
it	O
is	O
less	O
likely	O
that	O
a	O
program	O
will	O
suffer	O
from	O
an	O
unexpectedly	O
large	O
number	O
of	O
conflict	O
misses	O
due	O
to	O
a	O
pathological	O
access	O
pattern	O
.	O
</s>
<s>
The	O
downside	O
is	O
extra	O
latency	O
from	O
computing	O
the	O
hash	B-Error_Name
function	I-Error_Name
.	O
</s>
<s>
Additionally	O
,	O
when	O
it	O
comes	O
time	O
to	O
load	O
a	O
new	O
line	O
and	O
evict	O
an	O
old	O
line	O
,	O
it	O
may	O
be	O
difficult	O
to	O
determine	O
which	O
existing	O
line	O
was	O
least	O
recently	O
used	O
,	O
because	O
the	O
new	O
line	O
conflicts	O
with	O
data	B-General_Concept
at	O
different	O
indexes	O
in	O
each	O
way	O
;	O
LRU	B-General_Concept
tracking	O
for	O
non-skewed	O
caches	B-General_Concept
is	O
usually	O
done	O
on	O
a	O
per-set	O
basis	O
.	O
</s>
<s>
A	O
true	O
set-associative	O
cache	O
tests	O
all	O
the	O
possible	O
ways	O
simultaneously	O
,	O
using	O
something	O
like	O
a	O
content-addressable	B-Data_Structure
memory	I-Data_Structure
.	O
</s>
<s>
A	O
hash-rehash	O
cache	B-General_Concept
and	O
a	O
column-associative	O
cache	B-General_Concept
are	O
examples	O
of	O
a	O
pseudo-associative	O
cache	B-General_Concept
.	O
</s>
<s>
In	O
the	O
common	O
case	O
of	O
finding	O
a	O
hit	O
in	O
the	O
first	O
way	O
tested	O
,	O
a	O
pseudo-associative	O
cache	B-General_Concept
is	O
as	O
fast	O
as	O
a	O
direct-mapped	O
cache	B-General_Concept
,	O
but	O
it	O
has	O
a	O
much	O
lower	O
conflict	O
miss	O
rate	O
than	O
a	O
direct-mapped	O
cache	B-General_Concept
,	O
closer	O
to	O
the	O
miss	O
rate	O
of	O
a	O
fully	O
associative	B-General_Concept
cache	I-General_Concept
.	O
</s>
<s>
Comparing	O
with	O
a	O
direct-mapped	O
cache	B-General_Concept
,	O
a	O
set	O
associative	B-General_Concept
cache	I-General_Concept
has	O
a	O
reduced	O
number	O
of	O
bits	O
for	O
its	O
cache	B-General_Concept
set	O
index	O
that	O
maps	O
to	O
a	O
cache	B-General_Concept
set	O
,	O
where	O
multiple	O
ways	O
or	O
blocks	O
stays	O
,	O
such	O
as	O
2	O
blocks	O
for	O
a	O
2-way	O
set	O
associative	B-General_Concept
cache	I-General_Concept
and	O
4	B-General_Concept
blocks	O
for	O
a	O
4-way	O
set	O
associative	B-General_Concept
cache	I-General_Concept
.	O
</s>
<s>
Comparing	O
with	O
a	O
direct	O
mapped	O
cache	B-General_Concept
,	O
the	O
unused	O
cache	B-General_Concept
index	O
bits	O
become	O
a	O
part	O
of	O
the	O
tag	O
bits	O
.	O
</s>
<s>
For	O
example	O
,	O
a	O
2-way	O
set	O
associative	B-General_Concept
cache	I-General_Concept
contributes	O
1	O
bit	O
to	O
the	O
tag	O
and	O
a	O
4-way	O
set	O
associative	B-General_Concept
cache	I-General_Concept
contributes	O
2	O
bits	O
to	O
the	O
tag	O
.	O
</s>
<s>
The	O
basic	O
idea	O
of	O
the	O
multicolumn	O
cache	B-General_Concept
is	O
to	O
use	O
the	O
set	O
index	O
to	O
map	O
to	O
a	O
cache	B-General_Concept
set	O
as	O
a	O
conventional	O
set	O
associative	B-General_Concept
cache	I-General_Concept
does	O
,	O
and	O
to	O
use	O
the	O
added	O
tag	O
bits	O
to	O
index	O
a	O
way	O
in	O
the	O
set	O
.	O
</s>
<s>
For	O
example	O
,	O
in	O
a	O
4-way	O
set	O
associative	B-General_Concept
cache	I-General_Concept
,	O
the	O
two	O
bits	O
are	O
used	O
to	O
index	O
way	O
00	O
,	O
way	O
01	O
,	O
way	O
10	O
,	O
and	O
way	O
11	O
,	O
respectively	O
.	O
</s>
<s>
This	O
double	O
cache	B-General_Concept
indexing	O
is	O
called	O
a	O
“	O
major	O
location	O
mapping	O
”	O
,	O
and	O
its	O
latency	O
is	O
equivalent	O
to	O
a	O
direct-mapped	O
access	O
.	O
</s>
<s>
Extensive	O
experiments	O
in	O
multicolumn	O
cache	B-General_Concept
design	O
shows	O
that	O
the	O
hit	O
ratio	O
to	O
major	O
locations	O
is	O
as	O
high	O
as	O
90%	O
.	O
</s>
<s>
If	O
cache	B-General_Concept
mapping	O
conflicts	O
with	O
a	O
cache	B-General_Concept
block	O
in	O
the	O
major	O
location	O
,	O
the	O
existing	O
cache	B-General_Concept
block	O
will	O
be	O
moved	O
to	O
another	O
cache	B-General_Concept
way	O
in	O
the	O
same	O
set	O
,	O
which	O
is	O
called	O
“	O
selected	O
location	O
”	O
.	O
</s>
<s>
Because	O
the	O
newly	O
indexed	O
cache	B-General_Concept
block	O
is	O
a	O
most	O
recently	O
used	O
(	O
MRU	O
)	O
block	O
,	O
it	O
is	O
placed	O
in	O
the	O
major	O
location	O
in	O
multicolumn	O
cache	B-General_Concept
with	O
a	O
consideration	O
of	O
temporal	B-General_Concept
locality	I-General_Concept
.	O
</s>
<s>
Since	O
multicolumn	O
cache	B-General_Concept
is	O
designed	O
for	O
a	O
cache	B-General_Concept
with	O
a	O
high	O
associativity	O
,	O
the	O
number	O
of	O
ways	O
in	O
each	O
set	O
is	O
high	O
;	O
thus	O
,	O
it	O
is	O
easy	O
find	O
a	O
selected	O
location	O
in	O
the	O
set	O
.	O
</s>
<s>
A	O
selected	O
location	O
index	O
by	O
an	O
additional	O
hardware	O
is	O
maintained	O
for	O
the	O
major	O
location	O
in	O
a	O
cache	B-General_Concept
block	O
.	O
</s>
<s>
Multicolumn	O
cache	B-General_Concept
remains	O
a	O
high	O
hit	O
ratio	O
due	O
to	O
its	O
high	O
associativity	O
,	O
and	O
has	O
a	O
comparable	O
low	O
latency	O
to	O
a	O
direct-mapped	O
cache	B-General_Concept
due	O
to	O
its	O
high	O
percentage	O
of	O
hits	O
in	O
major	O
locations	O
.	O
</s>
<s>
Cache	B-General_Concept
row	O
entries	O
usually	O
have	O
the	O
following	O
structure	O
:	O
</s>
<s>
The	O
data	B-General_Concept
block	O
(	O
cache	B-General_Concept
line	I-General_Concept
)	O
contains	O
the	O
actual	O
data	B-General_Concept
fetched	O
from	O
the	O
main	O
memory	O
.	O
</s>
<s>
The	O
tag	O
contains	O
(	O
part	O
of	O
)	O
the	O
address	O
of	O
the	O
actual	O
data	B-General_Concept
fetched	O
from	O
the	O
main	O
memory	O
.	O
</s>
<s>
The	O
"	O
size	O
"	O
of	O
the	O
cache	B-General_Concept
is	O
the	O
amount	O
of	O
main	O
memory	O
data	B-General_Concept
it	O
can	O
hold	O
.	O
</s>
<s>
This	O
size	O
can	O
be	O
calculated	O
as	O
the	O
number	O
of	O
bytes	O
stored	O
in	O
each	O
data	B-General_Concept
block	O
times	O
the	O
number	O
of	O
blocks	O
stored	O
in	O
the	O
cache	B-General_Concept
.	O
</s>
<s>
(	O
The	O
tag	O
,	O
flag	O
and	O
error	B-Error_Name
correction	I-Error_Name
code	I-Error_Name
bits	O
are	O
not	O
included	O
in	O
the	O
size	O
,	O
although	O
they	O
do	O
affect	O
the	O
physical	O
area	O
of	O
a	O
cache	B-General_Concept
.	O
)	O
</s>
<s>
An	O
effective	O
memory	B-General_Concept
address	I-General_Concept
which	O
goes	O
along	O
with	O
the	O
cache	B-General_Concept
line	I-General_Concept
(	O
memory	O
block	O
)	O
is	O
split	O
(	O
MSB	O
to	O
LSB	O
)	O
into	O
the	O
tag	O
,	O
the	O
index	O
and	O
the	O
block	O
offset	O
.	O
</s>
<s>
The	O
index	O
describes	O
which	O
cache	B-General_Concept
set	O
that	O
the	O
data	B-General_Concept
has	O
been	O
put	O
in	O
.	O
</s>
<s>
The	O
index	O
length	O
is	O
bits	O
for	O
cache	B-General_Concept
sets	O
.	O
</s>
<s>
The	O
block	O
offset	O
specifies	O
the	O
desired	O
data	B-General_Concept
within	O
the	O
stored	O
data	B-General_Concept
block	O
within	O
the	O
cache	B-General_Concept
row	O
.	O
</s>
<s>
Typically	O
the	O
effective	O
address	O
is	O
in	O
bytes	O
,	O
so	O
the	O
block	O
offset	O
length	O
is	O
bits	O
,	O
where	O
is	O
the	O
number	O
of	O
bytes	O
per	O
data	B-General_Concept
block	O
.	O
</s>
<s>
If	O
it	O
does	O
,	O
a	O
cache	B-General_Concept
hit	O
occurs	O
.	O
</s>
<s>
The	O
original	B-General_Concept
Pentium	I-General_Concept
4	B-General_Concept
processor	O
had	O
a	O
four-way	O
set	O
associative	O
L1	O
data	B-General_Concept
cache	B-General_Concept
of	O
8KiB	O
in	O
size	O
,	O
with	O
64-byte	O
cache	B-General_Concept
blocks	O
.	O
</s>
<s>
Hence	O
,	O
there	O
are	O
8KiB/64	O
=	O
128	O
cache	B-General_Concept
blocks	O
.	O
</s>
<s>
The	O
number	O
of	O
sets	O
is	O
equal	O
to	O
the	O
number	O
of	O
cache	B-General_Concept
blocks	O
divided	O
by	O
the	O
number	O
of	O
ways	O
of	O
associativity	O
,	O
what	O
leads	O
to	O
128/4	O
=	O
32	O
sets	O
,	O
and	O
hence	O
25	O
=	O
32	O
different	O
indices	O
.	O
</s>
<s>
The	O
original	O
Pentium4	B-General_Concept
processor	O
also	O
had	O
an	O
eight-way	O
set	O
associative	O
L2	O
integrated	O
cache	B-General_Concept
256KiB	O
in	O
size	O
,	O
with	O
128-byte	O
cache	B-General_Concept
blocks	O
.	O
</s>
<s>
An	O
instruction	O
cache	B-General_Concept
requires	O
only	O
one	O
flag	O
bit	O
per	O
cache	B-General_Concept
row	O
entry	O
:	O
a	O
valid	O
bit	O
.	O
</s>
<s>
The	O
valid	O
bit	O
indicates	O
whether	O
or	O
not	O
a	O
cache	B-General_Concept
block	O
has	O
been	O
loaded	O
with	O
valid	O
data	B-General_Concept
.	O
</s>
<s>
On	O
power-up	O
,	O
the	O
hardware	O
sets	O
all	O
the	O
valid	O
bits	O
in	O
all	O
the	O
caches	B-General_Concept
to	O
"	O
invalid	O
"	O
.	O
</s>
<s>
Some	O
systems	O
also	O
set	O
a	O
valid	O
bit	O
to	O
"	O
invalid	O
"	O
at	O
other	O
times	O
,	O
such	O
as	O
when	O
multi-master	O
bus	B-General_Concept
snooping	I-General_Concept
hardware	O
in	O
the	O
cache	B-General_Concept
of	O
one	O
processor	O
hears	O
an	O
address	O
broadcast	O
from	O
some	O
other	O
processor	O
,	O
and	O
realizes	O
that	O
certain	O
data	B-General_Concept
blocks	O
in	O
the	O
local	O
cache	B-General_Concept
are	O
now	O
stale	O
and	O
should	O
be	O
marked	O
invalid	O
.	O
</s>
<s>
A	O
data	B-General_Concept
cache	B-General_Concept
typically	O
requires	O
two	O
flag	O
bits	O
per	O
cache	B-General_Concept
line	I-General_Concept
a	O
valid	O
bit	O
and	O
a	O
dirty	B-Operating_System
bit	I-Operating_System
.	O
</s>
<s>
Having	O
a	O
dirty	B-Operating_System
bit	I-Operating_System
set	O
indicates	O
that	O
the	O
associated	O
cache	B-General_Concept
line	I-General_Concept
has	O
been	O
changed	O
since	O
it	O
was	O
read	O
from	O
main	O
memory	O
(	O
"	O
dirty	B-Operating_System
"	O
)	O
,	O
meaning	O
that	O
the	O
processor	O
has	O
written	O
data	B-General_Concept
to	O
that	O
line	O
and	O
the	O
new	O
value	O
has	O
not	O
propagated	O
all	O
the	O
way	O
to	O
main	O
memory	O
.	O
</s>
<s>
A	O
cache	B-General_Concept
miss	O
is	O
a	O
failed	O
attempt	O
to	O
read	O
or	O
write	O
a	O
piece	O
of	O
data	B-General_Concept
in	O
the	O
cache	B-General_Concept
,	O
which	O
results	O
in	O
a	O
main	O
memory	O
access	O
with	O
much	O
longer	O
latency	O
.	O
</s>
<s>
There	O
are	O
three	O
kinds	O
of	O
cache	B-General_Concept
misses	O
:	O
instruction	O
read	O
miss	O
,	O
data	B-General_Concept
read	O
miss	O
,	O
and	O
data	B-General_Concept
write	O
miss	O
.	O
</s>
<s>
Cache	B-General_Concept
read	O
misses	O
from	O
an	O
instruction	O
cache	B-General_Concept
generally	O
cause	O
the	O
largest	O
delay	O
,	O
because	O
the	O
processor	O
,	O
or	O
at	O
least	O
the	O
thread	B-Operating_System
of	I-Operating_System
execution	I-Operating_System
,	O
has	O
to	O
wait	O
(	O
stall	O
)	O
until	O
the	O
instruction	O
is	O
fetched	O
from	O
main	O
memory	O
.	O
</s>
<s>
Cache	B-General_Concept
read	O
misses	O
from	O
a	O
data	B-General_Concept
cache	B-General_Concept
usually	O
cause	O
a	O
smaller	O
delay	O
,	O
because	O
instructions	O
not	O
dependent	O
on	O
the	O
cache	B-General_Concept
read	O
can	O
be	O
issued	O
and	O
continue	O
execution	O
until	O
the	O
data	B-General_Concept
is	O
returned	O
from	O
main	O
memory	O
,	O
and	O
the	O
dependent	O
instructions	O
can	O
resume	O
execution	O
.	O
</s>
<s>
Cache	B-General_Concept
write	O
misses	O
to	O
a	O
data	B-General_Concept
cache	B-General_Concept
generally	O
cause	O
the	O
shortest	O
delay	O
,	O
because	O
the	O
write	O
can	O
be	O
queued	O
and	O
there	O
are	O
few	O
limitations	O
on	O
the	O
execution	O
of	O
subsequent	O
instructions	O
;	O
the	O
processor	O
can	O
continue	O
until	O
the	O
queue	O
is	O
full	O
.	O
</s>
<s>
For	O
a	O
detailed	O
introduction	O
to	O
the	O
types	O
of	O
misses	O
,	O
see	O
cache	B-General_Concept
performance	I-General_Concept
measurement	I-General_Concept
and	I-General_Concept
metric	I-General_Concept
.	O
</s>
<s>
Most	O
general	O
purpose	O
CPUs	O
implement	O
some	O
form	O
of	O
virtual	B-Architecture
memory	I-Architecture
.	O
</s>
<s>
To	O
summarize	O
,	O
either	O
each	O
program	O
running	O
on	O
the	O
machine	O
sees	O
its	O
own	O
simplified	O
address	B-General_Concept
space	I-General_Concept
,	O
which	O
contains	O
code	O
and	O
data	B-General_Concept
for	O
that	O
program	O
only	O
,	O
or	O
all	O
programs	O
run	O
in	O
a	O
common	O
virtual	O
address	B-General_Concept
space	I-General_Concept
.	O
</s>
<s>
A	O
program	O
executes	O
by	O
calculating	O
,	O
comparing	O
,	O
reading	O
and	O
writing	O
to	O
addresses	O
of	O
its	O
virtual	O
address	B-General_Concept
space	I-General_Concept
,	O
rather	O
than	O
addresses	O
of	O
physical	O
address	B-General_Concept
space	I-General_Concept
,	O
making	O
programs	O
simpler	O
and	O
thus	O
easier	O
to	O
write	O
.	O
</s>
<s>
Virtual	B-Architecture
memory	I-Architecture
requires	O
the	O
processor	O
to	O
translate	O
virtual	O
addresses	O
generated	O
by	O
the	O
program	O
into	O
physical	O
addresses	O
in	O
main	O
memory	O
.	O
</s>
<s>
The	O
portion	O
of	O
the	O
processor	O
that	O
does	O
this	O
translation	O
is	O
known	O
as	O
the	O
memory	B-General_Concept
management	I-General_Concept
unit	I-General_Concept
(	O
MMU	O
)	O
.	O
</s>
<s>
The	O
fast	O
path	O
through	O
the	O
MMU	O
can	O
perform	O
those	O
translations	O
stored	O
in	O
the	O
translation	B-Architecture
lookaside	I-Architecture
buffer	I-Architecture
(	O
TLB	B-Architecture
)	O
,	O
which	O
is	O
a	O
cache	B-General_Concept
of	O
mappings	O
from	O
the	O
operating	O
system	O
's	O
page	B-General_Concept
table	I-General_Concept
,	O
segment	O
table	O
,	O
or	O
both	O
.	O
</s>
<s>
To	O
deliver	O
on	O
that	O
guarantee	O
,	O
the	O
processor	O
must	O
ensure	O
that	O
only	O
one	O
copy	O
of	O
a	O
physical	O
address	O
resides	O
in	O
the	O
cache	B-General_Concept
at	O
any	O
given	O
time	O
.	O
</s>
<s>
Granularity	O
:	O
The	O
virtual	O
address	B-General_Concept
space	I-General_Concept
is	O
broken	O
up	O
into	O
pages	O
.	O
</s>
<s>
For	O
instance	O
,	O
a	O
4GiB	O
virtual	O
address	B-General_Concept
space	I-General_Concept
might	O
be	O
cut	O
up	O
into	O
1,048,576	O
pages	O
of	O
4KiB	O
size	O
,	O
each	O
of	O
which	O
can	O
be	O
independently	O
mapped	O
.	O
</s>
<s>
There	O
may	O
be	O
multiple	O
page	O
sizes	O
supported	O
;	O
see	O
virtual	B-Architecture
memory	I-Architecture
for	O
elaboration	O
.	O
</s>
<s>
One	O
early	O
virtual	B-Architecture
memory	I-Architecture
system	O
,	O
the	O
IBM	B-Device
M44/44X	I-Device
,	O
required	O
an	O
access	O
to	O
a	O
mapping	O
table	O
held	O
in	O
core	B-General_Concept
memory	I-General_Concept
before	O
every	O
programmed	O
access	O
to	O
main	O
memory	O
.	O
</s>
<s>
With	O
no	O
caches	B-General_Concept
,	O
and	O
with	O
the	O
mapping	O
table	O
memory	O
running	O
at	O
the	O
same	O
speed	O
as	O
main	O
memory	O
this	O
effectively	O
cut	O
the	O
speed	O
of	O
memory	O
access	O
in	O
half	O
.	O
</s>
<s>
Two	O
early	O
machines	O
that	O
used	O
a	O
page	B-General_Concept
table	I-General_Concept
in	O
main	O
memory	O
for	O
mapping	O
,	O
the	O
IBM	B-Device
System/360	I-Device
Model	I-Device
67	I-Device
and	O
the	O
GE	B-Device
645	I-Device
,	O
both	O
had	O
a	O
small	O
associative	O
memory	O
as	O
a	O
cache	B-General_Concept
for	O
accesses	O
to	O
the	O
in-memory	O
page	B-General_Concept
table	I-General_Concept
.	O
</s>
<s>
Both	O
machines	O
predated	O
the	O
first	O
machine	O
with	O
a	O
cache	B-General_Concept
for	O
main	O
memory	O
,	O
the	O
IBM	B-Device
System/360	I-Device
Model	I-Device
85	I-Device
,	O
so	O
the	O
first	O
hardware	O
cache	B-General_Concept
used	O
in	O
a	O
computer	O
system	O
was	O
not	O
a	O
data	B-General_Concept
or	O
instruction	O
cache	B-General_Concept
,	O
but	O
rather	O
a	O
TLB	B-Architecture
.	O
</s>
<s>
Caches	B-General_Concept
can	O
be	O
divided	O
into	O
four	O
types	O
,	O
based	O
on	O
whether	O
the	O
index	O
or	O
tag	O
correspond	O
to	O
physical	O
or	O
virtual	O
addresses	O
:	O
</s>
<s>
Physically	O
indexed	O
,	O
physically	O
tagged	O
(	O
PIPT	O
)	O
caches	B-General_Concept
use	O
the	O
physical	O
address	O
for	O
both	O
the	O
index	O
and	O
the	O
tag	O
.	O
</s>
<s>
While	O
this	O
is	O
simple	O
and	O
avoids	O
problems	O
with	O
aliasing	O
,	O
it	O
is	O
also	O
slow	O
,	O
as	O
the	O
physical	O
address	O
must	O
be	O
looked	O
up	O
(	O
which	O
could	O
involve	O
a	O
TLB	B-Architecture
miss	O
and	O
access	O
to	O
main	O
memory	O
)	O
before	O
that	O
address	O
can	O
be	O
looked	O
up	O
in	O
the	O
cache	B-General_Concept
.	O
</s>
<s>
Virtually	O
indexed	O
,	O
virtually	O
tagged	O
(	O
VIVT	O
)	O
caches	B-General_Concept
use	O
the	O
virtual	O
address	O
for	O
both	O
the	O
index	O
and	O
the	O
tag	O
.	O
</s>
<s>
This	O
caching	B-General_Concept
scheme	O
can	O
result	O
in	O
much	O
faster	O
lookups	O
,	O
since	O
the	O
MMU	O
does	O
not	O
need	O
to	O
be	O
consulted	O
first	O
to	O
determine	O
the	O
physical	O
address	O
for	O
a	O
given	O
virtual	O
address	O
.	O
</s>
<s>
Although	O
solutions	O
to	O
this	O
problem	O
exist	O
they	O
do	O
not	O
work	O
for	O
standard	O
coherence	B-General_Concept
protocols	I-General_Concept
.	O
</s>
<s>
It	O
is	O
not	O
possible	O
to	O
distinguish	O
these	O
mappings	O
merely	O
by	O
looking	O
at	O
the	O
virtual	O
index	O
itself	O
,	O
though	O
potential	O
solutions	O
include	O
:	O
flushing	O
the	O
cache	B-General_Concept
after	O
a	O
context	B-Operating_System
switch	I-Operating_System
,	O
forcing	O
address	B-General_Concept
spaces	I-General_Concept
to	O
be	O
non-overlapping	O
,	O
tagging	O
the	O
virtual	O
address	O
with	O
an	O
address	B-General_Concept
space	I-General_Concept
ID	O
(	O
ASID	O
)	O
.	O
</s>
<s>
Additionally	O
,	O
there	O
is	O
a	O
problem	O
that	O
virtual-to-physical	B-Architecture
mappings	O
can	O
change	O
,	O
which	O
would	O
require	O
flushing	O
cache	B-General_Concept
lines	I-General_Concept
,	O
as	O
the	O
VAs	O
would	O
no	O
longer	O
be	O
valid	O
.	O
</s>
<s>
Virtually	O
indexed	O
,	O
physically	O
tagged	O
(	O
VIPT	O
)	O
caches	B-General_Concept
use	O
the	O
virtual	O
address	O
for	O
the	O
index	O
and	O
the	O
physical	O
address	O
in	O
the	O
tag	O
.	O
</s>
<s>
The	O
advantage	O
over	O
PIPT	O
is	O
lower	O
latency	O
,	O
as	O
the	O
cache	B-General_Concept
line	I-General_Concept
can	O
be	O
looked	O
up	O
in	O
parallel	O
with	O
the	O
TLB	B-Architecture
translation	O
,	O
however	O
the	O
tag	O
cannot	O
be	O
compared	O
until	O
the	O
physical	O
address	O
is	O
available	O
.	O
</s>
<s>
The	O
advantage	O
over	O
VIVT	O
is	O
that	O
since	O
the	O
tag	O
has	O
the	O
physical	O
address	O
,	O
the	O
cache	B-General_Concept
can	O
detect	O
homonyms	O
.	O
</s>
<s>
Theoretically	O
,	O
VIPT	O
requires	O
more	O
tags	O
bits	O
because	O
some	O
of	O
the	O
index	O
bits	O
could	O
differ	O
between	O
the	O
virtual	O
and	O
physical	O
addresses	O
(	O
for	O
example	O
bit	O
12	O
and	O
above	O
for	O
4	B-General_Concept
KiB	O
pages	O
)	O
and	O
would	O
have	O
to	O
be	O
included	O
both	O
in	O
the	O
virtual	O
index	O
and	O
in	O
the	O
physical	O
tag	O
.	O
</s>
<s>
In	O
practice	O
this	O
is	O
not	O
an	O
issue	O
because	O
,	O
in	O
order	O
to	O
avoid	O
coherency	O
problems	O
,	O
VIPT	O
caches	B-General_Concept
are	O
designed	O
to	O
have	O
no	O
such	O
index	O
bits	O
(	O
e.g.	O
,	O
by	O
limiting	O
the	O
total	O
number	O
of	O
bits	O
for	O
the	O
index	O
and	O
the	O
block	O
offset	O
to	O
12	O
for	O
4	B-General_Concept
KiB	O
pages	O
)	O
;	O
this	O
limits	O
the	O
size	O
of	O
VIPT	O
caches	B-General_Concept
to	O
the	O
page	O
size	O
times	O
the	O
associativity	O
of	O
the	O
cache	B-General_Concept
.	O
</s>
<s>
Physically	O
indexed	O
,	O
virtually	O
tagged	O
(	O
PIVT	O
)	O
caches	B-General_Concept
are	O
often	O
claimed	O
in	O
literature	O
to	O
be	O
useless	O
and	O
non-existing	O
.	O
</s>
<s>
However	O
,	O
the	O
MIPS	B-Device
R6000	I-Device
uses	O
this	O
cache	B-General_Concept
type	O
as	O
the	O
sole	O
known	O
implementation	O
.	O
</s>
<s>
The	O
R6000	B-Device
is	O
implemented	O
in	O
emitter-coupled	B-General_Concept
logic	I-General_Concept
,	O
which	O
is	O
an	O
extremely	O
fast	O
technology	O
not	O
suitable	O
for	O
large	O
memories	O
such	O
as	O
a	O
TLB	B-Architecture
.	O
</s>
<s>
The	O
R6000	B-Device
solves	O
the	O
issue	O
by	O
putting	O
the	O
TLB	B-Architecture
memory	O
into	O
a	O
reserved	O
part	O
of	O
the	O
second-level	O
cache	B-General_Concept
having	O
a	O
tiny	O
,	O
high-speed	O
TLB	B-Architecture
"	O
slice	O
"	O
on	O
chip	O
.	O
</s>
<s>
The	O
cache	B-General_Concept
is	O
indexed	O
by	O
the	O
physical	O
address	O
obtained	O
from	O
the	O
TLB	B-Architecture
slice	O
.	O
</s>
<s>
However	O
,	O
since	O
the	O
TLB	B-Architecture
slice	O
only	O
translates	O
those	O
virtual	O
address	O
bits	O
that	O
are	O
necessary	O
to	O
index	O
the	O
cache	B-General_Concept
and	O
does	O
not	O
use	O
any	O
tags	O
,	O
false	O
cache	B-General_Concept
hits	O
may	O
occur	O
,	O
which	O
is	O
solved	O
by	O
tagging	O
with	O
the	O
virtual	O
address	O
.	O
</s>
<s>
The	O
speed	O
of	O
this	O
recurrence	O
(	O
the	O
load	O
latency	O
)	O
is	O
crucial	O
to	O
CPU	O
performance	O
,	O
and	O
so	O
most	O
modern	O
level-1	O
caches	B-General_Concept
are	O
virtually	O
indexed	O
,	O
which	O
at	O
least	O
allows	O
the	O
MMU	O
's	O
TLB	B-Architecture
lookup	O
to	O
proceed	O
in	O
parallel	O
with	O
fetching	O
the	O
data	B-General_Concept
from	O
the	O
cache	B-General_Concept
RAM	B-Architecture
.	O
</s>
<s>
But	O
virtual	O
indexing	O
is	O
not	O
the	O
best	O
choice	O
for	O
all	O
cache	B-General_Concept
levels	O
.	O
</s>
<s>
The	O
cost	O
of	O
dealing	O
with	O
virtual	O
aliases	O
grows	O
with	O
cache	B-General_Concept
size	O
,	O
and	O
as	O
a	O
result	O
most	O
level-2	O
and	O
larger	O
caches	B-General_Concept
are	O
physically	O
indexed	O
.	O
</s>
<s>
Caches	B-General_Concept
have	O
historically	O
used	O
both	O
virtual	O
and	O
physical	O
addresses	O
for	O
the	O
cache	B-General_Concept
tags	O
,	O
although	O
virtual	O
tagging	O
is	O
now	O
uncommon	O
.	O
</s>
<s>
If	O
the	O
TLB	B-Architecture
lookup	O
can	O
finish	O
before	O
the	O
cache	B-General_Concept
RAM	B-Architecture
lookup	O
,	O
then	O
the	O
physical	O
address	O
is	O
available	O
in	O
time	O
for	O
tag	O
compare	O
,	O
and	O
there	O
is	O
no	O
need	O
for	O
virtual	O
tagging	O
.	O
</s>
<s>
Large	O
caches	B-General_Concept
,	O
then	O
,	O
tend	O
to	O
be	O
physically	O
tagged	O
,	O
and	O
only	O
small	O
,	O
very	O
low	O
latency	O
caches	B-General_Concept
are	O
virtually	O
tagged	O
.	O
</s>
<s>
A	O
cache	B-General_Concept
that	O
relies	O
on	O
virtual	O
indexing	O
and	O
tagging	O
becomes	O
inconsistent	O
after	O
the	O
same	O
virtual	O
address	O
is	O
mapped	O
into	O
different	O
physical	O
addresses	O
(	O
homonym	O
)	O
,	O
which	O
can	O
be	O
solved	O
by	O
using	O
physical	O
address	O
for	O
tagging	O
,	O
or	O
by	O
storing	O
the	O
address	B-General_Concept
space	I-General_Concept
identifier	O
in	O
the	O
cache	B-General_Concept
line	I-General_Concept
.	O
</s>
<s>
However	O
,	O
the	O
latter	O
approach	O
does	O
not	O
help	O
against	O
the	O
synonym	B-Application
problem	O
,	O
in	O
which	O
several	O
cache	B-General_Concept
lines	I-General_Concept
end	O
up	O
storing	O
data	B-General_Concept
for	O
the	O
same	O
physical	O
address	O
.	O
</s>
<s>
Writing	O
to	O
such	O
locations	O
may	O
update	O
only	O
one	O
location	O
in	O
the	O
cache	B-General_Concept
,	O
leaving	O
the	O
others	O
with	O
inconsistent	O
data	B-General_Concept
.	O
</s>
<s>
This	O
issue	O
may	O
be	O
solved	O
by	O
using	O
non-overlapping	O
memory	O
layouts	O
for	O
different	O
address	B-General_Concept
spaces	I-General_Concept
,	O
or	O
otherwise	O
the	O
cache	B-General_Concept
(	O
or	O
a	O
part	O
of	O
it	O
)	O
must	O
be	O
flushed	O
when	O
the	O
mapping	O
changes	O
.	O
</s>
<s>
The	O
great	O
advantage	O
of	O
virtual	O
tags	O
is	O
that	O
,	O
for	O
associative	B-General_Concept
caches	I-General_Concept
,	O
they	O
allow	O
the	O
tag	O
match	O
to	O
proceed	O
before	O
the	O
virtual	O
to	O
physical	O
translation	O
is	O
done	O
.	O
</s>
<s>
The	O
hardware	O
must	O
have	O
some	O
means	O
of	O
converting	O
the	O
physical	O
addresses	O
into	O
a	O
cache	B-General_Concept
index	O
,	O
generally	O
by	O
storing	O
physical	O
tags	O
as	O
well	O
as	O
virtual	O
tags	O
.	O
</s>
<s>
For	O
comparison	O
,	O
a	O
physically	O
tagged	O
cache	B-General_Concept
does	O
not	O
need	O
to	O
keep	O
virtual	O
tags	O
,	O
which	O
is	O
simpler	O
.	O
</s>
<s>
When	O
a	O
virtual	O
to	O
physical	O
mapping	O
is	O
deleted	O
from	O
the	O
TLB	B-Architecture
,	O
cache	B-General_Concept
entries	O
with	O
those	O
virtual	O
addresses	O
will	O
have	O
to	O
be	O
flushed	O
somehow	O
.	O
</s>
<s>
Alternatively	O
,	O
if	O
cache	B-General_Concept
entries	O
are	O
allowed	O
on	O
pages	O
not	O
mapped	O
by	O
the	O
TLB	B-Architecture
,	O
then	O
those	O
entries	O
will	O
have	O
to	O
be	O
flushed	O
when	O
the	O
access	O
rights	O
on	O
those	O
pages	O
are	O
changed	O
in	O
the	O
page	B-General_Concept
table	I-General_Concept
.	O
</s>
<s>
It	O
is	O
also	O
possible	O
for	O
the	O
operating	O
system	O
to	O
ensure	O
that	O
no	O
virtual	O
aliases	O
are	O
simultaneously	O
resident	O
in	O
the	O
cache	B-General_Concept
.	O
</s>
<s>
It	O
can	O
be	O
useful	O
to	O
distinguish	O
the	O
two	O
functions	O
of	O
tags	O
in	O
an	O
associative	B-General_Concept
cache	I-General_Concept
:	O
they	O
are	O
used	O
to	O
determine	O
which	O
way	O
of	O
the	O
entry	O
set	O
to	O
select	O
,	O
and	O
they	O
are	O
used	O
to	O
determine	O
if	O
the	O
cache	B-General_Concept
hit	O
or	O
missed	O
.	O
</s>
<s>
early	O
SPARCs	O
)	O
have	O
caches	B-General_Concept
with	O
both	O
virtual	O
and	O
physical	O
tags	O
.	O
</s>
<s>
This	O
kind	O
of	O
cache	B-General_Concept
enjoys	O
the	O
latency	O
advantage	O
of	O
a	O
virtually	O
tagged	O
cache	B-General_Concept
,	O
and	O
the	O
simple	O
software	O
interface	O
of	O
a	O
physically	O
tagged	O
cache	B-General_Concept
.	O
</s>
<s>
Also	O
,	O
during	O
miss	O
processing	O
,	O
the	O
alternate	O
ways	O
of	O
the	O
cache	B-General_Concept
line	I-General_Concept
indexed	O
have	O
to	O
be	O
probed	O
for	O
virtual	O
aliases	O
and	O
any	O
matches	O
evicted	O
.	O
</s>
<s>
The	O
extra	O
area	O
(	O
and	O
some	O
latency	O
)	O
can	O
be	O
mitigated	O
by	O
keeping	O
virtual	O
hints	O
with	O
each	O
cache	B-General_Concept
entry	O
instead	O
of	O
virtual	O
tags	O
.	O
</s>
<s>
These	O
hints	O
are	O
a	O
subset	O
or	O
hash	B-Error_Name
of	O
the	O
virtual	O
tag	O
,	O
and	O
are	O
used	O
for	O
selecting	O
the	O
way	O
of	O
the	O
cache	B-General_Concept
from	O
which	O
to	O
get	O
data	B-General_Concept
and	O
a	O
physical	O
tag	O
.	O
</s>
<s>
Like	O
a	O
virtually	O
tagged	O
cache	B-General_Concept
,	O
there	O
may	O
be	O
a	O
virtual	O
hint	O
match	O
but	O
physical	O
tag	O
mismatch	O
,	O
in	O
which	O
case	O
the	O
cache	B-General_Concept
entry	O
with	O
the	O
matching	O
hint	O
must	O
be	O
evicted	O
so	O
that	O
cache	B-General_Concept
accesses	O
after	O
the	O
cache	B-General_Concept
fill	O
at	O
this	O
address	O
will	O
have	O
just	O
one	O
hint	O
match	O
.	O
</s>
<s>
Since	O
virtual	O
hints	O
have	O
fewer	O
bits	O
than	O
virtual	O
tags	O
distinguishing	O
them	O
from	O
one	O
another	O
,	O
a	O
virtually	O
hinted	O
cache	B-General_Concept
suffers	O
more	O
conflict	O
misses	O
than	O
a	O
virtually	O
tagged	O
cache	B-General_Concept
.	O
</s>
<s>
Perhaps	O
the	O
ultimate	O
reduction	O
of	O
virtual	O
hints	O
can	O
be	O
found	O
in	O
the	O
Pentium4	B-General_Concept
(	O
Willamette	O
and	O
Northwood	O
cores	O
)	O
.	O
</s>
<s>
In	O
these	O
processors	O
the	O
virtual	O
hint	O
is	O
effectively	O
two	O
bits	O
,	O
and	O
the	O
cache	B-General_Concept
is	O
four-way	O
set	O
associative	O
.	O
</s>
<s>
Effectively	O
,	O
the	O
hardware	O
maintains	O
a	O
simple	O
permutation	O
from	O
virtual	O
address	O
to	O
cache	B-General_Concept
index	O
,	O
so	O
that	O
no	O
content-addressable	B-Data_Structure
memory	I-Data_Structure
(	O
CAM	B-Data_Structure
)	O
is	O
necessary	O
to	O
select	O
the	O
right	O
one	O
of	O
the	O
four	O
ways	O
fetched	O
.	O
</s>
<s>
Large	O
physically	O
indexed	O
caches	B-General_Concept
(	O
usually	O
secondary	O
caches	B-General_Concept
)	O
run	O
into	O
a	O
problem	O
:	O
the	O
operating	O
system	O
rather	O
than	O
the	O
application	O
controls	O
which	O
pages	O
collide	O
with	O
one	O
another	O
in	O
the	O
cache	B-General_Concept
.	O
</s>
<s>
Differences	O
in	O
page	O
allocation	O
from	O
one	O
program	O
run	O
to	O
the	O
next	O
lead	O
to	O
differences	O
in	O
the	O
cache	B-General_Concept
collision	O
patterns	O
,	O
which	O
can	O
lead	O
to	O
very	O
large	O
differences	O
in	O
program	O
performance	O
.	O
</s>
<s>
To	O
understand	O
the	O
problem	O
,	O
consider	O
a	O
CPU	O
with	O
a	O
1MiB	O
physically	O
indexed	O
direct-mapped	O
level-2	O
cache	B-General_Concept
and	O
4KiB	O
virtual	B-Architecture
memory	I-Architecture
pages	O
.	O
</s>
<s>
Sequential	O
physical	O
pages	O
map	O
to	O
sequential	O
locations	O
in	O
the	O
cache	B-General_Concept
until	O
after	O
256	O
pages	O
the	O
pattern	O
wraps	O
around	O
.	O
</s>
<s>
We	O
can	O
label	O
each	O
physical	O
page	O
with	O
a	O
color	O
of	O
0	O
–	O
255	O
to	O
denote	O
where	O
in	O
the	O
cache	B-General_Concept
it	O
can	O
go	O
.	O
</s>
<s>
Locations	O
within	O
physical	O
pages	O
with	O
different	O
colors	O
cannot	O
conflict	O
in	O
the	O
cache	B-General_Concept
.	O
</s>
<s>
Programmers	O
attempting	O
to	O
make	O
maximum	O
use	O
of	O
the	O
cache	B-General_Concept
may	O
arrange	O
their	O
programs	O
 '	O
access	O
patterns	O
so	O
that	O
only	O
1MiB	O
of	O
data	B-General_Concept
need	O
be	O
cached	O
at	O
any	O
given	O
time	O
,	O
thus	O
avoiding	O
capacity	O
misses	O
.	O
</s>
<s>
loop	O
nest	O
optimization	O
)	O
,	O
largely	O
coming	O
from	O
the	O
High	B-Architecture
Performance	I-Architecture
Computing	I-Architecture
(	O
HPC	O
)	O
community	O
.	O
</s>
<s>
In	O
fact	O
,	O
if	O
the	O
operating	O
system	O
assigns	O
physical	O
pages	O
to	O
virtual	O
pages	O
randomly	O
and	O
uniformly	O
,	O
it	O
is	O
extremely	O
likely	O
that	O
some	O
pages	O
will	O
have	O
the	O
same	O
physical	O
color	O
,	O
and	O
then	O
locations	O
from	O
those	O
pages	O
will	O
collide	O
in	O
the	O
cache	B-General_Concept
(	O
this	O
is	O
the	O
birthday	O
paradox	O
)	O
.	O
</s>
<s>
If	O
the	O
operating	O
system	O
can	O
guarantee	O
that	O
each	O
physical	O
page	O
maps	O
to	O
only	O
one	O
virtual	O
color	O
,	O
then	O
there	O
are	O
no	O
virtual	O
aliases	O
,	O
and	O
the	O
processor	O
can	O
use	O
virtually	O
indexed	O
caches	B-General_Concept
with	O
no	O
need	O
for	O
extra	O
virtual	O
alias	O
probes	O
during	O
miss	O
handling	O
.	O
</s>
<s>
Alternatively	O
,	O
the	O
OS	O
can	O
flush	O
a	O
page	O
from	O
the	O
cache	B-General_Concept
whenever	O
it	O
changes	O
from	O
one	O
virtual	O
color	O
to	O
another	O
.	O
</s>
<s>
The	O
software	O
page	O
coloring	O
technique	O
has	O
been	O
used	O
to	O
effectively	O
partition	O
the	O
shared	O
Last	O
level	O
Cache	B-General_Concept
(	O
LLC	O
)	O
in	O
multicore	B-Architecture
processors	I-Architecture
.	O
</s>
<s>
This	O
operating	O
system-based	O
LLC	O
management	O
in	O
multicore	B-Architecture
processors	I-Architecture
has	O
been	O
adopted	O
by	O
Intel	O
.	O
</s>
<s>
Modern	O
processors	O
have	O
multiple	O
interacting	O
on-chip	O
caches	B-General_Concept
.	O
</s>
<s>
The	O
operation	O
of	O
a	O
particular	O
cache	B-General_Concept
can	O
be	O
completely	O
specified	O
by	O
the	O
cache	B-General_Concept
size	O
,	O
the	O
cache	B-General_Concept
block	O
size	O
,	O
the	O
number	O
of	O
blocks	O
in	O
a	O
set	O
,	O
the	O
cache	B-General_Concept
set	O
replacement	O
policy	O
,	O
and	O
the	O
cache	B-General_Concept
write	O
policy	O
(	O
write-through	O
or	O
write-back	O
)	O
.	O
</s>
<s>
While	O
all	O
of	O
the	O
cache	B-General_Concept
blocks	O
in	O
a	O
particular	O
cache	B-General_Concept
are	O
the	O
same	O
size	O
and	O
have	O
the	O
same	O
associativity	O
,	O
typically	O
the	O
"	O
lower-level	O
"	O
caches	B-General_Concept
(	O
called	O
Level	O
1	O
cache	B-General_Concept
)	O
have	O
a	O
smaller	O
number	O
of	O
blocks	O
,	O
smaller	O
block	O
size	O
,	O
and	O
fewer	O
blocks	O
in	O
a	O
set	O
,	O
but	O
have	O
very	O
short	O
access	O
times	O
.	O
</s>
<s>
"	O
Higher-level	O
"	O
caches	B-General_Concept
(	O
i.e.	O
</s>
<s>
Cache	B-General_Concept
entry	O
replacement	O
policy	O
is	O
determined	O
by	O
a	O
cache	B-General_Concept
algorithm	I-General_Concept
selected	O
to	O
be	O
implemented	O
by	O
the	O
processor	O
designers	O
.	O
</s>
<s>
Pipelined	B-General_Concept
CPUs	I-General_Concept
access	O
memory	O
from	O
multiple	O
points	O
in	O
the	O
pipeline	B-General_Concept
:	O
instruction	O
fetch	O
,	O
virtual-to-physical	B-Architecture
address	O
translation	O
,	O
and	O
data	B-General_Concept
fetch	O
(	O
see	O
classic	B-General_Concept
RISC	I-General_Concept
pipeline	I-General_Concept
)	O
.	O
</s>
<s>
The	O
natural	O
design	O
is	O
to	O
use	O
different	O
physical	O
caches	B-General_Concept
for	O
each	O
of	O
these	O
points	O
,	O
so	O
that	O
no	O
one	O
physical	O
resource	O
has	O
to	O
be	O
scheduled	O
to	O
service	O
two	O
points	O
in	O
the	O
pipeline	B-General_Concept
.	O
</s>
<s>
Thus	O
the	O
pipeline	B-General_Concept
naturally	O
ends	O
up	O
with	O
at	O
least	O
three	O
separate	O
caches	B-General_Concept
(	O
instruction	O
,	O
TLB	B-Architecture
,	O
and	O
data	B-General_Concept
)	O
,	O
each	O
specialized	O
to	O
its	O
particular	O
role	O
.	O
</s>
<s>
A	O
victim	B-General_Concept
cache	I-General_Concept
is	O
a	O
cache	B-General_Concept
used	O
to	O
hold	O
blocks	O
evicted	O
from	O
a	O
CPU	O
cache	B-General_Concept
upon	O
replacement	O
.	O
</s>
<s>
The	O
victim	B-General_Concept
cache	I-General_Concept
lies	O
between	O
the	O
main	O
cache	B-General_Concept
and	O
its	O
refill	O
path	O
,	O
and	O
holds	O
only	O
those	O
blocks	O
of	O
data	B-General_Concept
that	O
were	O
evicted	O
from	O
the	O
main	O
cache	B-General_Concept
.	O
</s>
<s>
The	O
victim	B-General_Concept
cache	I-General_Concept
is	O
usually	O
fully	O
associative	O
,	O
and	O
is	O
intended	O
to	O
reduce	O
the	O
number	O
of	O
conflict	O
misses	O
.	O
</s>
<s>
The	O
victim	B-General_Concept
cache	I-General_Concept
exploits	O
this	O
property	O
by	O
providing	O
high	O
associativity	O
to	O
only	O
these	O
accesses	O
.	O
</s>
<s>
Intel	O
's	O
Crystalwell	O
variant	O
of	O
its	O
Haswell	B-Device
processors	O
introduced	O
an	O
on-package	O
128MiB	O
eDRAM	O
Level	O
4	B-General_Concept
cache	B-General_Concept
which	O
serves	O
as	O
a	O
victim	B-General_Concept
cache	I-General_Concept
to	O
the	O
processors	O
 '	O
Level	O
3	O
cache	B-General_Concept
.	O
</s>
<s>
In	O
the	O
Skylake	B-Architecture
microarchitecture	I-Architecture
the	O
Level	O
4	B-General_Concept
cache	B-General_Concept
no	O
longer	O
works	O
as	O
a	O
victim	B-General_Concept
cache	I-General_Concept
.	O
</s>
<s>
One	O
of	O
the	O
more	O
extreme	O
examples	O
of	O
cache	B-General_Concept
specialization	O
is	O
the	O
trace	O
cache	B-General_Concept
(	O
also	O
known	O
as	O
execution	O
trace	O
cache	B-General_Concept
)	O
found	O
in	O
the	O
Intel	B-General_Concept
Pentium	I-General_Concept
4	B-General_Concept
microprocessors	O
.	O
</s>
<s>
A	O
trace	O
cache	B-General_Concept
is	O
a	O
mechanism	O
for	O
increasing	O
the	O
instruction	O
fetch	O
bandwidth	O
and	O
decreasing	O
power	O
consumption	O
(	O
in	O
the	O
case	O
of	O
the	O
Pentium4	B-General_Concept
)	O
by	O
storing	O
traces	O
of	O
instructions	O
that	O
have	O
already	O
been	O
fetched	O
and	O
decoded	O
.	O
</s>
<s>
A	O
trace	O
cache	B-General_Concept
stores	O
instructions	O
either	O
after	O
they	O
have	O
been	O
decoded	O
,	O
or	O
as	O
they	O
are	O
retired	O
.	O
</s>
<s>
Generally	O
,	O
instructions	O
are	O
added	O
to	O
trace	O
caches	B-General_Concept
in	O
groups	O
representing	O
either	O
individual	O
basic	B-Application
blocks	I-Application
or	O
dynamic	O
instruction	O
traces	O
.	O
</s>
<s>
The	O
Pentium4	B-General_Concept
's	O
trace	O
cache	B-General_Concept
stores	O
micro-operations	B-General_Concept
resulting	O
from	O
decoding	O
x86	B-Operating_System
instructions	O
,	O
providing	O
also	O
the	O
functionality	O
of	O
a	O
micro-operation	B-General_Concept
cache	B-General_Concept
.	O
</s>
<s>
Having	O
this	O
,	O
the	O
next	O
time	O
an	O
instruction	O
is	O
needed	O
,	O
it	O
does	O
not	O
have	O
to	O
be	O
decoded	O
into	O
micro-ops	B-General_Concept
again	O
.	O
</s>
<s>
Write	O
Coalescing	O
Cache	B-General_Concept
is	O
a	O
special	O
cache	B-General_Concept
that	O
is	O
part	O
of	O
L2	O
cache	B-General_Concept
in	O
AMD	O
's	O
Bulldozer	O
microarchitecture	B-General_Concept
.	O
</s>
<s>
Stores	O
from	O
both	O
L1D	O
caches	B-General_Concept
in	O
the	O
module	O
go	O
through	O
the	O
WCC	O
,	O
where	O
they	O
are	O
buffered	O
and	O
coalesced	O
.	O
</s>
<s>
The	O
WCC	O
's	O
task	O
is	O
reducing	O
number	O
of	O
writes	O
to	O
the	O
L2	O
cache	B-General_Concept
.	O
</s>
<s>
A	O
micro-operation	B-General_Concept
cache	B-General_Concept
( μop	O
cache	B-General_Concept
,	O
uop	O
cache	B-General_Concept
or	O
UC	O
)	O
is	O
a	O
specialized	O
cache	B-General_Concept
that	O
stores	O
micro-operations	B-General_Concept
of	O
decoded	O
instructions	O
,	O
as	O
received	O
directly	O
from	O
the	O
instruction	O
decoders	O
or	O
from	O
the	O
instruction	O
cache	B-General_Concept
.	O
</s>
<s>
When	O
an	O
instruction	O
needs	O
to	O
be	O
decoded	O
,	O
the	O
μop	B-General_Concept
cache	B-General_Concept
is	O
checked	O
for	O
its	O
decoded	O
form	O
which	O
is	O
re-used	O
if	O
cached	O
;	O
if	O
it	O
is	O
not	O
available	O
,	O
the	O
instruction	O
is	O
decoded	O
and	O
then	O
cached	O
.	O
</s>
<s>
One	O
of	O
the	O
early	O
works	O
describing	O
μop	B-General_Concept
cache	B-General_Concept
as	O
an	O
alternative	O
frontend	O
for	O
the	O
Intel	B-Device
P6	I-Device
processor	O
family	O
is	O
the	O
2001	O
paper	O
"	O
Micro-Operation	B-General_Concept
Cache	B-General_Concept
:	O
A	O
Power	O
Aware	O
Frontend	O
for	O
Variable	O
Instruction	O
Length	O
ISA	O
"	O
.	O
</s>
<s>
Later	O
,	O
Intel	O
included	O
μop	B-General_Concept
caches	B-General_Concept
in	O
its	O
Sandy	B-Device
Bridge	I-Device
processors	O
and	O
in	O
successive	O
microarchitectures	B-General_Concept
like	O
Ivy	B-Device
Bridge	I-Device
and	O
Haswell	B-Device
.	O
</s>
<s>
AMD	O
implemented	O
a	O
μop	B-General_Concept
cache	B-General_Concept
in	O
their	O
Zen	O
microarchitecture	B-General_Concept
.	O
</s>
<s>
Fetching	O
complete	O
pre-decoded	O
instructions	O
eliminates	O
the	O
need	O
to	O
repeatedly	O
decode	O
variable	O
length	O
complex	O
instructions	O
into	O
simpler	O
fixed-length	O
micro-operations	B-General_Concept
,	O
and	O
simplifies	O
the	O
process	O
of	O
predicting	O
,	O
fetching	O
,	O
rotating	O
and	O
aligning	O
fetched	O
instructions	O
.	O
</s>
<s>
A	O
μop	B-General_Concept
cache	B-General_Concept
effectively	O
offloads	O
the	O
fetch	O
and	O
decode	O
hardware	O
,	O
thus	O
decreasing	O
power	O
consumption	O
and	O
improving	O
the	O
frontend	O
supply	O
of	O
decoded	O
micro-operations	B-General_Concept
.	O
</s>
<s>
The	O
μop	B-General_Concept
cache	B-General_Concept
also	O
increases	O
performance	O
by	O
more	O
consistently	O
delivering	O
decoded	O
micro-operations	B-General_Concept
to	O
the	O
backend	O
and	O
eliminating	O
various	O
bottlenecks	O
in	O
the	O
CPU	O
's	O
fetch	O
and	O
decode	O
logic	O
.	O
</s>
<s>
A	O
μop	B-General_Concept
cache	B-General_Concept
has	O
many	O
similarities	O
with	O
a	O
trace	O
cache	B-General_Concept
,	O
although	O
a	O
μop	B-General_Concept
cache	B-General_Concept
is	O
much	O
simpler	O
thus	O
providing	O
better	O
power	O
efficiency	O
;	O
this	O
makes	O
it	O
better	O
suited	O
for	O
implementations	O
on	O
battery-powered	O
devices	O
.	O
</s>
<s>
The	O
main	O
disadvantage	O
of	O
the	O
trace	O
cache	B-General_Concept
,	O
leading	O
to	O
its	O
power	O
inefficiency	O
,	O
is	O
the	O
hardware	O
complexity	O
required	O
for	O
its	O
heuristic	B-Algorithm
deciding	O
on	O
caching	B-General_Concept
and	O
reusing	O
dynamically	O
created	O
instruction	O
traces	O
.	O
</s>
<s>
A	O
branch	O
target	O
cache	B-General_Concept
or	O
branch	O
target	O
instruction	O
cache	B-General_Concept
,	O
the	O
name	O
used	O
on	O
ARM	B-Architecture
microprocessors	I-Architecture
,	O
is	O
a	O
specialized	O
cache	B-General_Concept
which	O
holds	O
the	O
first	O
few	O
instructions	O
at	O
the	O
destination	O
of	O
a	O
taken	O
branch	O
.	O
</s>
<s>
This	O
is	O
used	O
by	O
low-powered	O
processors	O
which	O
do	O
not	O
need	O
a	O
normal	O
instruction	O
cache	B-General_Concept
because	O
the	O
memory	O
system	O
is	O
capable	O
of	O
delivering	O
instructions	O
fast	O
enough	O
to	O
satisfy	O
the	O
CPU	O
without	O
one	O
.	O
</s>
<s>
However	O
,	O
this	O
only	O
applies	O
to	O
consecutive	O
instructions	O
in	O
sequence	O
;	O
it	O
still	O
takes	O
several	O
cycles	O
of	O
latency	O
to	O
restart	O
instruction	O
fetch	O
at	O
a	O
new	O
address	O
,	O
causing	O
a	O
few	O
cycles	O
of	O
pipeline	B-General_Concept
bubble	O
after	O
a	O
control	O
transfer	O
.	O
</s>
<s>
A	O
branch	O
target	O
cache	B-General_Concept
provides	O
instructions	O
for	O
those	O
few	O
cycles	O
avoiding	O
a	O
delay	O
after	O
most	O
taken	O
branches	O
.	O
</s>
<s>
This	O
allows	O
full-speed	O
operation	O
with	O
a	O
much	O
smaller	O
cache	B-General_Concept
than	O
a	O
traditional	O
full-time	O
instruction	O
cache	B-General_Concept
.	O
</s>
<s>
Smart	O
cache	B-General_Concept
is	O
a	O
level	O
2	O
or	O
level	O
3	O
caching	B-General_Concept
method	O
for	O
multiple	O
execution	O
cores	O
,	O
developed	O
by	O
Intel	O
.	O
</s>
<s>
Smart	O
Cache	B-General_Concept
shares	O
the	O
actual	O
cache	B-General_Concept
memory	I-General_Concept
between	O
the	O
cores	O
of	O
a	O
multi-core	B-Architecture
processor	I-Architecture
.	O
</s>
<s>
In	O
comparison	O
to	O
a	O
dedicated	O
per-core	O
cache	B-General_Concept
,	O
the	O
overall	O
cache	B-General_Concept
miss	O
rate	O
decreases	O
when	O
not	O
all	O
cores	O
need	O
equal	O
parts	O
of	O
the	O
cache	B-General_Concept
space	O
.	O
</s>
<s>
Consequently	O
,	O
a	O
single	O
core	O
can	O
use	O
the	O
full	O
level	O
2	O
or	O
level	O
3	O
cache	B-General_Concept
,	O
if	O
the	O
other	O
cores	O
are	O
inactive	O
.	O
</s>
<s>
Furthermore	O
,	O
the	O
shared	O
cache	B-General_Concept
makes	O
it	O
faster	O
to	O
share	O
memory	O
among	O
different	O
execution	O
cores	O
.	O
</s>
<s>
Another	O
issue	O
is	O
the	O
fundamental	O
tradeoff	O
between	O
cache	B-General_Concept
latency	O
and	O
hit	O
rate	O
.	O
</s>
<s>
Larger	O
caches	B-General_Concept
have	O
better	O
hit	O
rates	O
but	O
longer	O
latency	O
.	O
</s>
<s>
To	O
address	O
this	O
tradeoff	O
,	O
many	O
computers	O
use	O
multiple	O
levels	O
of	O
cache	B-General_Concept
,	O
with	O
small	O
fast	O
caches	B-General_Concept
backed	O
up	O
by	O
larger	O
,	O
slower	O
caches	B-General_Concept
.	O
</s>
<s>
Multi-level	O
caches	B-General_Concept
generally	O
operate	O
by	O
checking	O
the	O
fastest	O
cache	B-General_Concept
,	O
level	O
1	O
(	O
L1	O
)	O
,	O
first	O
;	O
if	O
it	O
hits	O
,	O
the	O
processor	O
proceeds	O
at	O
high	O
speed	O
.	O
</s>
<s>
If	O
that	O
smaller	O
cache	B-General_Concept
misses	O
,	O
the	O
next	O
fastest	O
cache	B-General_Concept
,	O
level	O
2	O
(	O
L2	O
)	O
,	O
is	O
checked	O
,	O
and	O
so	O
on	O
,	O
before	O
accessing	O
external	O
memory	O
.	O
</s>
<s>
As	O
the	O
latency	O
difference	O
between	O
main	O
memory	O
and	O
the	O
fastest	O
cache	B-General_Concept
has	O
become	O
larger	O
,	O
some	O
processors	O
have	O
begun	O
to	O
utilize	O
as	O
many	O
as	O
three	O
levels	O
of	O
on-chip	O
cache	B-General_Concept
.	O
</s>
<s>
Price-sensitive	O
designs	O
used	O
this	O
to	O
pull	O
the	O
entire	O
cache	B-General_Concept
hierarchy	I-General_Concept
on-chip	O
,	O
but	O
by	O
the	O
2010s	O
some	O
of	O
the	O
highest-performance	O
designs	O
returned	O
to	O
having	O
large	O
off-chip	O
caches	B-General_Concept
,	O
which	O
is	O
often	O
implemented	O
in	O
eDRAM	O
and	O
mounted	O
on	O
a	O
multi-chip	B-Algorithm
module	I-Algorithm
,	O
as	O
a	O
fourth	O
cache	B-General_Concept
level	O
.	O
</s>
<s>
In	O
rare	O
cases	O
,	O
such	O
as	O
in	O
the	O
mainframe	O
CPU	O
IBM	B-Device
z15	I-Device
(	O
2019	O
)	O
,	O
all	O
levels	O
down	O
to	O
L1	O
are	O
implemented	O
by	O
eDRAM	O
,	O
replacing	O
SRAM	B-Architecture
entirely	O
(	O
for	O
cache	B-General_Concept
,	O
SRAM	B-Architecture
is	O
still	O
used	O
for	O
registers	O
)	O
.	O
</s>
<s>
The	O
ARM-based	B-Architecture
Apple	B-Device
M1	I-Device
has	O
a	O
192KiB	O
L1	O
cache	B-General_Concept
for	O
each	O
of	O
the	O
four	O
high-performance	O
cores	O
,	O
an	O
unusually	O
large	O
amount	O
;	O
however	O
the	O
four	O
high-efficiency	O
cores	O
only	O
have	O
128KiB	O
.	O
</s>
<s>
The	O
benefits	O
of	O
L3	O
and	O
L4	O
caches	B-General_Concept
depend	O
on	O
the	O
application	O
's	O
access	O
patterns	O
.	O
</s>
<s>
Examples	O
of	O
products	O
incorporating	O
L3	O
and	O
L4	O
caches	B-General_Concept
include	O
the	O
following	O
:	O
</s>
<s>
Alpha	B-General_Concept
21164	I-General_Concept
(	O
1995	O
)	O
has	O
1	O
to	O
64MiB	O
off-chip	O
L3	O
cache	B-General_Concept
.	O
</s>
<s>
IBM	O
POWER4	B-Device
(	O
2001	O
)	O
has	O
off-chip	O
L3	O
caches	B-General_Concept
of	O
32MiB	O
per	O
processor	O
,	O
shared	O
among	O
several	O
processors	O
.	O
</s>
<s>
Itanium	O
2	O
(	O
2003	O
)	O
has	O
a	O
6MiB	O
unified	O
level	O
3	O
(	O
L3	O
)	O
cache	B-General_Concept
on-die	O
;	O
the	O
Itanium	O
2	O
(	O
2003	O
)	O
MX2	O
module	O
incorporates	O
two	O
Itanium2	O
processors	O
along	O
with	O
a	O
shared	O
64MiB	O
L4	O
cache	B-General_Concept
on	O
a	O
multi-chip	B-Algorithm
module	I-Algorithm
that	O
was	O
pin	O
compatible	O
with	O
a	O
Madison	O
processor	O
.	O
</s>
<s>
Intel	O
's	O
Xeon	B-Device
MP	I-Device
product	O
codenamed	O
"	O
Tulsa	O
"	O
(	O
2006	O
)	O
features	O
16MiB	O
of	O
on-die	O
L3	O
cache	B-General_Concept
shared	O
between	O
two	O
processor	O
cores	O
.	O
</s>
<s>
AMD	O
Phenom	O
II	O
(	O
2008	O
)	O
has	O
up	O
to	O
6MiB	O
on-die	O
unified	O
L3	O
cache	B-General_Concept
.	O
</s>
<s>
Intel	B-Device
Core	I-Device
i7	I-Device
(	O
2008	O
)	O
has	O
an	O
8MiB	O
on-die	O
unified	O
L3	O
cache	B-General_Concept
that	O
is	O
inclusive	O
,	O
shared	O
by	O
all	O
cores	O
.	O
</s>
<s>
Intel	B-Device
Haswell	I-Device
CPUs	O
with	O
integrated	O
Intel	B-Application
Iris	I-Application
Pro	I-Application
Graphics	I-Application
have	O
128MiB	O
of	O
eDRAM	O
acting	O
essentially	O
as	O
an	O
L4	O
cache	B-General_Concept
.	O
</s>
<s>
Finally	O
,	O
at	O
the	O
other	O
end	O
of	O
the	O
memory	B-General_Concept
hierarchy	I-General_Concept
,	O
the	O
CPU	B-General_Concept
register	I-General_Concept
file	O
itself	O
can	O
be	O
considered	O
the	O
smallest	O
,	O
fastest	O
cache	B-General_Concept
in	O
the	O
system	O
,	O
with	O
the	O
special	O
characteristic	O
that	O
it	O
is	O
scheduled	O
in	O
software	O
—	O
typically	O
by	O
a	O
compiler	O
,	O
as	O
it	O
allocates	O
registers	O
to	O
hold	O
values	O
retrieved	O
from	O
main	O
memory	O
for	O
,	O
as	O
an	O
example	O
,	O
loop	O
nest	O
optimization	O
.	O
</s>
<s>
However	O
,	O
with	O
register	B-Architecture
renaming	I-Architecture
most	O
compiler	O
register	B-General_Concept
assignments	O
are	O
reallocated	O
dynamically	O
by	O
hardware	O
at	O
runtime	O
into	O
a	O
register	B-General_Concept
bank	I-General_Concept
,	O
allowing	O
the	O
CPU	O
to	O
break	O
false	O
data	B-General_Concept
dependencies	O
and	O
thus	O
easing	O
pipeline	B-General_Concept
hazards	O
.	O
</s>
<s>
Register	B-General_Concept
files	I-General_Concept
sometimes	O
also	O
have	O
hierarchy	O
:	O
The	O
Cray-1	B-Device
(	O
circa	O
1976	O
)	O
had	O
eight	O
address	O
"	O
A	O
"	O
and	O
eight	O
scalar	O
data	B-General_Concept
"	O
S	O
"	O
registers	O
that	O
were	O
generally	O
usable	O
.	O
</s>
<s>
There	O
was	O
also	O
a	O
set	O
of	O
64	O
address	O
"	O
B	O
"	O
and	O
64	O
scalar	O
data	B-General_Concept
"	O
T	O
"	O
registers	O
that	O
took	O
longer	O
to	O
access	O
,	O
but	O
were	O
faster	O
than	O
main	O
memory	O
.	O
</s>
<s>
The	O
"	O
B	O
"	O
and	O
"	O
T	O
"	O
registers	O
were	O
provided	O
because	O
the	O
Cray-1	B-Device
did	O
not	O
have	O
a	O
data	B-General_Concept
cache	B-General_Concept
.	O
</s>
<s>
(	O
The	O
Cray-1	B-Device
did	O
,	O
however	O
,	O
have	O
an	O
instruction	O
cache	B-General_Concept
.	O
)	O
</s>
<s>
When	O
considering	O
a	O
chip	O
with	O
multiple	B-Architecture
cores	I-Architecture
,	O
there	O
is	O
a	O
question	O
of	O
whether	O
the	O
caches	B-General_Concept
should	O
be	O
shared	O
or	O
local	O
to	O
each	O
core	O
.	O
</s>
<s>
Implementing	O
shared	O
cache	B-General_Concept
inevitably	O
introduces	O
more	O
wiring	O
and	O
complexity	O
.	O
</s>
<s>
But	O
then	O
,	O
having	O
one	O
cache	B-General_Concept
per	O
chip	O
,	O
rather	O
than	O
core	O
,	O
greatly	O
reduces	O
the	O
amount	O
of	O
space	O
needed	O
,	O
and	O
thus	O
one	O
can	O
include	O
a	O
larger	O
cache	B-General_Concept
.	O
</s>
<s>
Typically	O
,	O
sharing	O
the	O
L1	O
cache	B-General_Concept
is	O
undesirable	O
because	O
the	O
resulting	O
increase	O
in	O
latency	O
would	O
make	O
each	O
core	O
run	O
considerably	O
slower	O
than	O
a	O
single-core	O
chip	O
.	O
</s>
<s>
However	O
,	O
for	O
the	O
highest-level	O
cache	B-General_Concept
,	O
the	O
last	O
one	O
called	O
before	O
accessing	O
memory	O
,	O
having	O
a	O
global	O
cache	B-General_Concept
is	O
desirable	O
for	O
several	O
reasons	O
,	O
such	O
as	O
allowing	O
a	O
single	O
core	O
to	O
use	O
the	O
whole	O
cache	B-General_Concept
,	O
reducing	O
data	B-General_Concept
redundancy	O
by	O
making	O
it	O
possible	O
for	O
different	O
processes	O
or	O
threads	O
to	O
share	O
cached	O
data	B-General_Concept
,	O
and	O
reducing	O
the	O
complexity	O
of	O
utilized	O
cache	B-General_Concept
coherency	I-General_Concept
protocols	O
.	O
</s>
<s>
For	O
example	O
,	O
an	O
eight-core	O
chip	O
with	O
three	O
levels	O
may	O
include	O
an	O
L1	O
cache	B-General_Concept
for	O
each	O
core	O
,	O
one	O
intermediate	O
L2	O
cache	B-General_Concept
for	O
each	O
pair	O
of	O
cores	O
,	O
and	O
one	O
L3	O
cache	B-General_Concept
shared	O
between	O
all	O
cores	O
.	O
</s>
<s>
Shared	O
highest-level	O
cache	B-General_Concept
,	O
which	O
is	O
called	O
before	O
accessing	O
memory	O
,	O
is	O
usually	O
referred	O
to	O
as	O
the	O
last	O
level	O
cache	B-General_Concept
(	O
LLC	O
)	O
.	O
</s>
<s>
Additional	O
techniques	O
are	O
used	O
for	O
increasing	O
the	O
level	O
of	O
parallelism	O
when	O
LLC	O
is	O
shared	O
between	O
multiple	B-Architecture
cores	I-Architecture
,	O
including	O
slicing	O
it	O
into	O
multiple	O
pieces	O
which	O
are	O
addressing	O
certain	O
ranges	O
of	O
memory	O
addresses	O
,	O
and	O
can	O
be	O
accessed	O
independently	O
.	O
</s>
<s>
In	O
a	O
separate	O
cache	B-General_Concept
structure	O
,	O
instructions	O
and	O
data	B-General_Concept
are	O
cached	O
separately	O
,	O
meaning	O
that	O
a	O
cache	B-General_Concept
line	I-General_Concept
is	O
used	O
to	O
cache	B-General_Concept
either	O
instructions	O
or	O
data	B-General_Concept
,	O
but	O
not	O
both	O
;	O
various	O
benefits	O
have	O
been	O
demonstrated	O
with	O
separate	O
data	B-General_Concept
and	O
instruction	O
translation	B-Architecture
lookaside	I-Architecture
buffers	I-Architecture
.	O
</s>
<s>
In	O
a	O
unified	O
structure	O
,	O
this	O
constraint	O
is	O
not	O
present	O
,	O
and	O
cache	B-General_Concept
lines	I-General_Concept
can	O
be	O
used	O
to	O
cache	B-General_Concept
both	O
instructions	O
and	O
data	B-General_Concept
.	O
</s>
<s>
Multi-level	O
caches	B-General_Concept
introduce	O
new	O
design	O
decisions	O
.	O
</s>
<s>
For	O
instance	O
,	O
in	O
some	O
processors	O
,	O
all	O
data	B-General_Concept
in	O
the	O
L1	O
cache	B-General_Concept
must	O
also	O
be	O
somewhere	O
in	O
the	O
L2	O
cache	B-General_Concept
.	O
</s>
<s>
These	O
caches	B-General_Concept
are	O
called	O
strictly	O
inclusive	O
.	O
</s>
<s>
Other	O
processors	O
(	O
like	O
the	O
AMD	B-Architecture
Athlon	I-Architecture
)	O
have	O
exclusive	O
caches	B-General_Concept
:	O
data	B-General_Concept
is	O
guaranteed	O
to	O
be	O
in	O
at	O
most	O
one	O
of	O
the	O
L1	O
and	O
L2	O
caches	B-General_Concept
,	O
never	O
in	O
both	O
.	O
</s>
<s>
Still	O
other	O
processors	O
(	O
like	O
the	O
Intel	B-General_Concept
Pentium	I-General_Concept
II	I-General_Concept
,	O
III	B-General_Concept
,	O
and	O
4	B-General_Concept
)	O
do	O
not	O
require	O
that	O
data	B-General_Concept
in	O
the	O
L1	O
cache	B-General_Concept
also	O
reside	O
in	O
the	O
L2	O
cache	B-General_Concept
,	O
although	O
it	O
may	O
often	O
do	O
so	O
.	O
</s>
<s>
The	O
advantage	O
of	O
exclusive	O
caches	B-General_Concept
is	O
that	O
they	O
store	O
more	O
data	B-General_Concept
.	O
</s>
<s>
This	O
advantage	O
is	O
larger	O
when	O
the	O
exclusive	O
L1	O
cache	B-General_Concept
is	O
comparable	O
to	O
the	O
L2	O
cache	B-General_Concept
,	O
and	O
diminishes	O
if	O
the	O
L2	O
cache	B-General_Concept
is	O
many	O
times	O
larger	O
than	O
the	O
L1	O
cache	B-General_Concept
.	O
</s>
<s>
When	O
the	O
L1	O
misses	O
and	O
the	O
L2	O
hits	O
on	O
an	O
access	O
,	O
the	O
hitting	O
cache	B-General_Concept
line	I-General_Concept
in	O
the	O
L2	O
is	O
exchanged	O
with	O
a	O
line	O
in	O
the	O
L1	O
.	O
</s>
<s>
This	O
exchange	O
is	O
quite	O
a	O
bit	O
more	O
work	O
than	O
just	O
copying	O
a	O
line	O
from	O
L2	O
to	O
L1	O
,	O
which	O
is	O
what	O
an	O
inclusive	O
cache	B-General_Concept
does	O
.	O
</s>
<s>
One	O
advantage	O
of	O
strictly	O
inclusive	O
caches	B-General_Concept
is	O
that	O
when	O
external	O
devices	O
or	O
other	O
processors	O
in	O
a	O
multiprocessor	B-Operating_System
system	O
wish	O
to	O
remove	O
a	O
cache	B-General_Concept
line	I-General_Concept
from	O
the	O
processor	O
,	O
they	O
need	O
only	O
have	O
the	O
processor	O
check	O
the	O
L2	O
cache	B-General_Concept
.	O
</s>
<s>
In	O
cache	B-General_Concept
hierarchies	I-General_Concept
which	O
do	O
not	O
enforce	O
inclusion	O
,	O
the	O
L1	O
cache	B-General_Concept
must	O
be	O
checked	O
as	O
well	O
.	O
</s>
<s>
As	O
a	O
drawback	O
,	O
there	O
is	O
a	O
correlation	O
between	O
the	O
associativities	O
of	O
L1	O
and	O
L2	O
caches	B-General_Concept
:	O
if	O
the	O
L2	O
cache	B-General_Concept
does	O
not	O
have	O
at	O
least	O
as	O
many	O
ways	O
as	O
all	O
L1	O
caches	B-General_Concept
together	O
,	O
the	O
effective	O
associativity	O
of	O
the	O
L1	O
caches	B-General_Concept
is	O
restricted	O
.	O
</s>
<s>
Another	O
disadvantage	O
of	O
inclusive	O
cache	B-General_Concept
is	O
that	O
whenever	O
there	O
is	O
an	O
eviction	O
in	O
L2	O
cache	B-General_Concept
,	O
the	O
(	O
possibly	O
)	O
corresponding	O
lines	O
in	O
L1	O
also	O
have	O
to	O
get	O
evicted	O
in	O
order	O
to	O
maintain	O
inclusiveness	O
.	O
</s>
<s>
Another	O
advantage	O
of	O
inclusive	O
caches	B-General_Concept
is	O
that	O
the	O
larger	O
cache	B-General_Concept
can	O
use	O
larger	O
cache	B-General_Concept
lines	I-General_Concept
,	O
which	O
reduces	O
the	O
size	O
of	O
the	O
secondary	O
cache	B-General_Concept
tags	O
.	O
</s>
<s>
(	O
Exclusive	O
caches	B-General_Concept
require	O
both	O
caches	B-General_Concept
to	O
have	O
the	O
same	O
size	O
cache	B-General_Concept
lines	I-General_Concept
,	O
so	O
that	O
cache	B-General_Concept
lines	I-General_Concept
can	O
be	O
swapped	O
on	O
a	O
L1	O
miss	O
,	O
L2	O
hit	O
.	O
)	O
</s>
<s>
If	O
the	O
secondary	O
cache	B-General_Concept
is	O
an	O
order	O
of	O
magnitude	O
larger	O
than	O
the	O
primary	O
,	O
and	O
the	O
cache	B-General_Concept
data	B-General_Concept
is	O
an	O
order	O
of	O
magnitude	O
larger	O
than	O
the	O
cache	B-General_Concept
tags	O
,	O
this	O
tag	O
area	O
saved	O
can	O
be	O
comparable	O
to	O
the	O
incremental	O
area	O
needed	O
to	O
store	O
the	O
L1	O
cache	B-General_Concept
data	B-General_Concept
in	O
the	O
L2	O
.	O
</s>
<s>
Scratchpad	B-General_Concept
memory	I-General_Concept
(	O
SPM	O
)	O
,	O
also	O
known	O
as	O
scratchpad	B-General_Concept
,	O
scratchpad	B-General_Concept
RAM	I-General_Concept
or	O
local	O
store	O
in	O
computer	O
terminology	O
,	O
is	O
a	O
high-speed	O
internal	O
memory	O
used	O
for	O
temporary	O
storage	O
of	O
calculations	O
,	O
data	B-General_Concept
,	O
and	O
other	O
work	O
in	O
progress	O
.	O
</s>
<s>
To	O
illustrate	O
both	O
specialization	O
and	O
multi-level	O
caching	B-General_Concept
,	O
here	O
is	O
the	O
cache	B-General_Concept
hierarchy	I-General_Concept
of	O
the	O
K8	O
core	O
in	O
the	O
AMD	B-Architecture
Athlon	I-Architecture
64	O
CPU	O
.	O
</s>
<s>
The	O
K8	O
has	O
four	O
specialized	O
caches	B-General_Concept
:	O
an	O
instruction	O
cache	B-General_Concept
,	O
an	O
instruction	O
TLB	B-Architecture
,	O
a	O
data	B-General_Concept
TLB	B-Architecture
,	O
and	O
a	O
data	B-General_Concept
cache	B-General_Concept
.	O
</s>
<s>
Each	O
of	O
these	O
caches	B-General_Concept
is	O
specialized	O
:	O
</s>
<s>
The	O
instruction	O
cache	B-General_Concept
keeps	O
copies	O
of	O
64-byte	O
lines	O
of	O
memory	O
,	O
and	O
fetches	O
16	O
bytes	O
each	O
cycle	O
.	O
</s>
<s>
Each	O
byte	O
in	O
this	O
cache	B-General_Concept
is	O
stored	O
in	O
ten	O
bits	O
rather	O
than	O
eight	O
,	O
with	O
the	O
extra	O
bits	O
marking	O
the	O
boundaries	O
of	O
instructions	O
(	O
this	O
is	O
an	O
example	O
of	O
predecoding	O
)	O
.	O
</s>
<s>
The	O
cache	B-General_Concept
has	O
only	O
parity	B-Error_Name
protection	O
rather	O
than	O
ECC	B-Error_Name
,	O
because	O
parity	B-Error_Name
is	O
smaller	O
and	O
any	O
damaged	O
data	B-General_Concept
can	O
be	O
replaced	O
by	O
fresh	O
data	B-General_Concept
fetched	O
from	O
memory	O
(	O
which	O
always	O
has	O
an	O
up-to-date	O
copy	O
of	O
instructions	O
)	O
.	O
</s>
<s>
The	O
instruction	O
TLB	B-Architecture
keeps	O
copies	O
of	O
page	B-General_Concept
table	I-General_Concept
entries	O
(	O
PTEs	O
)	O
.	O
</s>
<s>
Each	O
cycle	O
's	O
instruction	O
fetch	O
has	O
its	O
virtual	O
address	O
translated	O
through	O
this	O
TLB	B-Architecture
into	O
a	O
physical	O
address	O
.	O
</s>
<s>
The	O
operating	O
system	O
maps	O
different	O
sections	O
of	O
the	O
virtual	O
address	B-General_Concept
space	I-General_Concept
with	O
different	O
size	O
PTEs	O
.	O
</s>
<s>
The	O
data	B-General_Concept
TLB	B-Architecture
has	O
two	O
copies	O
which	O
keep	O
identical	O
entries	O
.	O
</s>
<s>
The	O
two	O
copies	O
allow	O
two	O
data	B-General_Concept
accesses	O
per	O
cycle	O
to	O
translate	O
virtual	O
addresses	O
to	O
physical	O
addresses	O
.	O
</s>
<s>
Like	O
the	O
instruction	O
TLB	B-Architecture
,	O
this	O
TLB	B-Architecture
is	O
split	O
into	O
two	O
kinds	O
of	O
entries	O
.	O
</s>
<s>
The	O
data	B-General_Concept
cache	B-General_Concept
keeps	O
copies	O
of	O
64-byte	O
lines	O
of	O
memory	O
.	O
</s>
<s>
It	O
is	O
split	O
into	O
8	O
banks	O
(	O
each	O
storing	O
8KiB	O
of	O
data	B-General_Concept
)	O
,	O
and	O
can	O
fetch	O
two	O
8-byte	O
data	B-General_Concept
each	O
cycle	O
so	O
long	O
as	O
those	O
data	B-General_Concept
are	O
in	O
different	O
banks	O
.	O
</s>
<s>
The	O
K8	O
also	O
has	O
multiple-level	O
caches	B-General_Concept
.	O
</s>
<s>
There	O
are	O
second-level	O
instruction	O
and	O
data	B-General_Concept
TLBs	O
,	O
which	O
store	O
only	O
PTEs	O
mapping	O
4KiB	O
.	O
</s>
<s>
Both	O
instruction	O
and	O
data	B-General_Concept
caches	B-General_Concept
,	O
and	O
the	O
various	O
TLBs	O
,	O
can	O
fill	O
from	O
the	O
large	O
unified	O
L2	O
cache	B-General_Concept
.	O
</s>
<s>
This	O
cache	B-General_Concept
is	O
exclusive	O
to	O
both	O
the	O
L1	O
instruction	O
and	O
data	B-General_Concept
caches	B-General_Concept
,	O
which	O
means	O
that	O
any	O
8-byte	O
line	O
can	O
only	O
be	O
in	O
one	O
of	O
the	O
L1	O
instruction	O
cache	B-General_Concept
,	O
the	O
L1	O
data	B-General_Concept
cache	B-General_Concept
,	O
or	O
the	O
L2	O
cache	B-General_Concept
.	O
</s>
<s>
It	O
is	O
,	O
however	O
,	O
possible	O
for	O
a	O
line	O
in	O
the	O
data	B-General_Concept
cache	B-General_Concept
to	O
have	O
a	O
PTE	O
which	O
is	O
also	O
in	O
one	O
of	O
the	O
TLBs	O
—	O
the	O
operating	O
system	O
is	O
responsible	O
for	O
keeping	O
the	O
TLBs	O
coherent	B-General_Concept
by	O
flushing	O
portions	O
of	O
them	O
when	O
the	O
page	B-General_Concept
tables	I-General_Concept
in	O
memory	O
are	O
updated	O
.	O
</s>
<s>
The	O
K8	O
also	O
caches	B-General_Concept
information	O
that	O
is	O
never	O
stored	O
in	O
memory	O
—	O
prediction	O
information	O
.	O
</s>
<s>
These	O
caches	B-General_Concept
are	O
not	O
shown	O
in	O
the	O
above	O
diagram	O
.	O
</s>
<s>
branch	B-General_Concept
prediction	I-General_Concept
,	O
with	O
tables	O
that	O
help	O
predict	O
whether	O
branches	O
are	O
taken	O
and	O
other	O
tables	O
which	O
predict	O
the	O
targets	O
of	O
branches	O
and	O
jumps	O
.	O
</s>
<s>
Some	O
of	O
this	O
information	O
is	O
associated	O
with	O
instructions	O
,	O
in	O
both	O
the	O
level	O
1	O
instruction	O
cache	B-General_Concept
and	O
the	O
unified	O
secondary	O
cache	B-General_Concept
.	O
</s>
<s>
The	O
K8	O
uses	O
an	O
interesting	O
trick	O
to	O
store	O
prediction	O
information	O
with	O
instructions	O
in	O
the	O
secondary	O
cache	B-General_Concept
.	O
</s>
<s>
Lines	O
in	O
the	O
secondary	O
cache	B-General_Concept
are	O
protected	O
from	O
accidental	O
data	B-General_Concept
corruption	O
(	O
e.g.	O
</s>
<s>
by	O
an	O
alpha	O
particle	O
strike	O
)	O
by	O
either	O
ECC	B-Error_Name
or	O
parity	B-Error_Name
,	O
depending	O
on	O
whether	O
those	O
lines	O
were	O
evicted	O
from	O
the	O
data	B-General_Concept
or	O
instruction	O
primary	O
caches	B-General_Concept
.	O
</s>
<s>
Since	O
the	O
parity	B-Error_Name
code	I-Error_Name
takes	O
fewer	O
bits	O
than	O
the	O
ECC	B-Error_Name
code	O
,	O
lines	O
from	O
the	O
instruction	O
cache	B-General_Concept
have	O
a	O
few	O
spare	O
bits	O
.	O
</s>
<s>
These	O
bits	O
are	O
used	O
to	O
cache	B-General_Concept
branch	B-General_Concept
prediction	I-General_Concept
information	O
associated	O
with	O
those	O
instructions	O
.	O
</s>
<s>
The	O
net	O
result	O
is	O
that	O
the	O
branch	B-General_Concept
predictor	I-General_Concept
has	O
a	O
larger	O
effective	O
history	O
table	O
,	O
and	O
so	O
has	O
better	O
accuracy	O
.	O
</s>
<s>
Other	O
processors	O
have	O
other	O
kinds	O
of	O
predictors	O
(	O
e.g.	O
,	O
the	O
store-to-load	O
bypass	O
predictor	O
in	O
the	O
DEC	O
Alpha	B-General_Concept
21264	I-General_Concept
)	O
,	O
and	O
various	O
specialized	O
predictors	O
are	O
likely	O
to	O
flourish	O
in	O
future	O
processors	O
.	O
</s>
<s>
These	O
predictors	O
are	O
caches	B-General_Concept
in	O
that	O
they	O
store	O
information	O
that	O
is	O
costly	O
to	O
compute	O
.	O
</s>
<s>
Some	O
of	O
the	O
terminology	O
used	O
when	O
discussing	O
predictors	O
is	O
the	O
same	O
as	O
that	O
for	O
caches	B-General_Concept
(	O
one	O
speaks	O
of	O
a	O
hit	O
in	O
a	O
branch	B-General_Concept
predictor	I-General_Concept
)	O
,	O
but	O
predictors	O
are	O
not	O
generally	O
thought	O
of	O
as	O
part	O
of	O
the	O
cache	B-General_Concept
hierarchy	I-General_Concept
.	O
</s>
<s>
The	O
K8	O
keeps	O
the	O
instruction	O
and	O
data	B-General_Concept
caches	B-General_Concept
coherent	B-General_Concept
in	O
hardware	O
,	O
which	O
means	O
that	O
a	O
store	O
into	O
an	O
instruction	O
closely	O
following	O
the	O
store	O
instruction	O
will	O
change	O
that	O
following	O
instruction	O
.	O
</s>
<s>
Other	O
processors	O
,	O
like	O
those	O
in	O
the	O
Alpha	O
and	O
MIPS	B-Device
family	O
,	O
have	O
relied	O
on	O
software	O
to	O
keep	O
the	O
instruction	O
cache	B-General_Concept
coherent	B-General_Concept
.	O
</s>
<s>
In	O
computer	O
engineering	O
,	O
a	O
tag	O
RAM	B-Architecture
is	O
used	O
to	O
specify	O
which	O
of	O
the	O
possible	O
memory	B-General_Concept
locations	I-General_Concept
is	O
currently	O
stored	O
in	O
a	O
CPU	O
cache	B-General_Concept
.	O
</s>
<s>
For	O
a	O
simple	O
,	O
direct-mapped	O
design	O
fast	O
SRAM	B-Architecture
can	O
be	O
used	O
.	O
</s>
<s>
Higher	O
associative	B-General_Concept
caches	I-General_Concept
usually	O
employ	O
content-addressable	B-Data_Structure
memory	I-Data_Structure
.	O
</s>
<s>
Cache	B-General_Concept
reads	O
are	O
the	O
most	O
common	O
CPU	O
operation	O
that	O
takes	O
more	O
than	O
a	O
single	O
cycle	O
.	O
</s>
<s>
Program	O
execution	O
time	O
tends	O
to	O
be	O
very	O
sensitive	O
to	O
the	O
latency	O
of	O
a	O
level-1	O
data	B-General_Concept
cache	B-General_Concept
hit	O
.	O
</s>
<s>
A	O
great	O
deal	O
of	O
design	O
effort	O
,	O
and	O
often	O
power	O
and	O
silicon	O
area	O
are	O
expended	O
making	O
the	O
caches	B-General_Concept
as	O
fast	O
as	O
possible	O
.	O
</s>
<s>
The	O
simplest	O
cache	B-General_Concept
is	O
a	O
virtually	O
indexed	O
direct-mapped	O
cache	B-General_Concept
.	O
</s>
<s>
The	O
virtual	O
address	O
is	O
calculated	O
with	O
an	O
adder	O
,	O
the	O
relevant	O
portion	O
of	O
the	O
address	O
extracted	O
and	O
used	O
to	O
index	O
an	O
SRAM	B-Architecture
,	O
which	O
returns	O
the	O
loaded	O
data	B-General_Concept
.	O
</s>
<s>
The	O
data	B-General_Concept
is	O
byte	O
aligned	O
in	O
a	O
byte	O
shifter	O
,	O
and	O
from	O
there	O
is	O
bypassed	O
to	O
the	O
next	O
operation	O
.	O
</s>
<s>
Later	O
in	O
the	O
pipeline	B-General_Concept
,	O
but	O
before	O
the	O
load	O
instruction	O
is	O
retired	O
,	O
the	O
tag	O
for	O
the	O
loaded	O
data	B-General_Concept
must	O
be	O
read	O
,	O
and	O
checked	O
against	O
the	O
virtual	O
address	O
to	O
make	O
sure	O
there	O
was	O
a	O
cache	B-General_Concept
hit	O
.	O
</s>
<s>
On	O
a	O
miss	O
,	O
the	O
cache	B-General_Concept
is	O
updated	O
with	O
the	O
requested	O
cache	B-General_Concept
line	I-General_Concept
and	O
the	O
pipeline	B-General_Concept
is	O
restarted	O
.	O
</s>
<s>
An	O
associative	B-General_Concept
cache	I-General_Concept
is	O
more	O
complicated	O
,	O
because	O
some	O
form	O
of	O
tag	O
must	O
be	O
read	O
to	O
determine	O
which	O
entry	O
of	O
the	O
cache	B-General_Concept
to	O
select	O
.	O
</s>
<s>
An	O
N-way	O
set-associative	O
level-1	O
cache	B-General_Concept
usually	O
reads	O
all	O
N	O
possible	O
tags	O
and	O
N	O
data	B-General_Concept
in	O
parallel	O
,	O
and	O
then	O
chooses	O
the	O
data	B-General_Concept
associated	O
with	O
the	O
matching	O
tag	O
.	O
</s>
<s>
Level-2	O
caches	B-General_Concept
sometimes	O
save	O
power	O
by	O
reading	O
the	O
tags	O
first	O
,	O
so	O
that	O
only	O
one	O
data	B-General_Concept
element	O
is	O
read	O
from	O
the	O
data	B-General_Concept
SRAM	B-Architecture
.	O
</s>
<s>
The	O
diagram	O
shows	O
the	O
SRAMs	O
,	O
indexing	O
,	O
and	O
multiplexing	B-Architecture
for	O
a	O
4KiB	O
,	O
2-way	O
set-associative	O
,	O
virtually	O
indexed	O
and	O
virtually	O
tagged	O
cache	B-General_Concept
with	O
64byte	O
(	O
B	O
)	O
lines	O
,	O
a	O
32-bit	O
read	O
width	O
and	O
32-bit	O
virtual	O
address	O
.	O
</s>
<s>
Because	O
the	O
cache	B-General_Concept
is	O
4KiB	O
and	O
has	O
64B	O
lines	O
,	O
there	O
are	O
just	O
64	O
lines	O
in	O
the	O
cache	B-General_Concept
,	O
and	O
we	O
read	O
two	O
at	O
a	O
time	O
from	O
a	O
Tag	O
SRAM	B-Architecture
which	O
has	O
32	O
rows	O
,	O
each	O
with	O
a	O
pair	O
of	O
21	O
bit	O
tags	O
.	O
</s>
<s>
Although	O
any	O
function	O
of	O
virtual	O
address	O
bits	O
31	O
through	O
6	O
could	O
be	O
used	O
to	O
index	O
the	O
tag	O
and	O
data	B-General_Concept
SRAMs	O
,	O
it	O
is	O
simplest	O
to	O
use	O
the	O
least	O
significant	O
bits	O
.	O
</s>
<s>
Similarly	O
,	O
because	O
the	O
cache	B-General_Concept
is	O
4KiB	O
and	O
has	O
a	O
4B	O
read	O
path	O
,	O
and	O
reads	O
two	O
ways	O
for	O
each	O
access	O
,	O
the	O
Data	B-General_Concept
SRAM	B-Architecture
is	O
512	O
rows	O
by	O
8	O
bytes	O
wide	O
.	O
</s>
<s>
A	O
more	O
modern	O
cache	B-General_Concept
might	O
be	O
16KiB	O
,	O
4-way	O
set-associative	O
,	O
virtually	O
indexed	O
,	O
virtually	O
hinted	O
,	O
and	O
physically	O
tagged	O
,	O
with	O
32B	O
lines	O
,	O
32-bit	O
read	O
width	O
and	O
36-bit	O
physical	O
addresses	O
.	O
</s>
<s>
The	O
read	O
path	O
recurrence	O
for	O
such	O
a	O
cache	B-General_Concept
looks	O
very	O
similar	O
to	O
the	O
path	O
above	O
.	O
</s>
<s>
Later	O
on	O
in	O
the	O
pipeline	B-General_Concept
,	O
the	O
virtual	O
address	O
is	O
translated	O
into	O
a	O
physical	O
address	O
by	O
the	O
TLB	B-Architecture
,	O
and	O
the	O
physical	O
tag	O
is	O
read	O
(	O
just	O
one	O
,	O
as	O
the	O
vhint	O
supplies	O
which	O
way	O
of	O
the	O
cache	B-General_Concept
to	O
read	O
)	O
.	O
</s>
<s>
Some	O
SPARC	O
designs	O
have	O
improved	O
the	O
speed	O
of	O
their	O
L1	O
caches	B-General_Concept
by	O
a	O
few	O
gate	O
delays	O
by	O
collapsing	O
the	O
virtual	O
address	O
adder	O
into	O
the	O
SRAM	B-Architecture
decoders	O
.	O
</s>
<s>
The	O
early	O
history	O
of	O
cache	B-General_Concept
technology	O
is	O
closely	O
tied	O
to	O
the	O
invention	O
and	O
use	O
of	O
virtual	B-Architecture
memory	I-Architecture
.	O
</s>
<s>
Because	O
of	O
scarcity	O
and	O
cost	O
of	O
semi-conductor	O
memories	O
,	O
early	O
mainframe	O
computers	O
in	O
the	O
1960s	O
used	O
a	O
complex	O
hierarchy	O
of	O
physical	O
memory	O
,	O
mapped	O
onto	O
a	O
flat	O
virtual	B-Architecture
memory	I-Architecture
space	O
used	O
by	O
programs	O
.	O
</s>
<s>
Virtual	B-Architecture
memory	I-Architecture
seen	O
and	O
used	O
by	O
programs	O
would	O
be	O
flat	O
and	O
caching	B-General_Concept
would	O
be	O
used	O
to	O
fetch	O
data	B-General_Concept
and	O
instructions	O
into	O
the	O
fastest	O
memory	O
ahead	O
of	O
processor	O
access	O
.	O
</s>
<s>
Extensive	O
studies	O
were	O
done	O
to	O
optimize	O
the	O
cache	B-General_Concept
sizes	O
.	O
</s>
<s>
Optimal	O
values	O
were	O
found	O
to	O
depend	O
greatly	O
on	O
the	O
programming	O
language	O
used	O
with	O
Algol	O
needing	O
the	O
smallest	O
and	O
Fortran	O
and	O
Cobol	O
needing	O
the	O
largest	O
cache	B-General_Concept
sizes	O
.	O
</s>
<s>
In	O
the	O
early	O
days	O
of	O
microcomputer	O
technology	O
,	O
memory	O
access	O
was	O
only	O
slightly	O
slower	O
than	O
register	B-General_Concept
access	O
.	O
</s>
<s>
While	O
it	O
was	O
technically	O
possible	O
to	O
have	O
all	O
the	O
main	O
memory	O
as	O
fast	O
as	O
the	O
CPU	O
,	O
a	O
more	O
economically	O
viable	O
path	O
has	O
been	O
taken	O
:	O
use	O
plenty	O
of	O
low-speed	O
memory	O
,	O
but	O
also	O
introduce	O
a	O
small	O
high-speed	O
cache	B-General_Concept
memory	I-General_Concept
to	O
alleviate	O
the	O
performance	O
gap	O
.	O
</s>
<s>
The	O
first	O
documented	O
uses	O
of	O
a	O
TLB	B-Architecture
were	O
on	O
the	O
GE	B-Device
645	I-Device
and	O
the	O
IBM	B-Device
360/67	I-Device
,	O
both	O
of	O
which	O
used	O
an	O
associative	O
memory	O
as	O
a	O
TLB	B-Architecture
.	O
</s>
<s>
The	O
first	O
documented	O
use	O
of	O
an	O
instruction	O
cache	B-General_Concept
was	O
on	O
the	O
CDC	B-Device
6600	I-Device
.	O
</s>
<s>
The	O
first	O
documented	O
use	O
of	O
a	O
data	B-General_Concept
cache	B-General_Concept
was	O
on	O
the	O
IBM	B-Device
System/360	I-Device
Model	I-Device
85	I-Device
.	O
</s>
<s>
The	O
68010	B-Device
,	O
released	O
in	O
1982	O
,	O
has	O
a	O
"	O
loop	O
mode	O
"	O
which	O
can	O
be	O
considered	O
a	O
tiny	O
and	O
special-case	O
instruction	O
cache	B-General_Concept
that	O
accelerates	O
loops	O
that	O
consist	O
of	O
only	O
two	O
instructions	O
.	O
</s>
<s>
The	O
68020	B-Device
,	O
released	O
in	O
1984	O
,	O
replaced	O
that	O
with	O
a	O
typical	O
instruction	O
cache	B-General_Concept
of	O
256	O
bytes	O
,	O
being	O
the	O
first	O
68k	O
series	O
processor	O
to	O
feature	O
true	O
on-chip	O
cache	B-General_Concept
memory	I-General_Concept
.	O
</s>
<s>
The	O
68030	B-Device
,	O
released	O
in	O
1987	O
,	O
is	O
basically	O
a	O
68020	B-Device
core	O
with	O
an	O
additional	O
256-byte	O
data	B-General_Concept
cache	B-General_Concept
,	O
an	O
on-chip	O
memory	B-General_Concept
management	I-General_Concept
unit	I-General_Concept
(	O
MMU	O
)	O
,	O
a	O
process	O
shrink	O
,	O
and	O
added	O
burst	O
mode	O
for	O
the	O
caches	B-General_Concept
.	O
</s>
<s>
The	O
68040	B-Device
,	O
released	O
in	O
1990	O
,	O
has	O
split	O
instruction	O
and	O
data	B-General_Concept
caches	B-General_Concept
of	O
four	O
kilobytes	O
each	O
.	O
</s>
<s>
The	O
68060	B-General_Concept
,	O
released	O
in	O
1994	O
,	O
has	O
the	O
following	O
:	O
8KiB	O
data	B-General_Concept
cache	B-General_Concept
(	O
four-way	O
associative	O
)	O
,	O
8KiB	O
instruction	O
cache	B-General_Concept
(	O
four-way	O
associative	O
)	O
,	O
96-byte	O
FIFO	O
instruction	O
buffer	O
,	O
256-entry	O
branch	O
cache	B-General_Concept
,	O
and	O
64-entry	O
address	O
translation	O
cache	B-General_Concept
MMU	O
buffer	O
(	O
four-way	O
associative	O
)	O
.	O
</s>
<s>
As	O
the	O
x86	B-Operating_System
microprocessors	I-Operating_System
reached	O
clock	O
rates	O
of	O
20MHz	O
and	O
above	O
in	O
the	O
386	B-General_Concept
,	O
small	O
amounts	O
of	O
fast	O
cache	B-General_Concept
memory	I-General_Concept
began	O
to	O
be	O
featured	O
in	O
systems	O
to	O
improve	O
performance	O
.	O
</s>
<s>
The	O
cache	B-General_Concept
was	O
constructed	O
from	O
more	O
expensive	O
,	O
but	O
significantly	O
faster	O
,	O
SRAM	B-Architecture
memory	B-Algorithm
cells	I-Algorithm
,	O
which	O
at	O
the	O
time	O
had	O
latencies	O
around	O
10	O
–	O
25ns	O
.	O
</s>
<s>
The	O
early	O
caches	B-General_Concept
were	O
external	O
to	O
the	O
processor	O
and	O
typically	O
located	O
on	O
the	O
motherboard	B-Device
in	O
the	O
form	O
of	O
eight	O
or	O
nine	O
DIP	B-Algorithm
devices	O
placed	O
in	O
sockets	O
to	O
enable	O
the	O
cache	B-General_Concept
as	O
an	O
optional	O
extra	O
or	O
upgrade	O
feature	O
.	O
</s>
<s>
Some	O
versions	O
of	O
the	O
Intel	B-General_Concept
386	I-General_Concept
processor	O
could	O
support	O
16	O
to	O
256KiB	O
of	O
external	O
cache	B-General_Concept
.	O
</s>
<s>
With	O
the	O
486	B-General_Concept
processor	I-General_Concept
,	O
an	O
8KiB	O
cache	B-General_Concept
was	O
integrated	O
directly	O
into	O
the	O
CPU	O
die	O
.	O
</s>
<s>
This	O
cache	B-General_Concept
was	O
termed	O
Level	O
1	O
or	O
L1	O
cache	B-General_Concept
to	O
differentiate	O
it	O
from	O
the	O
slower	O
on-motherboard	O
,	O
or	O
Level	O
2	O
(	O
L2	O
)	O
cache	B-General_Concept
.	O
</s>
<s>
These	O
on-motherboard	O
caches	B-General_Concept
were	O
much	O
larger	O
,	O
with	O
the	O
most	O
common	O
size	O
being	O
256KiB	O
.	O
</s>
<s>
The	O
popularity	O
of	O
on-motherboard	O
cache	B-General_Concept
continued	O
through	O
the	O
Pentium	B-General_Concept
MMX	I-General_Concept
era	O
but	O
was	O
made	O
obsolete	O
by	O
the	O
introduction	O
of	O
SDRAM	O
and	O
the	O
growing	O
disparity	O
between	O
bus	O
clock	O
rates	O
and	O
CPU	O
clock	O
rates	O
,	O
which	O
caused	O
on-motherboard	O
cache	B-General_Concept
to	O
be	O
only	O
slightly	O
faster	O
than	O
main	O
memory	O
.	O
</s>
<s>
The	O
next	O
development	O
in	O
cache	B-General_Concept
implementation	O
in	O
the	O
x86	B-Operating_System
microprocessors	I-Operating_System
began	O
with	O
the	O
Pentium	B-Device
Pro	I-Device
,	O
which	O
brought	O
the	O
secondary	O
cache	B-General_Concept
onto	O
the	O
same	O
package	O
as	O
the	O
microprocessor	O
,	O
clocked	O
at	O
the	O
same	O
frequency	O
as	O
the	O
microprocessor	O
.	O
</s>
<s>
On-motherboard	O
caches	B-General_Concept
enjoyed	O
prolonged	O
popularity	O
thanks	O
to	O
the	O
AMD	O
K6-2	O
and	O
AMD	B-Architecture
K6-III	I-Architecture
processors	O
that	O
still	O
used	O
Socket	B-General_Concept
7	I-General_Concept
,	O
which	O
was	O
previously	O
used	O
by	O
Intel	O
with	O
on-motherboard	O
caches	B-General_Concept
.	O
</s>
<s>
K6-III	B-Architecture
included	O
256KiB	O
on-die	O
L2	O
cache	B-General_Concept
and	O
took	O
advantage	O
of	O
the	O
on-board	O
cache	B-General_Concept
as	O
a	O
third	O
level	O
cache	B-General_Concept
,	O
named	O
L3	O
(	O
motherboards	B-Device
with	O
up	O
to	O
2MiB	O
of	O
on-board	O
cache	B-General_Concept
were	O
produced	O
)	O
.	O
</s>
<s>
After	O
the	O
Socket7	O
became	O
obsolete	O
,	O
on-motherboard	O
cache	B-General_Concept
disappeared	O
from	O
the	O
x86	B-Operating_System
systems	O
.	O
</s>
<s>
The	O
three-level	O
caches	B-General_Concept
were	O
used	O
again	O
first	O
with	O
the	O
introduction	O
of	O
multiple	O
processor	O
cores	O
,	O
where	O
the	O
L3	O
cache	B-General_Concept
was	O
added	O
to	O
the	O
CPU	O
die	O
.	O
</s>
<s>
It	O
became	O
common	O
for	O
the	O
total	O
cache	B-General_Concept
sizes	O
to	O
be	O
increasingly	O
larger	O
in	O
newer	O
processor	O
generations	O
,	O
and	O
recently	O
(	O
as	O
of	O
2011	O
)	O
it	O
is	O
not	O
uncommon	O
to	O
find	O
Level	O
3	O
cache	B-General_Concept
sizes	O
of	O
tens	O
of	O
megabytes	O
.	O
</s>
<s>
Intel	O
introduced	O
a	O
Level	O
4	B-General_Concept
on-package	O
cache	B-General_Concept
with	O
the	O
Haswell	B-Device
microarchitecture	I-Device
.	O
</s>
<s>
Crystalwell	O
Haswell	B-Device
CPUs	O
,	O
equipped	O
with	O
the	O
GT3e	O
variant	O
of	O
Intel	O
's	O
integrated	O
Iris	B-Application
Pro	I-Application
graphics	I-Application
,	O
effectively	O
feature	O
128MiB	O
of	O
embedded	O
DRAM	O
(	O
eDRAM	O
)	O
on	O
the	O
same	O
package	O
.	O
</s>
<s>
This	O
L4	O
cache	B-General_Concept
is	O
shared	O
dynamically	O
between	O
the	O
on-die	O
GPU	O
and	O
CPU	O
,	O
and	O
serves	O
as	O
a	O
victim	B-General_Concept
cache	I-General_Concept
to	O
the	O
CPU	O
's	O
L3	O
cache	B-General_Concept
.	O
</s>
<s>
Apple	B-Device
M1	I-Device
CPU	O
has	O
128	O
or	O
192KiB	O
instruction	O
L1	O
cache	B-General_Concept
for	O
each	O
core	O
(	O
important	O
for	O
latency/single	O
-thread	O
performance	O
)	O
,	O
depending	O
on	O
core	O
type	O
.	O
</s>
<s>
This	O
is	O
an	O
unusually	O
large	O
L1	O
cache	B-General_Concept
for	O
any	O
CPU	O
type	O
(	O
not	O
just	O
for	O
a	O
laptop	O
)	O
;	O
the	O
total	O
cache	B-General_Concept
memory	I-General_Concept
size	O
is	O
not	O
unusually	O
large	O
(	O
the	O
total	O
is	O
more	O
important	O
for	O
throughput	O
)	O
for	O
a	O
laptop	O
,	O
and	O
much	O
larger	O
total	O
(	O
e.g.	O
</s>
<s>
Early	O
cache	B-General_Concept
designs	O
focused	O
entirely	O
on	O
the	O
direct	O
cost	O
of	O
cache	B-General_Concept
and	O
RAM	B-Architecture
and	O
average	O
execution	O
speed	O
.	O
</s>
<s>
More	O
recent	O
cache	B-General_Concept
designs	O
also	O
consider	O
energy	O
efficiency	O
,	O
fault	O
tolerance	O
,	O
and	O
other	O
goals	O
.	O
</s>
<s>
There	O
are	O
several	O
tools	O
available	O
to	O
computer	O
architects	O
to	O
help	O
explore	O
tradeoffs	O
between	O
the	O
cache	B-General_Concept
cycle	O
time	O
,	O
energy	O
,	O
and	O
area	O
;	O
the	O
CACTI	O
cache	B-General_Concept
simulator	O
and	O
the	O
SimpleScalar	O
instruction	O
set	O
simulator	O
are	O
two	O
open-source	O
options	O
.	O
</s>
<s>
A	O
multi-ported	O
cache	B-General_Concept
is	O
a	O
cache	B-General_Concept
which	O
can	O
serve	O
more	O
than	O
one	O
request	O
at	O
a	O
time	O
.	O
</s>
<s>
When	O
accessing	O
a	O
traditional	O
cache	B-General_Concept
we	O
normally	O
use	O
a	O
single	O
memory	B-General_Concept
address	I-General_Concept
,	O
whereas	O
in	O
a	O
multi-ported	O
cache	B-General_Concept
we	O
may	O
request	O
N	O
addresses	O
at	O
a	O
time	O
where	O
N	O
is	O
the	O
number	O
of	O
ports	O
that	O
connected	O
through	O
the	O
processor	O
and	O
the	O
cache	B-General_Concept
.	O
</s>
<s>
The	O
benefit	O
of	O
this	O
is	O
that	O
a	O
pipelined	B-General_Concept
processor	I-General_Concept
may	O
access	O
memory	O
from	O
different	O
phases	O
in	O
its	O
pipeline	B-General_Concept
.	O
</s>
<s>
Another	O
benefit	O
is	O
that	O
it	O
allows	O
the	O
concept	O
of	O
super-scalar	O
processors	O
through	O
different	O
cache	B-General_Concept
levels	O
.	O
</s>
