<s>
Cache	B-General_Concept
hierarchy	I-General_Concept
,	O
or	O
multi-level	O
caches	B-General_Concept
,	O
refers	O
to	O
a	O
memory	O
architecture	O
that	O
uses	O
a	O
hierarchy	O
of	O
memory	O
stores	O
based	O
on	O
varying	O
access	O
speeds	O
to	O
cache	B-General_Concept
data	O
.	O
</s>
<s>
Highly	O
requested	O
data	O
is	O
cached	O
in	O
high-speed	O
access	O
memory	O
stores	O
,	O
allowing	O
swifter	O
access	O
by	O
central	B-General_Concept
processing	I-General_Concept
unit	I-General_Concept
(	O
CPU	O
)	O
cores	O
.	O
</s>
<s>
Cache	B-General_Concept
hierarchy	I-General_Concept
is	O
a	O
form	O
and	O
part	O
of	O
memory	B-General_Concept
hierarchy	I-General_Concept
and	O
can	O
be	O
considered	O
a	O
form	O
of	O
tiered	B-General_Concept
storage	I-General_Concept
.	O
</s>
<s>
This	O
design	O
was	O
intended	O
to	O
allow	O
CPU	B-Architecture
cores	I-Architecture
to	O
process	O
faster	O
despite	O
the	O
memory	B-Architecture
latency	I-Architecture
of	O
main	B-General_Concept
memory	I-General_Concept
access	O
.	O
</s>
<s>
Accessing	O
main	B-General_Concept
memory	I-General_Concept
can	O
act	O
as	O
a	O
bottleneck	O
for	O
CPU	B-Architecture
core	I-Architecture
performance	O
as	O
the	O
CPU	O
waits	O
for	O
data	O
,	O
while	O
making	O
all	O
of	O
main	B-General_Concept
memory	I-General_Concept
high-speed	O
may	O
be	O
prohibitively	O
expensive	O
.	O
</s>
<s>
High-speed	O
caches	B-General_Concept
are	O
a	O
compromise	O
allowing	O
high-speed	O
access	O
to	O
the	O
data	O
most-used	O
by	O
the	O
CPU	O
,	O
permitting	O
a	O
faster	O
CPU	O
clock	O
.	O
</s>
<s>
CPUs	O
were	O
increasingly	O
capable	O
of	O
running	O
and	O
executing	O
larger	O
amounts	O
of	O
instructions	O
in	O
a	O
given	O
time	O
,	O
but	O
the	O
time	O
needed	O
to	O
access	O
data	O
from	O
main	B-General_Concept
memory	I-General_Concept
prevented	O
programs	O
from	O
fully	O
benefiting	O
from	O
this	O
capability	O
.	O
</s>
<s>
This	O
resulted	O
in	O
the	O
concept	O
of	O
cache	B-General_Concept
memory	I-General_Concept
,	O
first	O
proposed	O
by	O
Maurice	O
Wilkes	O
,	O
a	O
British	O
computer	O
scientist	O
at	O
the	O
University	O
of	O
Cambridge	O
in	O
1965	O
.	O
</s>
<s>
Between	O
roughly	O
1970	O
and	O
1990	O
,	O
papers	O
and	O
articles	O
by	O
Anant	O
Agarwal	O
,	O
Alan	O
Jay	O
Smith	O
,	O
Mark	O
D	O
.	O
Hill	O
,	O
Thomas	O
R	O
.	O
Puzak	O
,	O
and	O
others	O
discussed	O
better	O
cache	B-General_Concept
memory	I-General_Concept
designs	O
.	O
</s>
<s>
The	O
first	O
cache	B-General_Concept
memory	I-General_Concept
models	O
were	O
implemented	O
at	O
the	O
time	O
,	O
but	O
even	O
as	O
researchers	O
were	O
investigating	O
and	O
proposing	O
better	O
designs	O
,	O
the	O
need	O
for	O
faster	O
memory	O
models	O
continued	O
.	O
</s>
<s>
This	O
need	O
resulted	O
from	O
the	O
fact	O
that	O
although	O
early	O
cache	B-General_Concept
models	O
improved	O
data	O
access	O
latency	O
,	O
with	O
respect	O
to	O
cost	O
and	O
technical	O
limitations	O
it	O
was	O
not	O
feasible	O
for	O
a	O
computer	O
system	O
's	O
cache	B-General_Concept
to	O
approach	O
the	O
size	O
of	O
main	B-General_Concept
memory	I-General_Concept
.	O
</s>
<s>
From	O
1990	O
onward	O
,	O
ideas	O
such	O
as	O
adding	O
another	O
cache	B-General_Concept
level	O
(	O
second-level	O
)	O
,	O
as	O
a	O
backup	O
for	O
the	O
first-level	B-General_Concept
cache	I-General_Concept
were	O
proposed	O
.	O
</s>
<s>
When	O
several	O
simulations	O
and	O
implementations	O
demonstrated	O
the	O
advantages	O
of	O
two-level	O
cache	B-General_Concept
models	O
,	O
the	O
concept	O
of	O
multi-level	O
caches	B-General_Concept
caught	O
on	O
as	O
a	O
new	O
and	O
generally	O
better	O
model	O
of	O
cache	B-General_Concept
memories	I-General_Concept
.	O
</s>
<s>
Since	O
2000	O
,	O
multi-level	O
cache	B-General_Concept
models	O
have	O
received	O
widespread	O
attention	O
and	O
are	O
currently	O
implemented	O
in	O
many	O
systems	O
,	O
such	O
as	O
the	O
three-level	O
caches	B-General_Concept
that	O
are	O
present	O
in	O
Intel	O
's	O
Core	O
i7	O
products	O
.	O
</s>
<s>
Accessing	O
main	B-General_Concept
memory	I-General_Concept
for	O
each	O
instruction	B-Language
execution	O
may	O
result	O
in	O
slow	O
processing	O
,	O
with	O
the	O
clock	O
speed	O
depending	O
on	O
the	O
time	O
required	O
to	O
find	O
and	O
fetch	O
the	O
data	O
.	O
</s>
<s>
In	O
order	O
to	O
hide	O
this	O
memory	B-Architecture
latency	I-Architecture
from	O
the	O
processor	O
,	O
data	O
caching	B-General_Concept
is	O
used	O
.	O
</s>
<s>
Whenever	O
the	O
data	O
is	O
required	O
by	O
the	O
processor	O
,	O
it	O
is	O
fetched	O
from	O
the	O
main	B-General_Concept
memory	I-General_Concept
and	O
stored	O
in	O
the	O
smaller	O
memory	O
structure	O
called	O
a	O
cache	B-General_Concept
.	O
</s>
<s>
If	O
there	O
is	O
any	O
further	O
need	O
of	O
that	O
data	O
,	O
the	O
cache	B-General_Concept
is	O
searched	O
first	O
before	O
going	O
to	O
the	O
main	B-General_Concept
memory	I-General_Concept
.	O
</s>
<s>
This	O
structure	O
resides	O
closer	O
to	O
the	O
processor	O
in	O
terms	O
of	O
the	O
time	O
taken	O
to	O
search	O
and	O
fetch	O
data	O
with	O
respect	O
to	O
the	O
main	B-General_Concept
memory	I-General_Concept
.	O
</s>
<s>
The	O
advantages	O
of	O
using	O
cache	B-General_Concept
can	O
be	O
proven	O
by	O
calculating	O
the	O
average	O
access	O
time	O
(	O
AAT	O
)	O
for	O
the	O
memory	B-General_Concept
hierarchy	I-General_Concept
with	O
and	O
without	O
the	O
cache	B-General_Concept
.	O
</s>
<s>
Caches	B-General_Concept
,	O
being	O
small	O
in	O
size	O
,	O
may	O
result	O
in	O
frequent	O
misses	O
–	O
when	O
a	O
search	O
of	O
the	O
cache	B-General_Concept
does	O
not	O
provide	O
the	O
sought-after	O
information	O
–	O
resulting	O
in	O
a	O
call	O
to	O
main	B-General_Concept
memory	I-General_Concept
to	O
fetch	O
data	O
.	O
</s>
<s>
AAT	O
for	O
main	B-General_Concept
memory	I-General_Concept
is	O
given	O
by	O
Hit	O
time	O
main	B-General_Concept
memory	I-General_Concept
.	O
</s>
<s>
Hit	O
timecache	O
+	O
(	O
Miss	O
ratecache	O
×	O
Miss	O
Penaltytime	O
taken	O
to	O
go	O
to	O
main	B-General_Concept
memory	I-General_Concept
after	O
missing	O
cache	B-General_Concept
)	O
.	O
</s>
<s>
The	O
hit	O
time	O
for	O
caches	B-General_Concept
is	O
less	O
than	O
the	O
hit	O
time	O
for	O
the	O
main	B-General_Concept
memory	I-General_Concept
,	O
so	O
the	O
AAT	O
for	O
data	O
retrieval	O
is	O
significantly	O
lower	O
when	O
accessing	O
data	O
through	O
the	O
cache	B-General_Concept
rather	O
than	O
main	B-General_Concept
memory	I-General_Concept
.	O
</s>
<s>
While	O
using	O
the	O
cache	B-General_Concept
may	O
improve	O
memory	B-Architecture
latency	I-Architecture
,	O
it	O
may	O
not	O
always	O
result	O
in	O
the	O
required	O
improvement	O
for	O
the	O
time	O
taken	O
to	O
fetch	O
data	O
due	O
to	O
the	O
way	O
caches	B-General_Concept
are	O
organized	O
and	O
traversed	O
.	O
</s>
<s>
For	O
example	O
,	O
direct-mapped	O
caches	B-General_Concept
that	O
are	O
the	O
same	O
size	O
usually	O
have	O
a	O
higher	O
miss	O
rate	O
than	O
fully	O
associative	O
caches	B-General_Concept
.	O
</s>
<s>
But	O
using	O
a	O
fully	O
associative	O
cache	B-General_Concept
may	O
result	O
in	O
more	O
power	O
consumption	O
,	O
as	O
it	O
has	O
to	O
search	O
the	O
whole	O
cache	B-General_Concept
every	O
time	O
.	O
</s>
<s>
Due	O
to	O
this	O
,	O
the	O
trade-off	O
between	O
power	O
consumption	O
(	O
and	O
associated	O
heat	O
)	O
and	O
the	O
size	O
of	O
the	O
cache	B-General_Concept
becomes	O
critical	O
in	O
the	O
cache	B-General_Concept
design	O
.	O
</s>
<s>
In	O
the	O
case	O
of	O
a	O
cache	B-General_Concept
miss	O
,	O
the	O
purpose	O
of	O
using	O
such	O
a	O
structure	O
will	O
be	O
rendered	O
useless	O
and	O
the	O
computer	O
will	O
have	O
to	O
go	O
to	O
the	O
main	B-General_Concept
memory	I-General_Concept
to	O
fetch	O
the	O
required	O
data	O
.	O
</s>
<s>
However	O
,	O
with	O
a	O
multiple-level	B-General_Concept
cache	I-General_Concept
,	O
if	O
the	O
computer	O
misses	O
the	O
cache	B-General_Concept
closest	O
to	O
the	O
processor	O
(	O
level-one	O
cache	B-General_Concept
or	O
L1	O
)	O
it	O
will	O
then	O
search	O
through	O
the	O
next-closest	O
level(s )	O
of	O
cache	B-General_Concept
and	O
go	O
to	O
main	B-General_Concept
memory	I-General_Concept
only	O
if	O
these	O
methods	O
fail	O
.	O
</s>
<s>
The	O
general	O
trend	O
is	O
to	O
keep	O
the	O
L1	O
cache	B-General_Concept
small	O
and	O
at	O
a	O
distance	O
of	O
1	O
–	O
2	O
CPU	O
clock	O
cycles	O
from	O
the	O
processor	O
,	O
with	O
the	O
lower	O
levels	O
of	O
caches	B-General_Concept
increasing	O
in	O
size	O
to	O
store	O
more	O
data	O
than	O
L1	O
,	O
hence	O
being	O
more	O
distant	O
but	O
with	O
a	O
lower	O
miss	O
rate	O
.	O
</s>
<s>
The	O
number	O
of	O
cache	B-General_Concept
levels	O
can	O
be	O
designed	O
by	O
architects	O
according	O
to	O
their	O
requirements	O
after	O
checking	O
for	O
trade-offs	O
between	O
cost	O
,	O
AATs	O
,	O
and	O
size	O
.	O
</s>
<s>
With	O
the	O
technology-scaling	O
that	O
allowed	O
memory	O
systems	O
able	O
to	O
be	O
accommodated	O
on	O
a	O
single	O
chip	O
,	O
most	O
modern	O
day	O
processors	O
have	O
up	O
to	O
three	O
or	O
four	O
cache	B-General_Concept
levels	O
.	O
</s>
<s>
The	O
reduction	O
in	O
the	O
AAT	O
can	O
be	O
understood	O
by	O
this	O
example	O
,	O
where	O
the	O
computer	O
checks	O
AAT	O
for	O
different	O
configurations	O
up	O
to	O
L3	O
caches	B-General_Concept
.	O
</s>
<s>
Example	O
:	O
main	B-General_Concept
memory	I-General_Concept
=	O
50	O
,	O
L1	O
=	O
1ns	O
with	O
10%	O
miss	O
rate	O
,	O
L2	O
=	O
5ns	O
with	O
1%	O
miss	O
rate	O
,	O
L3	O
=	O
10ns	O
with	O
0.2	O
%	O
miss	O
rate	O
.	O
</s>
<s>
Cache	B-General_Concept
memory	I-General_Concept
comes	O
at	O
an	O
increased	O
marginal	O
cost	O
than	O
main	B-General_Concept
memory	I-General_Concept
and	O
thus	O
can	O
increase	O
the	O
cost	O
of	O
the	O
overall	O
system	O
.	O
</s>
<s>
Cached	O
data	O
is	O
stored	O
only	O
so	O
long	O
as	O
power	O
is	O
provided	O
to	O
the	O
cache	B-General_Concept
.	O
</s>
<s>
Benefits	O
may	O
be	O
minimized	O
or	O
eliminated	O
in	O
the	O
case	O
of	O
a	O
large	O
programs	O
with	O
poor	O
temporal	B-General_Concept
locality	I-General_Concept
,	O
which	O
frequently	O
access	O
the	O
main	B-General_Concept
memory	I-General_Concept
.	O
</s>
<s>
In	O
a	O
banked	O
cache	B-General_Concept
,	O
the	O
cache	B-General_Concept
is	O
divided	O
into	O
a	O
cache	B-General_Concept
dedicated	O
to	O
instruction	B-Language
storage	O
and	O
a	O
cache	B-General_Concept
dedicated	O
to	O
data	O
.	O
</s>
<s>
In	O
contrast	O
,	O
a	O
unified	O
cache	B-General_Concept
contains	O
both	O
the	O
instructions	O
and	O
data	O
in	O
the	O
same	O
cache	B-General_Concept
.	O
</s>
<s>
During	O
a	O
process	O
,	O
the	O
L1	O
cache	B-General_Concept
(	O
or	O
most	O
upper-level	O
cache	B-General_Concept
in	O
relation	O
to	O
its	O
connection	O
to	O
the	O
processor	O
)	O
is	O
accessed	O
by	O
the	O
processor	O
to	O
retrieve	O
both	O
instructions	O
and	O
data	O
.	O
</s>
<s>
Requiring	O
both	O
actions	O
to	O
be	O
implemented	O
at	O
the	O
same	O
time	O
requires	O
multiple	O
ports	O
and	O
more	O
access	O
time	O
in	O
a	O
unified	O
cache	B-General_Concept
.	O
</s>
<s>
Having	O
multiple	O
ports	O
requires	O
additional	O
hardware	O
and	O
wiring	O
,	O
leading	O
to	O
a	O
significant	O
structure	O
between	O
the	O
caches	B-General_Concept
and	O
processing	O
units	O
.	O
</s>
<s>
To	O
avoid	O
this	O
,	O
the	O
L1	O
cache	B-General_Concept
is	O
often	O
organized	O
as	O
a	O
banked	O
cache	B-General_Concept
which	O
results	O
in	O
fewer	O
ports	O
,	O
less	O
hardware	O
,	O
and	O
generally	O
lower	O
access	O
times	O
.	O
</s>
<s>
Modern	O
processors	O
have	O
split	O
caches	B-General_Concept
,	O
and	O
in	O
systems	O
with	O
multilevel	O
caches	B-General_Concept
higher	O
level	O
caches	B-General_Concept
may	O
be	O
unified	O
while	O
lower	O
levels	O
split	O
.	O
</s>
<s>
Whether	O
a	O
block	O
present	O
in	O
the	O
upper	O
cache	B-General_Concept
layer	O
can	O
also	O
be	O
present	O
in	O
the	O
lower	O
cache	B-General_Concept
level	O
is	O
governed	O
by	O
the	O
memory	O
system	O
's	O
inclusion	O
policy	O
,	O
which	O
may	O
be	O
inclusive	O
,	O
exclusive	O
or	O
non-inclusive	O
non-exclusive	O
(	O
NINE	O
)	O
.	O
</s>
<s>
With	O
an	O
inclusive	O
policy	O
,	O
all	O
the	O
blocks	O
present	O
in	O
the	O
upper-level	O
cache	B-General_Concept
have	O
to	O
be	O
present	O
in	O
the	O
lower-level	O
cache	B-General_Concept
as	O
well	O
.	O
</s>
<s>
Each	O
upper-level	O
cache	B-General_Concept
component	O
is	O
a	O
subset	O
of	O
the	O
lower-level	O
cache	B-General_Concept
component	O
.	O
</s>
<s>
Under	O
an	O
exclusive	O
policy	O
,	O
all	O
the	O
cache	B-General_Concept
hierarchy	I-General_Concept
components	O
are	O
completely	O
exclusive	O
,	O
so	O
that	O
any	O
element	O
in	O
the	O
upper-level	O
cache	B-General_Concept
will	O
not	O
be	O
present	O
in	O
any	O
of	O
the	O
lower	O
cache	B-General_Concept
components	O
.	O
</s>
<s>
This	O
enables	O
complete	O
usage	O
of	O
the	O
cache	B-General_Concept
memory	I-General_Concept
.	O
</s>
<s>
This	O
means	O
that	O
the	O
upper-level	O
cache	B-General_Concept
may	O
or	O
may	O
not	O
be	O
present	O
in	O
the	O
lower-level	O
cache	B-General_Concept
.	O
</s>
<s>
There	O
are	O
two	O
policies	O
which	O
define	O
the	O
way	O
in	O
which	O
a	O
modified	O
cache	B-General_Concept
block	I-General_Concept
will	O
be	O
updated	O
in	O
the	O
main	B-General_Concept
memory	I-General_Concept
:	O
write	O
through	O
and	O
write	O
back	O
.	O
</s>
<s>
In	O
the	O
case	O
of	O
write	O
through	O
policy	O
,	O
whenever	O
the	O
value	O
of	O
the	O
cache	B-General_Concept
block	I-General_Concept
changes	O
,	O
it	O
is	O
further	O
modified	O
in	O
the	O
lower-level	O
memory	B-General_Concept
hierarchy	I-General_Concept
as	O
well	O
.	O
</s>
<s>
However	O
,	O
in	O
the	O
case	O
of	O
the	O
write	O
back	O
policy	O
,	O
the	O
changed	O
cache	B-General_Concept
block	I-General_Concept
will	O
be	O
updated	O
in	O
the	O
lower-level	O
hierarchy	O
only	O
when	O
the	O
cache	B-General_Concept
block	I-General_Concept
is	O
evicted	O
.	O
</s>
<s>
A	O
"	O
dirty	O
bit	O
"	O
is	O
attached	O
to	O
each	O
cache	B-General_Concept
block	I-General_Concept
and	O
set	O
whenever	O
the	O
cache	B-General_Concept
block	I-General_Concept
is	O
modified	O
.	O
</s>
<s>
Under	O
this	O
policy	O
,	O
there	O
is	O
a	O
risk	O
for	O
data-loss	O
as	O
the	O
most	O
recently	O
changed	O
copy	O
of	O
a	O
datum	O
is	O
only	O
stored	O
in	O
the	O
cache	B-General_Concept
and	O
therefore	O
some	O
corrective	O
techniques	O
must	O
be	O
observed	O
.	O
</s>
<s>
In	O
case	O
of	O
a	O
write	O
where	O
the	O
byte	O
is	O
not	O
present	O
in	O
the	O
cache	B-General_Concept
block	I-General_Concept
,	O
the	O
byte	O
may	O
be	O
brought	O
to	O
the	O
cache	B-General_Concept
as	O
determined	O
by	O
a	O
write	O
allocate	O
or	O
write	O
no-allocate	O
policy	O
.	O
</s>
<s>
Write	O
allocate	O
policy	O
states	O
that	O
in	O
case	O
of	O
a	O
write	O
miss	O
,	O
the	O
block	O
is	O
fetched	O
from	O
the	O
main	B-General_Concept
memory	I-General_Concept
and	O
placed	O
in	O
the	O
cache	B-General_Concept
before	O
writing	O
.	O
</s>
<s>
In	O
the	O
write	O
no-allocate	O
policy	O
,	O
if	O
the	O
block	O
is	O
missed	O
in	O
the	O
cache	B-General_Concept
it	O
will	O
write	O
in	O
the	O
lower-level	O
memory	B-General_Concept
hierarchy	I-General_Concept
without	O
fetching	O
the	O
block	O
into	O
the	O
cache	B-General_Concept
.	O
</s>
<s>
A	O
private	O
cache	B-General_Concept
is	O
assigned	O
to	O
one	O
particular	O
core	O
in	O
a	O
processor	O
,	O
and	O
cannot	O
be	O
accessed	O
by	O
any	O
other	O
cores	O
.	O
</s>
<s>
In	O
some	O
architectures	O
,	O
each	O
core	O
has	O
its	O
own	O
private	O
cache	B-General_Concept
;	O
this	O
creates	O
the	O
risk	O
of	O
duplicate	O
blocks	O
in	O
a	O
system	O
's	O
cache	B-General_Concept
architecture	O
,	O
which	O
results	O
in	O
reduced	O
capacity	O
utilization	O
.	O
</s>
<s>
However	O
,	O
this	O
type	O
of	O
design	O
choice	O
in	O
a	O
multi-layer	O
cache	B-General_Concept
architecture	O
can	O
also	O
be	O
good	O
for	O
a	O
lower	O
data-access	O
latency	O
.	O
</s>
<s>
A	O
shared	B-General_Concept
cache	I-General_Concept
is	O
a	O
cache	B-General_Concept
which	O
can	O
be	O
accessed	O
by	O
multiple	O
cores	O
.	O
</s>
<s>
Since	O
it	O
is	O
shared	O
,	O
each	O
block	O
in	O
the	O
cache	B-General_Concept
is	O
unique	O
and	O
therefore	O
has	O
a	O
larger	O
hit	O
rate	O
as	O
there	O
will	O
be	O
no	O
duplicate	O
blocks	O
.	O
</s>
<s>
However	O
,	O
data-access	O
latency	O
can	O
increase	O
as	O
multiple	O
cores	O
try	O
to	O
access	O
the	O
same	O
cache	B-General_Concept
.	O
</s>
<s>
In	O
multi-core	B-Architecture
processors	I-Architecture
,	O
the	O
design	O
choice	O
to	O
make	O
a	O
cache	B-General_Concept
shared	O
or	O
private	O
impacts	O
the	O
performance	O
of	O
the	O
processor	O
.	O
</s>
<s>
In	O
practice	O
,	O
the	O
upper-level	O
cache	B-General_Concept
L1	O
(	O
or	O
sometimes	O
L2	O
)	O
is	O
implemented	O
as	O
private	O
and	O
lower-level	O
caches	B-General_Concept
are	O
implemented	O
as	O
shared	O
.	O
</s>
<s>
This	O
design	O
provides	O
high	O
access	O
rates	O
for	O
the	O
high-level	O
caches	B-General_Concept
and	O
low	O
miss	O
rates	O
for	O
the	O
lower-level	O
caches	B-General_Concept
.	O
</s>
<s>
L3	O
cache	B-General_Concept
–	O
4	O
MB	O
local	O
&	O
remote	O
per	O
4-core	O
CCX	O
,	O
2	O
CCXs	O
per	O
chiplet	O
,	O
16-way	O
non-inclusive	O
.	O
</s>
<s>
L3	O
cache	B-General_Concept
–	O
16	O
MB	O
local	O
per	O
4-core	O
CCX	O
,	O
2	O
CCXs	O
per	O
chiplet	O
,	O
16-way	O
non-inclusive	O
.	O
</s>
