<s>
In	O
computing	O
,	O
a	O
cache	B-Architecture
control	I-Architecture
instruction	I-Architecture
is	O
a	O
hint	O
embedded	O
in	O
the	O
instruction	B-General_Concept
stream	O
of	O
a	O
processor	O
intended	O
to	O
improve	O
the	O
performance	O
of	O
hardware	O
caches	O
,	O
using	O
foreknowledge	O
of	O
the	O
memory	O
access	O
pattern	O
supplied	O
by	O
the	O
programmer	B-Application
or	O
compiler	B-Language
.	O
</s>
<s>
They	O
may	O
reduce	O
cache	B-General_Concept
pollution	I-General_Concept
,	O
reduce	O
bandwidth	O
requirement	O
,	O
bypass	O
latencies	O
,	O
by	O
providing	O
better	O
control	O
over	O
the	O
working	B-General_Concept
set	I-General_Concept
.	O
</s>
<s>
Most	O
cache	B-Architecture
control	I-Architecture
instructions	I-Architecture
do	O
not	O
affect	O
the	O
semantics	O
of	O
a	O
program	O
,	O
although	O
some	O
can	O
.	O
</s>
<s>
Several	O
such	O
instructions	O
,	O
with	O
variants	O
,	O
are	O
supported	O
by	O
several	O
processor	O
instruction	B-General_Concept
set	I-General_Concept
architectures	I-General_Concept
,	O
such	O
as	O
ARM	B-Architecture
,	O
MIPS	B-Device
,	O
PowerPC	B-Architecture
,	O
and	O
x86	B-Operating_System
.	O
</s>
<s>
This	O
is	O
performed	O
by	O
the	O
PREFETCH	B-General_Concept
instruction	B-General_Concept
in	O
the	O
x86	B-Operating_System
instruction	B-General_Concept
set	I-General_Concept
.	O
</s>
<s>
Some	O
variants	O
bypass	O
higher	O
levels	O
of	O
the	O
cache	B-General_Concept
hierarchy	I-General_Concept
,	O
which	O
is	O
useful	O
in	O
a	O
'	O
streaming	O
 '	O
context	O
for	O
data	O
that	O
is	O
traversed	O
once	O
,	O
rather	O
than	O
held	O
in	O
the	O
working	B-General_Concept
set	I-General_Concept
.	O
</s>
<s>
The	O
prefetch	B-General_Concept
should	O
occur	O
sufficiently	O
far	O
ahead	O
in	O
time	O
to	O
mitigate	O
the	O
latency	O
of	O
memory	O
access	O
,	O
for	O
example	O
in	O
a	O
loop	O
traversing	O
memory	O
linearly	O
.	O
</s>
<s>
The	O
GNU	B-Application
Compiler	I-Application
Collection	I-Application
intrinsic	B-Application
function	I-Application
__builtin_prefetch	O
can	O
be	O
used	O
to	O
invoke	O
this	O
in	O
the	O
programming	O
languages	O
C	B-Language
or	O
C++	B-Language
.	O
</s>
<s>
A	O
variant	O
of	O
prefetch	B-General_Concept
for	O
the	O
instruction	B-General_Concept
cache	O
.	O
</s>
<s>
This	O
saves	O
unneeded	O
main	O
memory	O
bandwidth	O
and	O
cache	B-General_Concept
pollution	I-General_Concept
.	O
</s>
<s>
It	O
is	O
used	O
when	O
it	O
is	O
known	O
that	O
data	O
is	O
no	O
longer	O
part	O
of	O
the	O
working	B-General_Concept
set	I-General_Concept
.	O
</s>
<s>
An	O
example	O
is	O
load	O
last	O
in	O
the	O
PowerPC	B-Architecture
instruction	B-General_Concept
set	I-General_Concept
,	O
which	O
suggests	O
that	O
data	O
will	O
only	O
be	O
used	O
once	O
,	O
i.e.	O
,	O
the	O
cache	O
line	O
in	O
question	O
may	O
be	O
pushed	O
to	O
the	O
head	O
of	O
the	O
eviction	O
queue	O
,	O
whilst	O
keeping	O
it	O
in	O
use	O
if	O
still	O
directly	O
needed	O
.	O
</s>
<s>
In	O
recent	O
times	O
,	O
cache	B-Architecture
control	I-Architecture
instructions	I-Architecture
have	O
become	O
less	O
popular	O
as	O
increasingly	O
advanced	O
application	O
processor	O
designs	O
from	O
Intel	O
and	O
ARM	B-Architecture
devote	O
more	O
transistors	O
to	O
accelerating	O
code	O
written	O
in	O
traditional	O
languages	O
,	O
e.g.	O
,	O
performing	O
automatic	O
prefetch	B-General_Concept
,	O
with	O
hardware	O
to	O
detect	O
linear	O
access	O
patterns	O
on	O
the	O
fly	O
.	O
</s>
<s>
Some	O
processors	O
support	O
scratchpad	B-General_Concept
memory	I-General_Concept
into	O
which	O
temporaries	O
may	O
be	O
put	O
,	O
and	O
direct	B-General_Concept
memory	I-General_Concept
access	I-General_Concept
(	O
DMA	O
)	O
to	O
transfer	O
data	O
to	O
and	O
from	O
main	O
memory	O
when	O
needed	O
.	O
</s>
<s>
This	O
approach	O
is	O
used	O
by	O
the	O
Cell	B-General_Concept
processor	I-General_Concept
,	O
and	O
some	O
embedded	B-Architecture
systems	I-Architecture
.	O
</s>
<s>
These	O
allow	O
greater	O
control	O
over	O
memory	O
traffic	O
and	O
locality	O
(	O
as	O
the	O
working	B-General_Concept
set	I-General_Concept
is	O
managed	O
by	O
explicit	O
transfers	O
)	O
,	O
and	O
eliminates	O
the	O
need	O
for	O
expensive	O
cache	B-General_Concept
coherency	I-General_Concept
in	O
a	O
manycore	B-General_Concept
machine	O
.	O
</s>
<s>
It	O
is	O
very	O
hard	O
to	O
adapt	O
programs	O
written	O
in	O
traditional	O
languages	O
such	O
as	O
C	B-Language
and	O
C++	B-Language
which	O
present	O
the	O
programmer	B-Application
with	O
a	O
uniform	O
view	O
of	O
a	O
large	O
address	O
space	O
(	O
which	O
is	O
an	O
illusion	O
simulated	O
by	O
caches	O
)	O
.	O
</s>
<s>
A	O
traditional	O
microprocessor	O
can	O
more	O
easily	O
run	O
legacy	O
code	O
,	O
which	O
may	O
then	O
be	O
accelerated	O
by	O
cache	B-Architecture
control	I-Architecture
instructions	I-Architecture
,	O
whilst	O
a	O
scratchpad	B-General_Concept
based	O
machine	O
requires	O
dedicated	O
coding	O
from	O
the	O
ground	O
up	O
to	O
even	O
function	O
.	O
</s>
<s>
Cache	B-Architecture
control	I-Architecture
instructions	I-Architecture
are	O
specific	O
to	O
a	O
certain	O
cache	O
line	O
size	O
,	O
which	O
in	O
practice	O
may	O
vary	O
between	O
generations	O
of	O
processors	O
in	O
the	O
same	O
architectural	O
family	O
.	O
</s>
<s>
Caches	O
may	O
also	O
help	O
coalescing	O
reads	O
and	O
writes	O
from	O
less	O
predictable	O
access	O
patterns	O
(	O
e.g.	O
,	O
during	O
texture	O
mapping	O
)	O
,	O
whilst	O
scratchpad	B-General_Concept
DMA	O
requires	O
reworking	O
algorithms	O
for	O
more	O
predictable	O
'	O
linear	O
 '	O
traversals	O
.	O
</s>
<s>
As	O
such	O
scratchpads	B-General_Concept
are	O
generally	O
harder	O
to	O
use	O
with	O
traditional	O
programming	O
models	O
,	O
although	O
dataflow	B-Application
models	O
(	O
such	O
as	O
TensorFlow	B-Language
)	O
might	O
be	O
more	O
suitable	O
.	O
</s>
<s>
Vector	B-Operating_System
processors	I-Operating_System
(	O
for	O
example	O
modern	O
graphics	B-Architecture
processing	I-Architecture
unit	I-Architecture
(	O
GPUs	B-Architecture
)	O
and	O
Xeon	B-General_Concept
Phi	I-General_Concept
)	O
use	O
massive	O
parallelism	B-Operating_System
to	O
achieve	O
high	O
throughput	O
whilst	O
working	O
around	O
memory	O
latency	O
(	O
reducing	O
the	O
need	O
for	O
prefetching	O
)	O
.	O
</s>
<s>
Many	O
read	O
operations	O
are	O
issued	O
in	O
parallel	O
,	O
for	O
subsequent	O
invocations	O
of	O
a	O
compute	B-Operating_System
kernel	I-Operating_System
;	O
calculations	O
may	O
be	O
put	O
on	O
hold	O
awaiting	O
future	O
data	O
,	O
whilst	O
the	O
execution	O
units	O
are	O
devoted	O
to	O
working	O
on	O
data	O
from	O
past	O
requests	O
data	O
that	O
has	O
already	O
turned	O
up	O
.	O
</s>
<s>
This	O
is	O
easier	O
for	O
programmers	B-Application
to	O
leverage	O
in	O
conjunction	O
with	O
the	O
appropriate	O
programming	O
models	O
(	O
compute	B-Operating_System
kernels	I-Operating_System
)	O
,	O
but	O
harder	O
to	O
apply	O
to	O
general	O
purpose	O
programming	O
.	O
</s>
