<s>
The	O
CVAX	B-Device
is	O
a	O
microprocessor	B-Architecture
chipset	O
developed	O
and	O
fabricated	O
by	O
Digital	O
Equipment	O
Corporation	O
(	O
DEC	O
)	O
that	O
implemented	O
the	O
VAX	B-Device
instruction	B-General_Concept
set	I-General_Concept
architecture	I-General_Concept
(	O
ISA	O
)	O
.	O
</s>
<s>
The	O
chipset	O
consisted	O
of	O
the	O
CVAX	B-Device
78034	O
CPU	O
,	O
CFPA	O
floating-point	O
accelerator	O
,	O
CVAX	B-Device
clock	O
chip	O
,	O
and	O
the	O
associated	O
support	O
chips	O
,	O
the	O
CVAX	B-Device
System	O
Support	O
Chip	O
(	O
CSSC	O
)	O
,	O
CVAX	B-Device
Memory	O
Controller	O
(	O
CMCTL	O
)	O
,	O
and	O
CVAX	B-Device
Q-Bus	O
Interface	O
Chip	O
(	O
CQBIC	O
)	O
.	O
</s>
<s>
The	O
CVAX	B-Device
78034	O
,	O
also	O
known	O
as	O
the	O
MicroVAX	B-Device
78034	O
,	O
is	O
a	O
second-generation	O
single-chip	O
VAX	B-Device
microprocessor	B-Architecture
.	O
</s>
<s>
Systems	O
featuring	O
the	O
CVAX	B-Device
chip	O
set	O
became	O
available	O
in	O
late	O
1987	O
.	O
</s>
<s>
It	O
is	O
clocked	O
at	O
frequencies	O
of	O
12.5MHz	O
(	O
80	O
ns	O
)	O
in	O
higher-end	O
systems	O
such	O
as	O
the	O
VAX	B-Device
6000	I-Device
Model	I-Device
200	I-Device
and	O
at	O
11.11MHz	O
(	O
90	O
ns	O
)	O
in	O
lower-end	O
systems	O
such	O
as	O
the	O
MicroVAX	B-Device
3500	I-Device
and	I-Device
3600	I-Device
.	O
</s>
<s>
The	O
78034	O
was	O
the	O
first	O
VAX	B-Device
microprocessor	B-Architecture
to	O
have	O
internal	O
caches	O
,	O
a	O
1	O
KB	O
combined	O
instruction	O
and	O
data	O
stream	O
cache	O
.	O
</s>
<s>
The	O
cache	O
is	O
quite	O
unusual	O
as	O
it	O
is	O
implemented	O
with	O
one-transistor	O
DRAM	O
,	O
whereas	O
the	O
majority	O
of	O
microprocessors	B-Architecture
use	O
SRAM	O
for	O
their	O
internal	O
caches	O
.	O
</s>
<s>
This	O
was	O
the	O
first	O
microprocessor	B-Architecture
to	O
use	O
one-transistor	O
DRAM	O
for	O
cache	O
.	O
</s>
<s>
The	O
microprocessor	B-Architecture
is	O
microprogrammed	O
and	O
partially	O
pipelined	O
and	O
consists	O
of	O
six	O
major	O
functional	O
units	O
,	O
the	O
I-Box	O
,	O
E-Box	O
,	O
M-box	O
,	O
bus	O
interface	O
unit	O
(	O
BIU	O
)	O
,	O
cache	O
,	O
and	O
control	O
store	O
and	O
microsequencer	O
.	O
</s>
<s>
The	O
I-Box	O
fetches	O
VAX	B-Device
instructions	O
from	O
the	O
cache	O
and	O
decodes	O
them	O
(	O
parses	O
)	O
into	O
macroinstructions	O
.	O
</s>
<s>
The	O
M-Box	O
works	O
closely	O
with	O
the	O
BIU	O
,	O
which	O
controls	O
access	O
to	O
the	O
internal	O
cache	O
and	O
interfaces	O
the	O
microprocessor	B-Architecture
to	O
the	O
32-bit	O
address	O
data	O
multiplexed	O
external	O
bus	O
.	O
</s>
<s>
Unlike	O
the	O
MicroVAX	B-Device
78032	O
,	O
which	O
uses	O
X-shaped	O
cells	O
,	O
the	O
78034	O
uses	O
conventional	O
H-shaped	O
cells	O
.	O
</s>
<s>
The	O
CFPA	O
(	O
CVAX	B-Device
Floating	O
Point	O
Accelerator	O
)	O
is	O
a	O
floating	O
point	O
coprocessor	O
for	O
the	O
CVAX	B-Device
78034	O
.	O
</s>
<s>
CVAX+	B-Device
referred	O
to	O
an	O
optical	O
shrink	O
of	O
the	O
original	O
CVAX	B-Device
fabricated	O
in	O
DEC	O
's	O
second-generation	O
CMOS	O
process	O
,	O
CMOS-2	O
,	O
a	O
1.5μm	O
process	O
with	O
two	O
levels	O
of	O
wiring	O
.	O
</s>
<s>
The	O
original	O
design	O
team	O
shrunk	O
the	O
CVAX	B-Device
78034	O
,	O
CFPA	O
and	O
CMCTL	O
,	O
with	O
the	O
other	O
chips	O
left	O
unchanged	O
.	O
</s>
<s>
The	O
shrunk	O
78034	O
was	O
known	O
as	O
the	O
CVAX-60	O
,	O
which	O
taped	O
out	O
in	O
August	O
1987	O
,	O
before	O
the	O
original	O
78034	O
begun	O
volume	O
production	O
,	O
and	O
the	O
CFPA-60	O
taped	O
out	O
in	O
November	O
1987	O
.	O
</s>
<s>
The	O
CVAX+	B-Device
operated	O
at	O
16.67MHz	O
,	O
but	O
power	O
requirements	O
was	O
unchanged	O
.	O
</s>
<s>
The	O
CVAX+	B-Device
started	O
to	O
ship	O
in	O
late	O
1988	O
,	O
as	O
upgrades	O
to	O
all	O
entry-level	O
CVAX-based	O
systems	O
and	O
were	O
also	O
provided	O
as	O
an	O
upgrade	O
to	O
the	O
VAX	B-Device
6000	I-Device
when	O
the	O
introduction	O
of	O
Rigel	B-Device
was	O
delayed	O
by	O
yield	O
issues	O
.	O
</s>
<s>
SOC	O
referred	O
to	O
a	O
microprocessor	B-Architecture
which	O
contained	O
the	O
CVAX	B-Device
78034	O
,	O
CFPA	O
,	O
clock	O
chip	O
,	O
and	O
an	O
8	O
KB	O
second	O
level	O
cache	O
on	O
a	O
single	O
die	O
.	O
</s>
<s>
Operating	O
at	O
25	O
or	O
28.5MHz	O
,	O
it	O
was	O
introduced	O
in	O
1990	O
and	O
used	O
in	O
entry-level	O
servers	O
,	O
workstations	O
,	O
VXT-2000	O
X	O
terminals	O
,	O
and	O
as	O
an	O
embedded	B-Architecture
microprocessor	I-Architecture
in	O
DEC	O
's	O
high-end	O
printers	O
and	O
terminals	O
.	O
</s>
