<s>
In	O
the	O
x86	B-Operating_System
architecture	I-Operating_System
,	O
the	O
CPUID	B-Architecture
instruction	O
(	O
identified	O
by	O
a	O
CPUID	B-Architecture
opcode	B-Language
)	O
is	O
a	O
processor	B-General_Concept
supplementary	I-General_Concept
instruction	I-General_Concept
(	O
its	O
name	O
derived	O
from	O
CPU	B-General_Concept
Identification	O
)	O
allowing	O
software	O
to	O
discover	O
details	O
of	O
the	O
processor	O
.	O
</s>
<s>
It	O
was	O
introduced	O
by	O
Intel	O
in	O
1993	O
with	O
the	O
launch	O
of	O
the	O
Pentium	B-General_Concept
and	O
SL-enhanced	O
486	B-General_Concept
processors	I-General_Concept
.	O
</s>
<s>
A	O
program	O
can	O
use	O
the	O
CPUID	B-Architecture
to	O
determine	O
processor	O
type	O
and	O
whether	O
features	O
such	O
as	O
MMX/SSE	O
are	O
implemented	O
.	O
</s>
<s>
Prior	O
to	O
the	O
general	O
availability	O
of	O
the	O
CPUID	B-Architecture
instruction	O
,	O
programmers	O
would	O
write	O
esoteric	O
machine	B-Language
code	I-Language
which	O
exploited	O
minor	O
differences	O
in	O
CPU	B-General_Concept
behavior	O
in	O
order	O
to	O
determine	O
the	O
processor	O
make	O
and	O
model	O
.	O
</s>
<s>
Outside	O
the	O
x86	B-Operating_System
family	O
,	O
developers	O
are	O
mostly	O
still	O
required	O
to	O
use	O
esoteric	O
processes	O
(	O
involving	O
instruction	O
timing	O
or	O
CPU	B-General_Concept
fault	O
triggers	O
)	O
to	O
determine	O
the	O
variations	O
in	O
CPU	B-General_Concept
design	O
that	O
are	O
present	O
.	O
</s>
<s>
In	O
the	O
Motorola	O
680x0	O
family	O
—	O
that	O
never	O
had	O
a	O
CPUID	B-Architecture
instruction	O
of	O
any	O
kind	O
—	O
certain	O
specific	O
instructions	O
required	O
elevated	O
privileges	O
.	O
</s>
<s>
These	O
could	O
be	O
used	O
to	O
tell	O
various	O
CPU	B-General_Concept
family	O
members	O
apart	O
.	O
</s>
<s>
In	O
the	O
Motorola	B-Device
68010	I-Device
the	O
instruction	O
MOVE	O
from	O
SR	O
became	O
privileged	O
.	O
</s>
<s>
This	O
notable	O
instruction	O
(	O
and	O
state	O
machine	O
)	O
change	O
allowed	O
the	O
68010	B-Device
to	O
meet	O
the	O
Popek	B-Architecture
and	I-Architecture
Goldberg	I-Architecture
virtualization	I-Architecture
requirements	I-Architecture
.	O
</s>
<s>
Because	O
the	O
68000	O
offered	O
an	O
unprivileged	O
MOVE	O
from	O
SR	O
the	O
2	O
different	O
CPUs	O
could	O
be	O
told	O
apart	O
by	O
a	O
CPU	B-General_Concept
error	O
condition	O
being	O
triggered	O
.	O
</s>
<s>
While	O
the	O
CPUID	B-Architecture
instruction	O
is	O
specific	O
to	O
the	O
x86	B-Operating_System
architecture	I-Operating_System
,	O
other	O
architectures	O
(	O
like	O
ARM	O
)	O
often	O
provide	O
on-chip	O
registers	O
which	O
can	O
be	O
read	O
in	O
prescribed	O
ways	O
to	O
obtain	O
the	O
same	O
sorts	O
of	O
information	O
provided	O
by	O
the	O
x86	B-Operating_System
CPUID	B-Architecture
instruction	O
.	O
</s>
<s>
The	O
CPUID	B-Architecture
opcode	B-Language
is	O
0F	O
A2	O
.	O
</s>
<s>
In	O
assembly	B-Language
language	I-Language
,	O
the	O
CPUID	B-Architecture
instruction	O
takes	O
no	O
parameters	O
as	O
CPUID	B-Architecture
implicitly	O
uses	O
the	O
EAX	O
register	O
to	O
determine	O
the	O
main	O
category	O
of	O
information	O
returned	O
.	O
</s>
<s>
In	O
Intel	O
's	O
more	O
recent	O
terminology	O
,	O
this	O
is	O
called	O
the	O
CPUID	B-Architecture
leaf	O
.	O
</s>
<s>
CPUID	B-Architecture
should	O
be	O
called	O
with	O
EAX	O
=	O
0	O
first	O
,	O
as	O
this	O
will	O
store	O
in	O
the	O
EAX	O
register	O
the	O
highest	O
EAX	O
calling	O
parameter	O
(	O
leaf	O
)	O
that	O
the	O
CPU	B-General_Concept
implements	O
.	O
</s>
<s>
To	O
obtain	O
extended	O
function	O
information	O
CPUID	B-Architecture
should	O
be	O
called	O
with	O
the	O
most	O
significant	O
bit	O
of	O
EAX	O
set	O
.	O
</s>
<s>
To	O
determine	O
the	O
highest	O
extended	O
function	O
calling	O
parameter	O
,	O
call	O
CPUID	B-Architecture
with	O
EAX	O
=	O
80000000h	O
.	O
</s>
<s>
CPUID	B-Architecture
leaves	O
greater	O
than	O
3	O
but	O
less	O
than	O
80000000	O
are	O
accessible	O
only	O
when	O
the	O
model-specific	B-General_Concept
registers	I-General_Concept
have	O
IA32_MISC_ENABLE.BOOT_NT4	O
[	O
bit	O
22 ]	O
=	O
0	O
(	O
which	O
is	O
so	O
by	O
default	O
)	O
.	O
</s>
<s>
As	O
the	O
name	O
suggests	O
,	O
Windows	B-Device
NT	I-Device
4.0	I-Device
until	O
SP6	O
did	O
not	O
boot	O
properly	O
unless	O
this	O
bit	O
was	O
set	O
,	O
but	O
later	O
versions	O
of	O
Windows	O
do	O
not	O
need	O
it	O
,	O
so	O
basic	O
leaves	O
greater	O
than	O
4	O
can	O
be	O
assumed	O
visible	O
on	O
current	O
Windows	O
systems	O
.	O
</s>
<s>
Some	O
of	O
the	O
more	O
recently	O
added	O
leaves	O
also	O
have	O
sub-leaves	O
,	O
which	O
are	O
selected	O
via	O
the	O
ECX	O
register	O
before	O
calling	O
CPUID	B-Architecture
.	O
</s>
<s>
This	O
returns	O
the	O
CPU	B-General_Concept
's	O
manufacturer	O
ID	O
string	O
a	O
twelve-character	O
ASCII	B-Protocol
string	O
stored	O
in	O
EBX	O
,	O
EDX	O
,	O
ECX	O
(	O
in	O
that	O
order	O
)	O
.	O
</s>
<s>
The	O
highest	O
basic	O
calling	O
parameter	O
(	O
the	O
largest	O
value	O
that	O
EAX	O
can	O
be	O
set	O
to	O
before	O
calling	O
CPUID	B-Architecture
)	O
is	O
returned	O
in	O
EAX	O
.	O
</s>
<s>
+	O
Highest	O
Function	O
Parameter	O
Processors	O
Basic	O
Extended	O
Earlier	O
Intel	B-General_Concept
486	I-General_Concept
CPUID	B-Architecture
Not	O
Implemented	O
Later	O
Intel	B-General_Concept
486	I-General_Concept
and	O
Pentium	B-General_Concept
0x01	O
Not	O
Implemented	O
Pentium	B-Device
Pro	I-Device
,	O
Pentium	B-General_Concept
II	I-General_Concept
and	O
Celeron	B-Device
0x02	O
Not	O
Implemented	O
Pentium	B-General_Concept
III	I-General_Concept
0x03	O
Not	O
Implemented	O
Pentium	B-General_Concept
4	I-General_Concept
0x02	O
0x8000	O
0004	O
Xeon	B-Device
0x02	O
0x8000	O
0004	O
Pentium	B-Architecture
M	I-Architecture
0x02	O
0x8000	O
0004	O
Pentium	B-General_Concept
4	I-General_Concept
with	O
Hyper-Threading	B-Operating_System
0x05	O
0x8000	O
0008	O
Pentium	B-Device
D	I-Device
(	O
8xx	O
)	O
0x05	O
0x8000	O
0008	O
Pentium	B-Device
D	I-Device
(	O
9xx	O
)	O
0x06	O
0x8000	O
0008	O
Core	O
Duo	O
0x0A	O
0x8000	O
0008	O
Core	O
2	O
Duo	O
0x0A	O
0x8000	O
0008	O
Xeon	B-Device
3000	O
,	O
5100	O
,	O
5200	O
,	O
5300	O
,	O
5400	O
(	O
5000	O
series	O
)	O
0x0A	O
0x8000	O
0008	O
Core	O
2	O
Duo	O
8000	O
series	O
0x0D	O
0x8000	O
0008	O
Xeon	B-Device
5200	O
,	O
5400	O
series	O
0x0A	O
0x8000	O
0008	O
Atom	B-Device
0x0A	O
0x8000	O
0008	O
Nehalem-based	O
processors	O
0x0B	O
0x8000	O
0008Ivy	O
Bridge-based	O
processors0x0D0x8000	O
0008Skylake-based	O
processors	O
(	O
proc	O
base	O
&	O
max	O
freq	O
;	O
Bus	O
ref	O
.	O
</s>
<s>
The	O
following	O
are	O
ID	O
strings	O
used	O
by	O
open	O
source	O
soft	B-Device
CPU	I-Device
cores	I-Device
:	O
</s>
<s>
The	O
following	O
example	O
code	O
displays	O
the	O
vendor	O
ID	O
string	O
as	O
well	O
as	O
the	O
highest	O
calling	O
parameter	O
that	O
the	O
CPU	B-General_Concept
implements	O
.	O
</s>
<s>
This	O
returns	O
the	O
CPU	B-General_Concept
's	O
stepping	B-General_Concept
,	O
model	O
,	O
and	O
family	O
information	O
in	O
register	O
EAX	O
(	O
also	O
called	O
the	O
signature	O
of	O
a	O
CPU	B-General_Concept
)	O
,	O
feature	O
flags	O
in	O
registers	O
EDX	O
and	O
ECX	O
,	O
and	O
additional	O
feature	O
info	O
in	O
register	O
EBX	O
.	O
</s>
<s>
Stepping	B-General_Concept
ID	O
is	O
a	O
product	O
revision	O
number	O
assigned	O
due	O
to	O
fixed	O
errata	O
or	O
other	O
changes	O
.	O
</s>
<s>
CPUID.01.EDX.CLFSH	O
[	O
bit	O
19 ]	O
=	O
123:16Maximum	O
number	O
of	O
addressable	O
IDs	O
for	O
logical	O
processors	O
in	O
this	O
physical	O
package	O
;	O
</s>
<s>
The	O
nearest	O
power-of-2	O
integer	O
that	O
is	O
not	O
smaller	O
than	O
this	O
value	O
is	O
the	O
number	O
of	O
unique	O
initial	O
APIC	B-Device
IDs	O
reserved	O
for	O
addressing	O
different	O
logical	O
processors	O
in	O
a	O
physical	O
package	O
.	O
</s>
<s>
Former	O
use	O
:	O
Number	O
of	O
logical	O
processors	O
per	O
physical	O
processor	O
;	O
two	O
for	O
the	O
Pentium	B-General_Concept
4	I-General_Concept
processor	O
with	O
Hyper-Threading	B-Operating_System
Technology.http://bochs.sourceforge.net/techspec/24161821.pdf	O
if	O
Hyper-threading	B-Operating_System
feature	O
flag	O
is	O
set	O
.	O
</s>
<s>
CPUID.01.EDX.HTT	O
[	O
bit	O
28 ]	O
=	O
131:24Local	O
APIC	B-Device
ID	O
:	O
The	O
initial	O
APIC-ID	O
is	O
used	O
to	O
identify	O
the	O
executing	O
logical	O
processor	O
.	O
</s>
<s>
It	O
can	O
also	O
be	O
identified	O
via	O
the	O
cpuid	B-Architecture
0BH	O
leaf	O
(	O
CPUID.0Bh.EDX[x2APIC-ID]	O
)	O
.Pentium	O
4	O
and	O
subsequent	O
processors	O
.	O
</s>
<s>
+	O
Feature	O
Information	O
Bit	O
EDX	O
ECX	O
Short	O
Feature	O
Short	O
Feature	O
0	O
fpu	O
Onboard	O
x87	B-Application
FPU	I-Application
sse3	B-General_Concept
Prescott	O
New	O
Instructions-SSE3	O
(	O
PNI	O
)	O
1	O
vme	O
Virtual	O
8086	O
mode	O
extensions	O
(	O
such	O
as	O
VIF	O
,	O
VIP	O
,	O
PIV	O
)	O
pclmulqdq	B-Device
PCLMULQDQ	B-Device
2	O
de	O
Debugging	O
extensions	O
(	O
CR4	O
bit	O
3	O
)	O
dtes64	O
64-bit	O
debug	O
store	O
(	O
edx	O
bit	O
21	O
)	O
3	O
pse	O
Page	B-General_Concept
Size	I-General_Concept
Extension	I-General_Concept
monitor	O
MONITOR	O
and	O
MWAIT	O
instructions	O
(	O
SSE3	B-General_Concept
)	O
4	O
tsc	O
Time	B-Device
Stamp	I-Device
Counter	I-Device
ds-cpl	O
CPL	O
qualified	O
debug	O
store	O
5	O
msr	O
Model-specific	B-General_Concept
registers	I-General_Concept
vmx	O
Virtual	B-General_Concept
Machine	I-General_Concept
eXtensions	I-General_Concept
6	O
pae	O
Physical	B-General_Concept
Address	I-General_Concept
Extension	I-General_Concept
smx	O
Safer	B-Device
Mode	I-Device
Extensions	I-Device
(	O
LaGrande	B-Device
)	O
7	O
mce	O
Machine	B-Device
Check	I-Device
Exception	I-Device
est	O
Enhanced	O
SpeedStep	B-Device
8	O
cx8	O
CMPXCHG8	O
(	O
compare-and-swap	B-Operating_System
)	O
instruction	O
tm2	B-Device
Thermal	B-Device
Monitor	I-Device
2	I-Device
9	O
apic	B-Device
Onboard	O
Advanced	B-Device
Programmable	I-Device
Interrupt	I-Device
Controller	I-Device
ssse3	B-General_Concept
Supplemental	B-General_Concept
SSE3	I-General_Concept
instructions	O
10	O
(	O
reserved	O
)	O
cnxt-id	O
L1	O
Context	O
ID	O
11	O
sep	O
SYSENTER	O
and	O
SYSEXIT	O
instructions	O
sdbg	O
Silicon	O
Debug	O
interface	O
12	O
mtrr	O
Memory	B-General_Concept
Type	I-General_Concept
Range	I-General_Concept
Registers	I-General_Concept
fma	O
Fused	B-General_Concept
multiply-add	I-General_Concept
(	O
FMA3	B-General_Concept
)	O
13	O
pge	O
Page	B-General_Concept
Global	O
Enable	O
bit	O
in	O
CR4	O
cx16	O
CMPXCHG16B	O
instruction	O
14	O
mca	O
Machine	B-Device
check	I-Device
architecture	I-Device
xtpr	O
Can	O
disable	O
sending	O
task	O
priority	O
messages	O
15	O
cmov	O
Conditional	O
move	O
and	O
FCMOV	B-Device
instructions	O
pdcm	O
Perfmon	O
&	O
debug	O
capability	O
16	O
pat	O
Page	B-General_Concept
Attribute	I-General_Concept
Table	I-General_Concept
(	O
reserved	O
)	O
17	O
pse-36	B-General_Concept
36-bit	B-General_Concept
page	I-General_Concept
size	I-General_Concept
extension	I-General_Concept
pcid	O
Process	O
context	O
identifiers	O
(	O
CR4	O
bit	O
17	O
)	O
18	O
psn	O
Processor	O
Serial	O
Number	O
dca	O
Direct	O
cache	O
access	O
for	O
DMA	O
writes	O
19	O
clfsh	O
CLFLUSH	O
instruction	O
(	O
SSE2	B-General_Concept
)	O
sse4.1	O
SSE4.1	O
instructions	O
20	O
(	O
reserved	O
)	O
sse4.2	O
SSE4.2	O
instructions	O
21	O
ds	O
Debug	O
store	O
:	O
save	O
trace	O
of	O
executed	O
jumps	O
x2apic	O
x2APIC	O
22	O
acpi	B-Device
Onboard	O
thermal	O
control	O
MSRs	O
for	O
ACPI	B-Device
movbe	O
MOVBE	O
instruction	O
(	O
big-endian	O
)	O
23	O
mmx	B-Architecture
MMX	B-Architecture
instructions	O
popcnt	O
POPCNT	O
instruction	O
24	O
fxsr	O
FXSAVE	O
,	O
FXRESTOR	O
instructions	O
,	O
CR4	O
bit	O
9	O
tsc-deadline	O
APIC	B-Device
implements	O
one-shot	O
operation	O
using	O
a	O
TSC	O
deadline	O
value	O
25	O
sse	B-General_Concept
SSE	B-General_Concept
instructions	I-General_Concept
(	O
a.k.a.	O
</s>
<s>
This	O
returns	O
a	O
list	O
of	O
descriptors	O
indicating	O
cache	O
and	O
TLB	B-Architecture
capabilities	O
in	O
EAX	O
,	O
EBX	O
,	O
ECX	O
and	O
EDX	O
registers	O
.	O
</s>
<s>
The	O
processor	O
serial	O
number	O
was	O
introduced	O
on	O
Intel	B-General_Concept
Pentium	I-General_Concept
III	I-General_Concept
,	O
but	O
due	O
to	O
privacy	O
concerns	O
,	O
this	O
feature	O
is	O
no	O
longer	O
implemented	O
on	O
later	O
models	O
(	O
the	O
PSN	O
feature	O
bit	O
is	O
always	O
cleared	O
)	O
.	O
</s>
<s>
AMD	O
CPUs	O
however	O
,	O
do	O
not	O
implement	O
this	O
feature	O
in	O
any	O
CPU	B-General_Concept
models	O
.	O
</s>
<s>
For	O
Intel	B-General_Concept
Pentium	I-General_Concept
III	I-General_Concept
CPUs	O
,	O
the	O
serial	O
number	O
is	O
returned	O
in	O
the	O
EDX:ECX	O
registers	O
.	O
</s>
<s>
Note	O
that	O
the	O
processor	O
serial	O
number	O
feature	O
must	O
be	O
enabled	O
in	O
the	O
BIOS	B-Operating_System
setting	O
in	O
order	O
to	O
function	O
.	O
</s>
<s>
These	O
two	O
leaves	O
are	O
used	O
for	O
processor	O
topology	O
(	O
thread	O
,	O
core	O
,	O
package	O
)	O
and	O
cache	O
hierarchy	O
enumeration	O
in	O
Intel	O
multi-core	O
(	O
and	O
hyperthreaded	B-Operating_System
)	O
processors	O
.	O
</s>
<s>
Unlike	O
most	O
other	O
CPUID	B-Architecture
leaves	O
,	O
leaf	O
Bh	O
will	O
return	O
different	O
values	O
in	O
EDX	O
depending	O
on	O
which	O
logical	O
processor	O
the	O
CPUID	B-Architecture
instruction	O
runs	O
;	O
the	O
value	O
returned	O
in	O
EDX	O
is	O
actually	O
the	O
x2APIC	O
id	O
of	O
the	O
logical	O
processor	O
.	O
</s>
<s>
The	O
processor(s )	O
topology	O
exposed	O
by	O
leaf	O
Bh	O
is	O
a	O
hierarchical	O
one	O
,	O
but	O
with	O
the	O
strange	O
caveat	O
that	O
the	O
order	O
of	O
(	O
logical	O
)	O
levels	O
in	O
this	O
hierarchy	O
does	O
n't	O
necessarily	O
correspond	O
to	O
the	O
order	O
in	O
the	O
physical	O
hierarchy	O
(	O
SMT/core/package	O
)	O
.	O
</s>
<s>
However	O
,	O
every	O
logical	O
level	O
can	O
be	O
queried	O
as	O
an	O
ECX	O
subleaf	O
(	O
of	O
the	O
Bh	O
leaf	O
)	O
for	O
its	O
correspondence	O
to	O
a	O
"	O
level	O
type	O
"	O
,	O
which	O
can	O
be	O
either	O
SMT	B-Operating_System
,	O
core	O
,	O
or	O
"	O
invalid	O
"	O
.	O
</s>
<s>
As	O
an	O
example	O
,	O
a	O
dual-core	O
Westmere	B-Device
processor	O
capable	O
of	O
hyperthreading	B-Operating_System
(	O
thus	O
having	O
two	O
cores	O
and	O
four	O
threads	O
in	O
total	O
)	O
could	O
have	O
x2APIC	O
ids	O
0	O
,	O
1	O
,	O
4	O
and	O
5	O
for	O
its	O
four	O
logical	O
processors	O
.	O
</s>
<s>
Leaf	O
Bh	O
(=	O
EAX	O
)	O
,	O
subleaf	O
0	O
(=	O
ECX	O
)	O
of	O
CPUID	B-Architecture
could	O
for	O
instance	O
return	O
100h	O
in	O
ECX	O
,	O
meaning	O
that	O
level	O
0	O
describes	O
the	O
SMT	B-Operating_System
(	O
hyperthreading	B-Operating_System
)	O
layer	O
,	O
and	O
return	O
2	O
in	O
EBX	O
because	O
there	O
are	O
two	O
logical	O
processors	O
(	O
SMT	B-Operating_System
units	O
)	O
per	O
physical	O
core	O
.	O
</s>
<s>
The	O
value	O
returned	O
in	O
EAX	O
for	O
this	O
0-subleaf	O
should	O
be	O
1	O
in	O
this	O
case	O
,	O
because	O
shifting	O
the	O
aforementioned	O
x2APIC	O
ids	O
to	O
the	O
right	O
by	O
one	O
bit	O
gives	O
a	O
unique	O
core	O
number	O
(	O
at	O
the	O
next	O
level	O
of	O
the	O
level	O
id	O
hierarchy	O
)	O
and	O
erases	O
the	O
SMT	B-Operating_System
id	O
bit	O
inside	O
each	O
core	O
.	O
</s>
<s>
A	O
simpler	O
way	O
to	O
interpret	O
this	O
information	O
is	O
that	O
the	O
last	O
bit	O
(	O
bit	O
number	O
0	O
)	O
of	O
the	O
x2APIC	O
id	O
identifies	O
the	O
SMT/hyperthreading	O
unit	O
inside	O
each	O
core	O
in	O
our	O
example	O
.	O
</s>
<s>
Advancing	O
to	O
subleaf	O
1	O
(	O
by	O
making	O
another	O
call	O
to	O
CPUID	B-Architecture
with	O
EAX	O
=	O
Bh	O
and	O
ECX	O
=	O
1	O
)	O
could	O
for	O
instance	O
return	O
201h	O
in	O
ECX	O
,	O
meaning	O
that	O
this	O
is	O
a	O
core-type	O
level	O
,	O
and	O
4	O
in	O
EBX	O
because	O
there	O
are	O
4	O
logical	O
processors	O
in	O
the	O
package	O
;	O
EAX	O
returned	O
could	O
be	O
any	O
value	O
greater	O
than	O
3	O
,	O
because	O
it	O
so	O
happens	O
that	O
bit	O
number	O
2	O
is	O
used	O
to	O
identify	O
the	O
core	O
in	O
the	O
x2APIC	O
id	O
.	O
</s>
<s>
In	O
EAX[31:26]	O
it	O
returns	O
the	O
APIC	B-Device
mask	O
bits	O
reserved	O
for	O
a	O
package	O
;	O
that	O
would	O
be	O
111b	O
in	O
our	O
example	O
because	O
bits	O
0	O
to	O
2	O
are	O
used	O
for	O
identifying	O
logical	O
processors	O
inside	O
this	O
package	O
,	O
but	O
bit	O
1	O
is	O
also	O
reserved	O
although	O
not	O
used	O
as	O
part	O
of	O
the	O
logical	O
processor	O
identification	O
scheme	O
.	O
</s>
<s>
In	O
other	O
words	O
,	O
APIC	B-Device
ids	O
0	O
to	O
7	O
are	O
reserved	O
for	O
the	O
package	O
,	O
even	O
though	O
half	O
of	O
these	O
values	O
do	O
n't	O
map	O
to	O
a	O
logical	O
processor	O
.	O
</s>
<s>
The	O
APIC	B-Device
ids	O
are	O
also	O
used	O
in	O
this	O
hierarchy	O
to	O
convey	O
information	O
about	O
how	O
the	O
different	O
levels	O
of	O
cache	O
are	O
shared	O
by	O
the	O
SMT	B-Operating_System
units	O
and	O
cores	O
.	O
</s>
<s>
To	O
continue	O
our	O
example	O
,	O
the	O
L2	O
cache	O
,	O
which	O
is	O
shared	O
by	O
SMT	B-Operating_System
units	O
of	O
the	O
same	O
core	O
but	O
not	O
between	O
physical	O
cores	O
on	O
the	O
Westmere	B-Device
is	O
indicated	O
by	O
EAX[26:14]	O
being	O
set	O
to	O
1	O
,	O
while	O
the	O
information	O
that	O
the	O
L3	O
cache	O
is	O
shared	O
by	O
the	O
whole	O
package	O
is	O
indicated	O
by	O
setting	O
those	O
bits	O
to	O
(	O
at	O
least	O
)	O
111b	O
.	O
</s>
<s>
Beware	O
that	O
older	O
versions	O
of	O
the	O
Intel	O
app	O
note	O
485	O
contain	O
some	O
misleading	O
information	O
,	O
particularly	O
with	O
respect	O
to	O
identifying	O
and	O
counting	O
cores	O
in	O
a	O
multi-core	O
processor	O
;	O
errors	O
from	O
misinterpreting	O
this	O
information	O
have	O
even	O
been	O
incorporated	O
in	O
the	O
Microsoft	O
sample	O
code	O
for	O
using	O
CPUID	B-Architecture
,	O
even	O
for	O
the	O
2013	O
edition	O
of	O
Visual	O
Studio	O
,	O
and	O
also	O
in	O
the	O
sandpile.org	O
page	B-General_Concept
for	O
CPUID	B-Architecture
,	O
but	O
the	O
Intel	O
code	O
sample	O
for	O
identifying	O
processor	O
topology	O
has	O
the	O
correct	O
interpretation	O
,	O
and	O
the	O
current	O
Intel	O
Software	O
Developer	O
’s	O
Manual	O
has	O
a	O
more	O
clear	O
language	O
.	O
</s>
<s>
Beware	O
that	O
using	O
that	O
older	O
detection	O
method	O
on	O
2010	O
and	O
newer	O
Intel	O
processors	O
may	O
overestimate	O
the	O
number	O
of	O
cores	O
and	O
logical	O
processors	O
because	O
the	O
old	O
detection	O
method	O
assumes	O
there	O
are	O
no	O
gaps	O
in	O
the	O
APIC	B-Device
id	O
space	O
,	O
and	O
this	O
assumption	O
is	O
violated	O
by	O
some	O
newer	O
processors	O
(	O
starting	O
with	O
the	O
Core	O
i3	O
5x0	O
series	O
)	O
,	O
but	O
these	O
newer	O
processors	O
also	O
come	O
with	O
an	O
x2APIC	O
,	O
so	O
their	O
topology	O
can	O
be	O
correctly	O
determined	O
using	O
the	O
EAX	O
=	O
Bh	O
leaf	O
method	O
.	O
</s>
<s>
+	O
EAX	O
=	O
7	O
,	O
ECX	O
=	O
0	O
CPUID	B-Architecture
feature	O
bits	O
Bit	O
EBX	O
ECX	O
EDX	O
Bit	O
Short	O
Feature	O
Short	O
Feature	O
Short	O
Feature	O
0	O
fsgsbase	O
Access	O
to	O
base	O
of	O
%fs	O
and	O
%gs	O
prefetchwt1	O
PREFETCHWT1	O
instruction	O
sgx-keys	O
Attestation	O
Services	O
for	O
Intel	O
SGX	O
0	O
1	O
IA32_TSC_ADJUST	O
MSR	O
avx512-vbmi	O
AVX-512	B-General_Concept
Vector	O
Bit	O
Manipulation	O
Instructions	O
(	O
reserved	O
)	O
1	O
2	O
sgx	O
Software	O
Guard	O
Extensions	O
umip	O
User-mode	O
Instruction	O
Prevention	O
avx512-4vnniw	O
AVX-512	B-General_Concept
4-register	O
Neural	O
Network	O
Instructions	O
2	O
3	O
bmi1	O
Bit	O
Manipulation	O
Instruction	O
Set	O
1	O
pku	O
Memory	O
Protection	O
Keys	O
for	O
User-mode	O
pages	O
avx512-4fmaps	O
AVX-512	B-General_Concept
4-register	O
Multiply	O
Accumulation	O
Single	O
precision	O
3	O
4	O
hle	O
TSX	B-Operating_System
Hardware	O
Lock	O
Elision	O
ospke	O
PKU	O
enabled	O
by	O
OS	O
fsrm	O
Fast	O
Short	O
REP	O
MOVSB	O
4	O
5	O
avx2	O
Advanced	B-General_Concept
Vector	I-General_Concept
Extensions	I-General_Concept
2	O
waitpkg	O
Timed	O
pause	O
and	O
user-level	O
monitor/wait	O
uintr	O
User	O
Inter-processor	O
Interrupts	O
5	O
6	O
FDP_EXCPTN_ONLY	O
avx512-vbmi2	O
AVX-512	B-General_Concept
Vector	O
Bit	O
Manipulation	O
Instructions	O
2	O
(	O
reserved	O
)	O
6	O
7	O
smep	O
Supervisor	O
Mode	O
Execution	O
Prevention	O
cet_ss	O
Control	O
flow	O
enforcement	O
(	O
CET	O
)	O
shadow	O
stack	O
(	O
reserved	O
)	O
7	O
8	O
bmi2	O
Bit	O
Manipulation	O
Instruction	O
Set	O
2	O
gfni	O
Galois	O
Field	O
instructions	O
avx512-vp2intersect	O
AVX-512	B-General_Concept
VP2INTERSECT	O
Doubleword	O
and	O
Quadword	O
Instructions	O
8	O
9	O
erms	O
Enhanced	O
REP	O
MOVSB/STOSB	O
vaes	O
Vector	O
AES	B-Algorithm
instruction	I-Algorithm
set	I-Algorithm
(	O
VEX-256/EVEX	O
)	O
srdbs-ctrl	O
Special	O
Register	O
Buffer	O
Data	O
Sampling	O
Mitigations	O
9	O
10	O
invpcid	O
INVPCID	O
instruction	O
vpclmulqdq	O
CLMUL	B-Device
instruction	I-Device
set	I-Device
(	O
VEX-256/EVEX	O
)	O
mc-clear	O
VERW	O
instruction	O
clears	O
CPU	B-General_Concept
buffers	O
10	O
11	O
rtm	O
TSX	B-Operating_System
Restricted	O
Transactional	O
Memory	O
avx512-vnni	O
AVX-512	B-General_Concept
Vector	O
Neural	O
Network	O
Instructions	O
rtm-always-abort	O
All	O
TSX	B-Operating_System
transactions	O
are	O
aborted	O
11	O
12	O
rdt-m/pqm	O
Intel	O
Resource	O
Director	O
(	O
RDT	O
)	O
Monitoring	O
or	O
AMD	O
Platform	O
QOS	O
Monitoring	O
avx512-bitalg	O
AVX-512	B-General_Concept
BITALG	O
instructions	O
(	O
reserved	O
)	O
12	O
13	O
FPU	O
CS	O
and	O
FPU	O
DS	O
deprecated	O
tme	O
IA32_TME	O
related	O
MSRs	O
TSX_FORCE_ABORT	O
MSR	O
is	O
available	O
13	O
14	O
mpx	O
Intel	B-Device
MPX	I-Device
(	O
Memory	B-Device
Protection	I-Device
Extensions	I-Device
)	O
avx512-vpopcntdq	O
AVX-512	B-General_Concept
Vector	O
Population	O
Count	O
Double	O
and	O
Quad-word	O
serialize	O
SERIALIZE	O
instruction	O
14	O
15	O
rdt-a/pqe	O
Intel	O
Resource	O
Director	O
(	O
RDT	O
)	O
Allocation	O
or	O
AMD	O
Platform	O
QOS	O
Enforcement	O
(	O
reserved	O
)	O
hybrid	O
Mixture	O
of	O
CPU	B-General_Concept
types	O
in	O
processor	O
topology	O
(	O
eg	O
.	O
</s>
<s>
+	O
EAX	O
=	O
0Dh	O
,	O
ECX	O
=	O
1	O
CPUID	B-Architecture
feature	O
bits	O
Bit	O
EAX	O
Short	O
Feature	O
0	O
sgx1	O
SGX1	O
leaf	O
functions	O
1	O
sgx2	O
SGX2	O
leaf	O
functions	O
2	O
(	O
reserved	O
)	O
3	O
(	O
reserved	O
)	O
4	O
(	O
reserved	O
)	O
5	O
oss	O
ENCLV	O
leaves	O
:	O
EINCVIRTCHILD	O
,	O
EDECVIRTCHILD	O
,	O
and	O
ESETCONTEXT	O
6	O
?	O
</s>
<s>
+	O
EAX	O
=	O
14h	O
,	O
ECX	O
=	O
0	O
CPUID	B-Architecture
feature	O
bits	O
Bit	O
EBX	O
Short	O
Feature	O
0	O
(	O
reserved	O
)	O
1	O
(	O
reserved	O
)	O
2	O
(	O
reserved	O
)	O
3	O
(	O
reserved	O
)	O
4	O
ptwrite	O
?	O
</s>
<s>
+	O
EAX	O
=	O
80000001h	O
CPUID	B-Architecture
feature	O
bits	O
Bit	O
EDX	O
ECX	O
Short	O
Feature	O
Short	O
Feature	O
0	O
fpu	O
Onboard	O
x87	B-Application
FPU	I-Application
lahf_lm	O
LAHF/SAHF	O
in	O
long	B-Application
mode	I-Application
1	O
vme	O
Virtual	O
mode	O
extensions	O
(	O
VIF	O
)	O
cmp_legacy	O
Hyperthreading	B-Operating_System
not	O
valid	O
2	O
de	O
Debugging	O
extensions	O
(	O
CR4	O
bit	O
3	O
)	O
svm	O
Secure	O
Virtual	O
Machine	O
3	O
pse	O
Page	B-General_Concept
Size	I-General_Concept
Extension	I-General_Concept
extapic	O
Extended	O
APIC	B-Device
space	O
4	O
tsc	O
Time	B-Device
Stamp	I-Device
Counter	I-Device
cr8_legacy	O
CR8	O
in	O
32-bit	O
mode	O
5	O
msr	O
Model-specific	B-General_Concept
registers	I-General_Concept
abm	O
Advanced	O
bit	O
manipulation	O
(	O
lzcnt	B-Algorithm
and	O
popcnt	O
)	O
6	O
pae	O
Physical	B-General_Concept
Address	I-General_Concept
Extension	I-General_Concept
sse4a	O
SSE4a	O
7	O
mce	O
Machine	B-Device
Check	I-Device
Exception	I-Device
misalignsse	O
Misaligned	O
SSE	B-General_Concept
mode	O
8	O
cx8	O
CMPXCHG8	O
(	O
compare-and-swap	B-Operating_System
)	O
instruction	O
3dnowprefetch	O
PREFETCH	O
and	O
PREFETCHW	O
instructions	O
9	O
apic	B-Device
Onboard	O
Advanced	B-Device
Programmable	I-Device
Interrupt	I-Device
Controller	I-Device
osvw	O
OS	O
Visible	O
Workaround	O
10	O
(	O
reserved	O
)	O
ibs	O
Instruction	O
Based	O
Sampling	O
11	O
syscall	O
SYSCALL	O
and	O
SYSRET	O
instructions	O
xop	O
XOP	B-General_Concept
instruction	I-General_Concept
set	I-General_Concept
12	O
mtrr	O
Memory	B-General_Concept
Type	I-General_Concept
Range	I-General_Concept
Registers	I-General_Concept
skinit	O
SKINIT/STGI	O
instructions	O
13	O
pge	O
Page	B-General_Concept
Global	O
Enable	O
bit	O
in	O
CR4	O
wdt	O
Watchdog	B-Application
timer	I-Application
14	O
mca	O
Machine	B-Device
check	I-Device
architecture	I-Device
(	O
reserved	O
)	O
15	O
cmov	O
Conditional	O
move	O
and	O
FCMOV	B-Device
instructions	O
lwp	O
Light	O
Weight	O
Profiling	O
16	O
pat	O
Page	B-General_Concept
Attribute	I-General_Concept
Table	I-General_Concept
fma4	B-General_Concept
4	O
operands	O
fused	B-General_Concept
multiply-add	I-General_Concept
17	O
pse36	B-General_Concept
36-bit	B-General_Concept
page	I-General_Concept
size	I-General_Concept
extension	I-General_Concept
tce	O
Translation	O
Cache	O
Extension	O
18	O
(	O
reserved	O
)	O
19	O
mp	O
Multiprocessor	B-Operating_System
Capable	O
nodeid_msr	O
NodeID	O
MSR	O
20	O
nx	O
NX	B-General_Concept
bit	I-General_Concept
(	O
reserved	O
)	O
21	O
(	O
reserved	O
)	O
tbm	O
Trailing	O
Bit	O
Manipulation	O
22	O
mmxext	O
Extended	O
MMX	B-Architecture
topoext	O
Topology	O
Extensions	O
23	O
mmx	B-Architecture
MMX	B-Architecture
instructions	O
perfctr_core	O
Core	O
performance	O
counter	O
extensions	O
24	O
fxsr	O
FXSAVE	O
,	O
FXRSTOR	O
instructions	O
,	O
CR4	O
bit	O
9	O
perfctr_nb	O
NB	O
performance	O
counter	O
extensions	O
25	O
fxsr_opt	O
FXSAVE/FXRSTOR	O
optimizations	O
(	O
reserved	O
)	O
26	O
pdpe1gb	O
Gigabyte	O
pages	O
dbx	O
Data	O
breakpoint	O
extensions	O
27	O
rdtscp	O
RDTSCP	O
instruction	O
perftsc	O
Performance	O
TSC	O
28	O
(	O
reserved	O
)	O
pcx_l2i	O
L2I	O
perf	O
counter	O
extensions	O
29	O
lm	O
Long	B-Application
mode	I-Application
monitorx	O
MONITORX	O
and	O
MWAITX	O
instructions	O
30	O
3dnowext	O
Extended	O
3DNow	B-General_Concept
!	I-General_Concept
</s>
<s>
31	O
3dnow	B-General_Concept
3DNow	B-General_Concept
!	I-General_Concept
</s>
<s>
CPUID	B-Architecture
must	O
be	O
issued	O
with	O
each	O
parameter	O
in	O
sequence	O
to	O
get	O
the	O
entire	O
48-byte	O
null-terminated	O
ASCII	B-Protocol
processor	O
brand	O
string	O
.	O
</s>
<s>
It	O
is	O
necessary	O
to	O
check	O
whether	O
the	O
feature	O
is	O
present	O
in	O
the	O
CPU	B-General_Concept
by	O
issuing	O
CPUID	B-Architecture
with	O
EAX	O
=	O
80000000h	O
first	O
and	O
checking	O
if	O
the	O
returned	O
value	O
is	O
not	O
less	O
than	O
80000004h	O
.	O
</s>
<s>
This	O
function	O
contains	O
the	O
processor	O
’s	O
L1	O
cache	O
and	O
TLB	B-Architecture
characteristics	O
.	O
</s>
<s>
+	O
EAX	O
=	O
8000001Fh	O
CPUID	B-Architecture
feature	O
bits	O
Bit	O
EAX	O
Short	O
Feature	O
0	O
sme	O
Secure	O
Memory	O
Encryption	O
1	O
sev	O
Secure	O
Encrypted	O
Virtualization	O
2	O
page_flush	O
Page	B-General_Concept
flush	O
MSR	O
3	O
sev_es	O
SEV	O
Encrypted	O
State	O
4	O
sev_snp	O
SEC	O
Secure	O
Nested	O
Paging	O
5	O
vmpl	O
VM	O
Permission	O
Levels	O
6	O
(	O
reserved	O
)	O
7	O
(	O
reserved	O
)	O
8	O
(	O
reserved	O
)	O
9	O
(	O
reserved	O
)	O
10	O
hw_cache_coherency	O
?	O
</s>
<s>
+	O
EAX	O
=	O
80000021h	O
CPUID	B-Architecture
feature	O
bits	O
Bit	O
EBX	O
Short	O
Feature	O
11:0	O
MicrocodePatchSize	O
The	O
size	O
of	O
the	O
Microcode	O
patch	O
in	O
16-byte	O
multiples	O
.	O
</s>
<s>
Several	O
AMD	O
CPU	B-General_Concept
models	O
will	O
,	O
for	O
CPUID	B-Architecture
with	O
EAX	O
=	O
8FFFFFFFh	O
,	O
return	O
an	O
Easter	O
Egg	O
string	O
in	O
EAX	O
,	O
EBX	O
,	O
ECX	O
and	O
EDX	O
.	O
</s>
<s>
Processor	O
String	O
AMD	B-Architecture
K6	I-Architecture
NexGen‍erationAMD	O
AMD	B-Device
K8	I-Device
IT	O
'S	O
HAMMER	O
TIME	O
AMD	O
Jaguarinstlatx64	O
,	O
CPUID	B-Architecture
dump	O
of	O
AMD	O
A4-5000	O
,	O
lists	O
"	O
HELLO	O
KITTY	O
"	O
string	O
for	O
CPUID	B-Architecture
leaf	O
8FFFFFFFh	O
.	O
</s>
<s>
For	O
instance	O
,	O
the	O
C	O
code	O
for	O
gcc	O
below	O
prints	O
the	O
first	O
five	O
values	O
,	O
returned	O
by	O
the	O
cpuid	B-Architecture
:	O
</s>
<s>
In	O
MSVC	B-Application
and	O
Borland/Embarcadero	O
C	O
compilers	O
(	O
bcc32	O
)	O
flavored	O
inline	O
assembly	O
,	O
the	O
clobbering	O
information	O
is	O
implicit	O
in	O
the	O
instructions	O
:	O
</s>
<s>
If	O
either	O
version	O
was	O
written	O
in	O
plain	O
assembly	B-Language
language	I-Language
,	O
the	O
programmer	O
must	O
manually	O
save	O
the	O
results	O
of	O
EAX	O
,	O
EBX	O
,	O
ECX	O
,	O
and	O
EDX	O
elsewhere	O
if	O
they	O
want	O
to	O
keep	O
using	O
the	O
values	O
.	O
</s>
<s>
GCC	O
also	O
provides	O
a	O
header	O
called	O
<cpuid.h>	O
on	O
systems	O
that	O
have	O
CPUID	B-Architecture
.	O
</s>
<s>
But	O
if	O
one	O
requested	O
an	O
extended	O
feature	O
not	O
present	O
on	O
this	O
CPU	B-General_Concept
,	O
they	O
would	O
not	O
notice	O
and	O
might	O
get	O
random	O
,	O
unexpected	O
results	O
.	O
</s>
<s>
Safer	O
version	O
is	O
also	O
provided	O
in	O
<cpuid.h>	O
.	O
</s>
<s>
Microsoft	B-Application
Visual	I-Application
C	I-Application
compiler	O
has	O
builtin	O
function	O
__cpuid( )	O
so	O
the	O
cpuid	B-Architecture
instruction	O
may	O
be	O
embedded	O
without	O
using	O
inline	O
assembly	O
,	O
which	O
is	O
handy	O
since	O
the	O
x86-64	O
version	O
of	O
MSVC	B-Application
does	O
not	O
allow	O
inline	O
assembly	O
at	O
all	O
.	O
</s>
<s>
The	O
same	O
program	O
for	O
MSVC	B-Application
would	O
be	O
:	O
</s>
<s>
Many	O
interpreted	O
or	O
compiled	O
scripting	O
languages	O
are	O
capable	O
of	O
using	O
CPUID	B-Architecture
via	O
an	O
FFI	B-Application
library	O
.	O
</s>
<s>
shows	O
usage	O
of	O
the	O
Ruby	O
FFI	B-Application
module	O
to	O
execute	O
assembly	B-Language
language	I-Language
that	O
includes	O
the	O
CPUID	B-Architecture
opcode	B-Language
.	O
</s>
<s>
.NET	B-Application
5	I-Application
and	O
later	O
versions	O
provide	O
the	O
System.Runtime.Intrinsics.X86.X86base.CpuId	O
method	O
.	O
</s>
<s>
For	O
instance	O
,	O
the	O
C#	O
code	O
below	O
prints	O
the	O
processor	O
brand	O
if	O
it	O
supports	O
CPUID	B-Architecture
instruction	O
:	O
</s>
<s>
Some	O
of	O
the	O
non-x86	O
CPU	B-General_Concept
architectures	O
also	O
provide	O
certain	O
forms	O
of	O
structured	O
information	O
about	O
the	O
processor	O
's	O
abilities	O
,	O
commonly	O
as	O
a	O
set	O
of	O
special	O
registers	O
:	O
</s>
<s>
ARM	B-Architecture
architectures	I-Architecture
have	O
a	O
CPUIDcoprocessor	O
register	O
which	O
requires	O
EL1	O
or	O
above	O
to	O
access	O
.	O
</s>
<s>
The	O
IBM	B-Device
System	I-Device
z	I-Device
mainframe	O
processors	O
have	O
a	O
Store	O
CPU	B-General_Concept
ID	O
(	O
STIDP	O
)	O
instruction	O
since	O
the	O
1983	O
IBM	B-Device
4381	I-Device
for	O
querying	O
the	O
processor	O
ID	O
.	O
</s>
<s>
The	O
IBM	B-Device
System	I-Device
z	I-Device
mainframe	O
processors	O
also	O
have	O
a	O
Store	O
Facilities	O
List	O
Extended	O
(	O
STFLE	O
)	O
instruction	O
which	O
lists	O
the	O
installed	O
hardware	O
features	O
.	O
</s>
<s>
The	O
MIPS32/64	B-Device
architecture	O
defines	O
a	O
mandatory	O
Processor	O
Identification	O
(	O
PrId	O
)	O
and	O
a	O
series	O
of	O
daisy-chained	O
Configuration	O
Registers	O
.	O
</s>
<s>
The	O
PowerPC	B-Architecture
processor	I-Architecture
has	O
the	O
32-bit	O
read-only	O
Processor	O
Version	O
Register	O
(	O
PVR	O
)	O
identifying	O
the	O
processor	O
model	O
in	O
use	O
.	O
</s>
<s>
DSP	B-Architecture
and	O
transputer-like	O
chip	O
families	O
have	O
not	O
taken	O
up	O
the	O
instruction	O
in	O
any	O
noticeable	O
way	O
,	O
in	O
spite	O
of	O
having	O
(	O
in	O
relative	O
terms	O
)	O
as	O
many	O
variations	O
in	O
design	O
.	O
</s>
