<s>
The	O
National	O
Semiconductor	O
COP8	B-Device
is	O
an	O
8-bit	O
CISC	B-Architecture
core	O
microcontroller	B-Architecture
.	O
</s>
<s>
COP8	B-Device
is	O
an	O
enhancement	O
to	O
the	O
earlier	O
COP400	B-Device
4-bit	O
microcontroller	B-Architecture
family	O
.	O
</s>
<s>
COP8	B-Device
main	O
features	O
are	O
:	O
</s>
<s>
Free	O
assembler	B-Language
toolchain	O
.	O
</s>
<s>
The	O
COP8	B-Device
uses	O
separate	O
instruction	O
and	O
data	O
spaces	O
(	O
Harvard	B-Architecture
architecture	I-Architecture
)	O
.	O
</s>
<s>
The	O
CPU	O
has	O
an	O
8-bit	O
accumulator	O
and	O
15-bit	O
program	B-General_Concept
counter	I-General_Concept
.	O
</s>
<s>
16	O
additional	O
8-bit	O
registers	O
(	O
R0	O
–	O
R15	O
)	O
and	O
an	O
8-bit	O
program	B-Device
status	I-Device
word	I-Device
are	O
memory	O
mapped	O
.	O
</s>
<s>
+	O
COP8	B-Device
data	O
address	O
space	O
Addresses	O
Use	O
0x00	O
–	O
6F	O
General	O
purpose	O
RAM	O
,	O
used	O
for	O
stack	O
0x70	O
–	O
7F	O
Unused	O
,	O
reads	O
as	O
all-ones	O
(	O
0xFF	O
)	O
to	O
trap	O
stack	O
underflows	O
0x80	O
–	O
8F	O
Unused	O
,	O
reads	O
undefined	O
0x90	O
–	O
BF	O
Additional	O
peripheral	O
control	O
registers	O
0xC0	O
–	O
CF	O
Peripheral	O
control	O
registers	O
.	O
</s>
<s>
0xD0	O
–	O
DF	O
General	O
purpose	O
I/O	B-General_Concept
ports	O
L	O
,	O
G	O
,	O
I	O
,	O
C	B-Language
and	O
D	O
0xE0	O
–	O
E8	O
Reserved	O
0xE9	O
Microwire	O
shift	O
register	O
0xEA	O
–	O
ED	O
Timer	O
1	O
registers	O
0xEE	O
CNTRL	O
register	O
,	O
control	O
bits	O
for	O
Microwire	O
&	O
Timer	O
1	O
0xEF	O
PSW	O
,	O
CPU	O
program	B-Device
status	I-Device
word	I-Device
0xF0	O
–	O
FB	O
R0	O
–	O
R11	O
,	O
general	O
purpose	O
registers	O
(	O
additional	O
RAM	O
)	O
0xFC	O
R12	O
,	O
a.k.a.	O
</s>
<s>
(	O
These	O
are	O
intended	O
primarily	O
for	O
models	O
with	O
up	O
to	O
4K	O
of	O
ROM	B-Device
.	O
)	O
</s>
<s>
Conditional	O
branches	O
per	O
se	O
do	O
not	O
exist	O
,	O
nor	O
does	O
the	O
processor	O
provide	O
the	O
traditional	O
ZCVN	O
status	O
flags	O
,	O
although	O
the	O
program	B-Device
status	I-Device
word	I-Device
contains	O
carry	O
and	O
half-carry	O
flags	O
for	O
multi-byte	O
arithmetic	O
.	O
</s>
<s>
A	O
feature	O
unique	O
to	O
the	O
COP8	B-Device
architecture	O
is	O
the	O
instruction	O
.	O
</s>
<s>
COP8	B-Device
operands	O
are	O
listed	O
in	O
destination	O
,	O
source	O
order	O
.	O
</s>
<s>
There	O
are	O
instructions	O
to	O
fetch	O
from	O
tables	O
in	O
ROM	B-Device
.	O
</s>
<s>
These	O
combine	O
the	O
high	O
7	O
bits	O
of	O
the	O
program	B-General_Concept
counter	I-General_Concept
(	O
PCU	O
)	O
with	O
the	O
accumulator	O
,	O
fetch	O
a	O
byte	O
from	O
that	O
address	O
,	O
and	O
place	O
it	O
in	O
the	O
accumulator	O
(	O
instruction	O
)	O
or	O
the	O
low	O
8	O
bits	O
of	O
the	O
program	B-General_Concept
counter	I-General_Concept
PCL	O
(	O
instruction	O
)	O
.	O
</s>
<s>
Because	O
the	O
next	B-General_Concept
instruction	I-General_Concept
executed	O
must	O
be	O
in	O
the	O
same	O
256-byte	O
page	O
of	O
ROM	B-Device
as	O
the	O
table	O
itself	O
,	O
a	O
256-entry	O
table	O
is	O
not	O
possible	O
.	O
</s>
<s>
+	O
COP8	B-Device
family	O
instruction	O
set	O
Extracted	O
from	O
zipped	B-General_Concept
ISO	B-General_Concept
image	I-General_Concept
530094-003_COP8_Tools_Docs_Aug1999.zip	O
,	O
retrieved	O
2020-01-07	O
.	O
</s>
<s>
0	O
1	O
0	O
0	O
k	O
—	O
—	O
IFBNE	O
#imm4	O
1	O
Execute	O
next	B-General_Concept
instruction	I-General_Concept
if	O
(	O
B	O
&	O
15	O
)	O
≠	O
k	O
;	O
skip	O
if	O
(	O
B	O
&	O
15	O
)	O
=	O
k	O
.	O
0	O
1	O
0	O
1	O
k	O
—	O
—	O
LD	O
B	O
,	O
#imm4	O
1	O
B	O
←	O
15	O
−	O
k	O
(	O
zero-extended	O
)	O
0	O
1	O
1	O
0	O
0	O
0	O
0	O
0	O
k	O
—	O
ANDSZ	O
A	O
,	O
#imm8	O
*	O
2	O
Skip	O
if	O
A	O
&	O
k	O
=	O
0	O
(=	O
IFBIT	O
#bit	O
,	O
A	O
)	O
0	O
1	O
1	O
0	O
0	O
0	O
0	O
1	O
addrlo	O
—	O
JSRB	O
addr8†	O
5	O
Push	O
PC	O
,	O
jump	O
to	O
boot	O
ROM	B-Device
subroutine	O
at	O
address	O
0	O
1	O
1	O
0	O
0	O
0	O
1	O
–	O
—	O
—	O
(	O
reserved	O
for	O
boot	O
ROM†	O
)	O
0	O
1	O
1	O
0	O
0	O
1	O
0	O
0	O
—	O
—	O
CLR	O
A	O
1	O
A	O
←	O
0	O
0	O
1	O
1	O
0	O
0	O
1	O
0	O
1	O
—	O
—	O
SWAP	O
A	O
1	O
A	O
←	O
Axxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx1>4	O
;	O
swap	O
nibbles	O
0	O
1	O
1	O
0	O
0	O
1	O
1	O
0	O
—	O
—	O
DCOR	O
A	O
1	O
Decimal	O
correct	O
after	O
BCD	O
addition	O
0	O
1	O
1	O
0	O
0	O
1	O
1	O
1	O
—	O
—	O
PUSH	O
A*	O
3	O
 [ SP ] 	O
←	O
A	O
,	O
SP	O
←	O
SP−1	O
0	O
1	O
1	O
0	O
1	O
bit	O
—	O
—	O
RBIT	O
#bit,[B]	O
1	O
Reset	O
(	O
clear	O
to	O
0	O
)	O
given	O
bit	O
of	O
RAM	O
0	O
1	O
1	O
1	O
0	O
bit	O
—	O
—	O
IFBIT	O
#bit,[B]	O
1	O
Test	O
given	O
bit	O
of	O
RAM	O
,	O
skip	O
if	O
zero	O
0	O
1	O
1	O
1	O
1	O
bit	O
—	O
—	O
SBIT	O
#bit,[B]	O
1	O
Set	O
(	O
to	O
1	O
)	O
given	O
bit	O
of	O
RAM	O
1	O
0	O
0	O
m	O
0	O
opcode	O
operand	O
—	O
ALU	O
operations	O
,	O
A	O
←	O
A	O
op	O
operand	O
1	O
0	O
0	O
0	O
0	O
opcode	O
—	O
—	O
OP	O
A,[B]	O
1	O
ALU	O
operation	O
with	O
A	O
and	O
 [ B ] 	O
(	O
with	O
 [ address ] 	O
using	O
DIR	O
prefix	O
)	O
1	O
0	O
0	O
1	O
0	O
opcode	O
k	O
—	O
OP	O
A	O
,	O
#imm8	O
2	O
ALU	O
operation	O
with	O
A	O
and	O
immediate	O
k	O
1	O
0	O
0	O
m	O
0	O
0	O
0	O
0	O
operand	O
—	O
ADC	O
A	O
,	O
operand	O
C	B-Language
,	O
A	O
←	O
A	O
+	O
operand	O
+	O
C	B-Language
;	O
add	O
with	O
carry	O
1	O
0	O
0	O
m	O
0	O
0	O
0	O
1	O
operand	O
—	O
SUBC	O
A	O
,	O
operand	O
C	B-Language
,	O
A	O
←	O
A	O
+	O
~	O
operand	O
+	O
C	B-Language
(	O
A	O
−	O
operand	O
−	O
~	O
C	B-Language
)	O
1	O
0	O
0	O
m	O
0	O
0	O
1	O
0	O
operand	O
—	O
IFEQ	O
A	O
,	O
operand	O
Skip	O
if	O
A	O
≠	O
operand	O
1	O
0	O
0	O
m	O
0	O
0	O
1	O
1	O
operand	O
—	O
IFGT	O
A	O
,	O
operand	O
Skip	O
if	O
A	O
≤	O
operand	O
1	O
0	O
0	O
m	O
0	O
1	O
0	O
0	O
operand	O
—	O
ADD	O
A	O
,	O
operand	O
A	O
←	O
A	O
+	O
operand	O
(	O
carry	O
unchanged	O
!	O
)	O
</s>
