<s>
The	O
CDC	B-Device
Cyber	I-Device
range	O
of	O
mainframe-class	O
supercomputers	B-Architecture
were	O
the	O
primary	O
products	O
of	O
Control	O
Data	O
Corporation	O
(	O
CDC	O
)	O
during	O
the	O
1970s	O
and	O
1980s	O
.	O
</s>
<s>
The	O
lineup	O
also	O
included	O
the	O
Cyber	O
18	O
and	O
Cyber	O
1000	O
minicomputers	B-Architecture
.	O
</s>
<s>
Like	O
their	O
predecessor	O
,	O
the	O
CDC	B-Device
6600	I-Device
,	O
they	O
were	O
unusual	O
in	O
using	O
the	O
ones	O
 '	O
complement	O
binary	O
representation	O
.	O
</s>
<s>
The	O
200	O
series	O
based	O
on	O
the	O
CDC	B-Device
STAR-100	I-Device
-	O
released	O
in	O
the	O
1970s	O
.	O
</s>
<s>
Primarily	O
aimed	O
at	O
large	O
office	O
applications	O
instead	O
of	O
the	O
traditional	O
supercomputer	B-Architecture
tasks	O
,	O
some	O
of	O
the	O
Cyber	O
machines	O
nevertheless	O
included	O
basic	O
vector	B-Operating_System
instructions	I-Operating_System
for	O
added	O
performance	O
in	O
traditional	O
CDC	O
roles	O
.	O
</s>
<s>
The	O
Cyber	B-Device
70	I-Device
and	O
170	O
architectures	O
were	O
successors	O
to	O
the	O
earlier	O
CDC	B-Device
6600	I-Device
and	O
CDC	B-Device
7600	I-Device
series	O
and	O
therefore	O
shared	O
almost	O
all	O
of	O
the	O
earlier	O
architecture	O
's	O
characteristics	O
.	O
</s>
<s>
The	O
Cyber-73	O
could	O
be	O
configured	O
with	O
either	O
one	O
or	O
two	O
CPUs	B-General_Concept
.	O
</s>
<s>
It	O
could	O
also	O
be	O
delivered	O
with	O
dual	O
CPUs	B-General_Concept
.	O
</s>
<s>
The	O
Cyber	O
74	O
was	O
an	O
updated	O
version	O
of	O
the	O
CDC	B-Device
6600	I-Device
.	O
</s>
<s>
The	O
Cyber	O
76	O
was	O
essentially	O
a	O
renamed	O
CDC	B-Device
7600	I-Device
.	O
</s>
<s>
The	O
Cyber-170	O
series	O
represented	O
CDCs	O
move	O
from	O
discrete	O
electronic	O
components	O
and	O
core	O
memory	O
to	O
integrated	O
circuits	O
and	O
semiconductor	B-Architecture
memory	I-Architecture
.	O
</s>
<s>
The	O
172	O
,	O
173	O
,	O
and	O
174	O
use	O
integrated	O
circuits	O
and	O
semiconductor	B-Architecture
memory	I-Architecture
whereas	O
the	O
175	O
uses	O
high-speed	O
discrete	O
transistors	O
.	O
</s>
<s>
The	O
central	O
processor	B-General_Concept
(	O
CPU	O
)	O
and	O
central	O
memory	O
(	O
CM	O
)	O
operated	O
in	O
units	O
of	O
60-bit	O
words	O
.	O
</s>
<s>
In	O
CDC	O
lingo	O
,	O
the	O
term	O
"	O
byte	B-Application
"	O
referred	O
to	O
12-bit	O
entities	O
(	O
which	O
coincided	O
with	O
the	O
word	O
size	O
used	O
by	O
the	O
peripheral	O
processors	O
)	O
.	O
</s>
<s>
Central	O
processor	B-General_Concept
instructions	O
were	O
either	O
15	O
bits	O
or	O
30	O
bits	O
.	O
</s>
<s>
The	O
18-bit	O
addressing	O
inherent	O
to	O
the	O
Cyber	O
170	O
series	O
imposed	O
a	O
limit	O
of	O
262,144	O
(	O
256K	O
)	O
words	O
of	O
main	O
memory	O
,	O
which	O
is	O
semiconductor	B-Architecture
memory	I-Architecture
in	O
this	O
series	O
.	O
</s>
<s>
The	O
central	O
processor	B-General_Concept
has	O
no	O
I/O	B-General_Concept
instructions	O
,	O
relying	O
upon	O
the	O
peripheral	O
processor	B-General_Concept
(	O
PP	O
)	O
units	O
to	O
do	O
I/O	B-General_Concept
.	O
</s>
<s>
A	O
Cyber	O
170-series	O
system	O
consists	O
of	O
one	O
or	O
two	O
CPUs	B-General_Concept
that	O
run	O
at	O
either	O
25	O
or	O
40MHz	O
,	O
and	O
is	O
equipped	O
with	O
10	O
,	O
14	O
,	O
17	O
,	O
or	O
20	O
peripheral	O
processors	O
(	O
PP	O
)	O
,	O
and	O
up	O
to	O
24	O
high-performance	O
channels	O
for	O
high-speed	O
I/O	B-General_Concept
.	O
</s>
<s>
Due	O
to	O
the	O
relatively	O
slow	O
memory	O
reference	O
times	O
of	O
the	O
CPU	O
(	O
in	O
some	O
models	O
,	O
memory	O
reference	O
instructions	O
were	O
slower	O
than	O
floating-point	O
divides	O
)	O
,	O
the	O
higher-end	O
CPUs	B-General_Concept
(	O
e.g.	O
,	O
Cyber-74	O
,	O
Cyber-76	O
,	O
Cyber-175	O
,	O
and	O
Cyber-176	O
)	O
are	O
equipped	O
with	O
eight	O
or	O
twelve	O
words	O
of	O
high-speed	O
memory	O
used	O
as	O
an	O
instruction	O
cache	O
.	O
</s>
<s>
As	O
with	O
predecessor	O
systems	O
,	O
the	O
Cyber	O
170	O
series	O
has	O
eight	O
18-bit	O
address	B-General_Concept
registers	I-General_Concept
(	O
A0	O
through	O
A7	O
)	O
,	O
eight	O
18-bit	O
index	O
registers	B-General_Concept
(	O
B0	O
through	O
B7	O
)	O
,	O
and	O
eight	O
60-bit	O
operand	O
registers	B-General_Concept
(	O
X0	O
through	O
X7	O
)	O
.	O
</s>
<s>
Seven	O
of	O
the	O
A	O
registers	B-General_Concept
are	O
tied	O
to	O
their	O
corresponding	O
X	O
register	O
.	O
</s>
<s>
A0	O
is	O
effectively	O
a	O
scratch	B-General_Concept
register	I-General_Concept
.	O
</s>
<s>
The	O
higher-end	O
CPUs	B-General_Concept
consisted	O
of	O
multiple	O
functional	B-General_Concept
units	I-General_Concept
(	O
e.g.	O
,	O
shift	O
,	O
increment	O
,	O
floating	O
add	O
)	O
which	O
allowed	O
some	O
degree	O
of	O
parallel	O
execution	O
of	O
instructions	O
.	O
</s>
<s>
The	O
peripheral	O
processor	B-General_Concept
subsystem	O
uses	O
a	O
technique	O
known	O
as	O
barrel	O
and	O
slot	O
to	O
share	O
the	O
execution	B-General_Concept
unit	I-General_Concept
;	O
each	O
PP	O
had	O
its	O
own	O
memory	O
and	O
registers	B-General_Concept
,	O
but	O
the	O
processor	B-General_Concept
(	O
the	O
slot	O
)	O
itself	O
executed	O
one	O
instruction	O
from	O
each	O
PP	O
in	O
turn	O
(	O
the	O
barrel	O
)	O
.	O
</s>
<s>
The	O
peripheral	O
processors	O
have	O
4096	O
bytes	B-Application
of	O
12-bit	O
memory	O
words	O
and	O
an	O
18-bit	O
accumulator	O
register	O
.	O
</s>
<s>
Each	O
PP	O
has	O
access	O
to	O
all	O
I/O	B-General_Concept
channels	O
and	O
all	O
of	O
the	O
system	O
's	O
central	O
memory	O
(	O
CM	O
)	O
in	O
addition	O
to	O
the	O
PP	O
's	O
own	O
memory	O
.	O
</s>
<s>
The	O
PP	O
instruction	O
set	O
lacks	O
,	O
for	O
example	O
,	O
extensive	O
arithmetic	O
capabilities	O
and	O
does	O
not	O
run	O
user	O
code	O
;	O
the	O
peripheral	O
processor	B-General_Concept
subsystem	O
's	O
purpose	O
is	O
to	O
process	O
I/O	B-General_Concept
and	O
thereby	O
free	O
the	O
more	O
powerful	O
central	O
processor	B-General_Concept
unit(s )	O
to	O
running	O
user	O
computations	O
.	O
</s>
<s>
A	O
feature	O
of	O
the	O
lower	O
Cyber	O
CPUs	B-General_Concept
is	O
the	O
Compare	O
Move	O
Unit	O
(	O
CMU	O
)	O
.	O
</s>
<s>
The	O
CMU	O
hardware	O
is	O
not	O
included	O
in	O
the	O
higher-end	O
Cyber	O
CPUs	B-General_Concept
,	O
because	O
hand	O
coded	O
loops	O
could	O
run	O
as	O
fast	O
or	O
faster	O
than	O
the	O
CMU	O
instructions	O
.	O
</s>
<s>
Later	O
systems	O
typically	O
run	O
CDC	O
's	O
NOS	B-Operating_System
(	O
Network	O
Operating	O
System	O
)	O
.	O
</s>
<s>
Version	O
1	O
of	O
NOS	B-Operating_System
continued	O
to	O
be	O
updated	O
until	O
about	O
1981	O
;	O
NOS	B-Operating_System
version	O
2	O
was	O
released	O
early	O
1982	O
.	O
</s>
<s>
Besides	O
NOS	B-Operating_System
,	O
the	O
only	O
other	O
operating	O
systems	O
commonly	O
used	O
on	O
the	O
170	O
series	O
was	O
NOS/BE	B-Operating_System
or	O
its	O
predecessor	O
SCOPE	B-Operating_System
,	O
a	O
product	O
of	O
CDC	O
's	O
Sunnyvale	O
division	O
.	O
</s>
<s>
These	O
operating	O
systems	O
provide	O
time-sharing	B-General_Concept
of	O
batch	O
and	O
interactive	O
applications	O
.	O
</s>
<s>
The	O
predecessor	O
to	O
NOS	B-Operating_System
was	O
Kronos	B-Operating_System
which	O
was	O
in	O
common	O
use	O
up	O
until	O
1975	O
or	O
so	O
.	O
</s>
<s>
The	O
machine	O
family	O
was	O
originally	O
called	O
Integrated	O
Product	O
Line	O
(	O
IPL	O
)	O
and	O
was	O
intended	O
to	O
be	O
a	O
virtual	B-Architecture
memory	I-Architecture
replacement	O
for	O
the	O
NCR	O
6150	O
and	O
CDC	B-Device
Cyber	I-Device
70	I-Device
product	O
lines	O
.	O
</s>
<s>
The	O
Software	O
Writer	O
's	O
Language	O
(	O
SWL	O
)	O
,	O
a	O
high-level	O
Pascal-like	O
language	O
,	O
was	O
developed	O
for	O
the	O
project	O
with	O
the	O
intent	O
that	O
all	O
languages	O
and	O
the	O
operating	O
system	O
(	O
IPLOS	O
)	O
were	O
going	O
to	O
be	O
written	O
in	O
SWL	O
.	O
</s>
<s>
SWL	O
was	O
later	O
renamed	O
PASCAL-X	O
and	O
eventually	O
became	O
Cybil	B-Language
.	O
</s>
<s>
The	O
first	O
machines	O
of	O
the	O
series	O
were	O
announced	O
in	O
1982	O
and	O
the	O
product	O
announcement	O
for	O
the	O
NOS/VE	B-Operating_System
operating	O
system	O
occurred	O
in	O
1983	O
.	O
</s>
<s>
As	O
the	O
computing	O
world	O
standardized	O
to	O
an	O
eight-bit	O
byte	B-Application
size	O
,	O
CDC	O
customers	O
started	O
pushing	O
for	O
the	O
Cyber	O
machines	O
to	O
do	O
the	O
same	O
.	O
</s>
<s>
The	O
result	O
was	O
a	O
new	O
series	O
of	O
systems	O
that	O
could	O
operate	O
in	O
both	O
60	O
-	O
and	O
64-bit	B-Device
modes	O
.	O
</s>
<s>
The	O
64-bit	B-Device
operating	O
system	O
was	O
called	O
NOS/VE	B-Operating_System
,	O
and	O
supported	O
the	O
virtual	B-Architecture
memory	I-Architecture
capabilities	O
of	O
the	O
hardware	O
.	O
</s>
<s>
The	O
older	O
60-bit	O
operating	O
systems	O
,	O
NOS	B-Operating_System
and	O
NOS/BE	B-Operating_System
,	O
could	O
run	O
in	O
a	O
special	O
address	O
space	O
for	O
compatibility	O
with	O
the	O
older	O
systems	O
.	O
</s>
<s>
The	O
true	O
180-mode	O
machines	O
are	O
microcoded	B-Device
processors	O
that	O
can	O
support	O
both	O
instruction	O
sets	O
simultaneously	O
.	O
</s>
<s>
The	O
small	O
170-mode	O
exchange	O
package	O
was	O
mapped	O
into	O
the	O
much	O
larger	O
180-mode	O
exchange	O
package	O
;	O
within	O
the	O
180-mode	O
exchange	O
package	O
,	O
there	O
is	O
a	O
virtual	O
machine	O
identifier	O
(	O
VMID	O
)	O
that	O
determines	O
whether	O
the	O
8/16/64	O
-bit	O
two	O
's	O
complement	O
180	O
instruction	O
set	O
or	O
the	O
12/60	O
-bit	O
one	O
's	O
complement	O
170	O
instruction	O
set	O
is	O
executed	O
.	O
</s>
<s>
The	O
P2	O
was	O
designed	O
in	O
Mississauga	O
,	O
Ontario	B-Architecture
,	O
by	O
the	O
same	O
team	O
that	O
later	O
designed	O
the	O
smaller	O
P1	O
,	O
and	O
the	O
P3	O
was	O
designed	O
in	O
Arden	O
Hills	O
,	O
Minnesota	O
.	O
</s>
<s>
The	O
180s	O
were	O
initially	O
marketed	O
as	O
170/8xx	O
machines	O
with	O
no	O
mention	O
of	O
the	O
new	O
8/64	O
-bit	O
system	O
inside	O
.	O
</s>
<s>
The	O
170	O
operating	O
system	O
(	O
NOS	B-Operating_System
)	O
used	O
a	O
single	O
,	O
large	O
,	O
fixed	O
page	O
within	O
the	O
main	O
memory	O
.	O
</s>
<s>
The	O
single	O
word	O
I/O	B-General_Concept
instructions	O
in	O
the	O
PPs	O
are	O
always	O
16-bit	O
instructions	O
,	O
so	O
at	O
deadstart	O
the	O
PPs	O
can	O
set	O
up	O
the	O
proper	O
environment	O
to	O
run	O
both	O
EI	O
plus	O
NOS	B-Operating_System
and	O
the	O
customer	O
's	O
existing	O
170-mode	O
software	O
.	O
</s>
<s>
The	O
825	O
was	O
released	O
initially	O
after	O
some	O
delay	O
loops	O
had	O
been	O
added	O
to	O
its	O
microcode	B-Device
;	O
it	O
seemed	O
the	O
design	O
folks	O
in	O
Toronto	O
had	O
done	O
a	O
little	O
too	O
well	O
and	O
it	O
was	O
too	O
close	O
to	O
the	O
P2	O
in	O
performance	O
.	O
</s>
<s>
The	O
865	O
and	O
875	O
models	O
were	O
revamped	O
170/760	O
heads	O
(	O
one	O
or	O
two	O
processors	O
with	O
6600/7600	O
-style	O
parallel	O
functional	B-General_Concept
units	I-General_Concept
)	O
with	O
larger	O
memories	O
.	O
</s>
<s>
The	O
865	O
used	O
normal	O
170	O
memory	O
;	O
the	O
875	O
took	O
its	O
faster	O
main	O
processor	B-General_Concept
memory	O
from	O
the	O
Cyber	O
205	O
line	O
.	O
</s>
<s>
At	O
some	O
point	O
,	O
the	O
model	O
815	O
was	O
introduced	O
with	O
the	O
delayed	O
microcode	B-Device
and	O
the	O
faster	O
microcode	B-Device
was	O
restored	O
to	O
the	O
model	O
825	O
.	O
</s>
<s>
In	O
1974	O
,	O
CDC	O
introduced	O
the	O
STAR	B-Device
architecture	O
.	O
</s>
<s>
The	O
STAR	B-Device
is	O
an	O
entirely	O
new	O
64-bit	B-Device
design	O
with	O
virtual	B-Architecture
memory	I-Architecture
and	O
vector	B-Operating_System
processing	I-Operating_System
instructions	O
added	O
for	O
high	O
performance	O
on	O
a	O
certain	O
class	O
of	O
math	O
tasks	O
.	O
</s>
<s>
The	O
STAR	B-Device
's	O
vector	O
pipeline	O
is	O
a	O
memory	O
to	O
memory	O
pipe	O
,	O
which	O
supports	O
vector	O
lengths	O
of	O
up	O
to	O
65,536	O
elements	O
.	O
</s>
<s>
The	O
scalar	O
processor	B-General_Concept
was	O
deliberately	O
simplified	O
to	O
provide	O
room	O
for	O
the	O
vector	B-Operating_System
processor	I-Operating_System
and	O
is	O
relatively	O
slow	O
in	O
comparison	O
to	O
the	O
CDC	B-Device
7600	I-Device
.	O
</s>
<s>
As	O
such	O
,	O
the	O
original	O
STAR	B-Device
proved	O
to	O
be	O
a	O
great	O
disappointment	O
when	O
it	O
was	O
released	O
(	O
see	O
Amdahl	B-Operating_System
's	I-Operating_System
Law	I-Operating_System
)	O
.	O
</s>
<s>
Best	O
estimates	O
claim	O
that	O
three	O
STAR-100	O
systems	O
were	O
delivered	O
.	O
</s>
<s>
It	O
appeared	O
that	O
all	O
of	O
the	O
problems	O
in	O
the	O
STAR	B-Device
were	O
solvable	O
.	O
</s>
<s>
The	O
new	O
name	O
kept	O
with	O
their	O
new	O
branding	O
,	O
and	O
perhaps	O
to	O
distance	O
itself	O
from	O
the	O
STAR	B-Device
's	O
failure	O
.	O
</s>
<s>
The	O
Cyber	O
203	O
contains	O
redesigned	O
scalar	O
processing	O
and	O
loosely	O
coupled	O
I/O	B-General_Concept
design	O
,	O
but	O
retains	O
the	O
STAR	B-Device
's	O
vector	O
pipeline	O
.	O
</s>
<s>
Best	O
estimates	O
claim	O
that	O
two	O
Cyber	O
203s	O
were	O
delivered	O
or	O
upgraded	O
from	O
STAR-100s	O
.	O
</s>
<s>
The	O
Cyber	O
205	O
replaces	O
the	O
STAR	B-Device
vector	O
pipeline	O
with	O
redesigned	O
vector	O
pipelines	O
:	O
both	O
scalar	O
and	O
vector	O
units	O
utilized	O
ECL	B-General_Concept
gate	O
array	O
ICs	O
and	O
are	O
cooled	O
with	O
Freon	O
.	O
</s>
<s>
Cyber	O
205	O
systems	O
were	O
available	O
with	O
two	O
or	O
four	O
vector	O
pipelines	O
,	O
with	O
the	O
four-pipe	O
version	O
theoretically	O
delivering	O
400	O
64-bit	B-Device
MFLOPs	O
and	O
800	O
32-bit	O
MFLOPs	O
.	O
</s>
<s>
These	O
speeds	O
are	O
rarely	O
seen	O
in	O
practice	O
other	O
than	O
by	O
handcrafted	O
assembly	B-Language
language	I-Language
.	O
</s>
<s>
The	O
ECL	B-General_Concept
gate	O
array	O
ICs	O
contain	O
168	O
logic	O
gates	O
each	O
,	O
with	O
the	O
clock	O
tree	O
networks	O
being	O
tuned	O
by	O
hand-crafted	O
coax	O
length	O
adjustment	O
.	O
</s>
<s>
The	O
instruction	O
set	O
would	O
be	O
considered	O
V-CISC	O
(	O
very	O
complex	O
instruction	O
set	O
)	O
among	O
modern	O
processors	O
.	O
</s>
<s>
The	O
Cyber	O
205	O
architecture	O
evolved	O
into	O
the	O
ETA10	B-Operating_System
as	O
the	O
design	O
team	O
spun	O
off	O
into	O
ETA	O
Systems	O
in	O
September	O
1983	O
.	O
</s>
<s>
Each	O
Cyberplus	O
(	O
aka	O
Advanced	O
Flexible	O
Processor	B-General_Concept
,	O
AFP	O
)	O
is	O
a	O
16-bit	O
processor	B-General_Concept
with	O
optional	O
64-bit	B-Device
floating	O
point	O
capabilities	O
and	O
has	O
256	O
K	O
or	O
512	O
K	O
words	O
of	O
64-bit	B-Device
memory	O
.	O
</s>
<s>
The	O
AFP	O
was	O
the	O
successor	O
to	O
the	O
Flexible	O
Processor	B-General_Concept
(	O
FP	O
)	O
,	O
whose	O
design	O
development	O
started	O
in	O
1972	O
under	O
black-project	O
circumstances	O
targeted	O
at	O
processing	O
radar	O
and	O
photo	O
image	O
data	O
.	O
</s>
<s>
The	O
FP	O
control	O
unit	O
had	O
a	O
hardware	O
network	O
for	O
conditional	B-General_Concept
microinstruction	I-General_Concept
execution	I-General_Concept
,	O
with	O
four	O
mask	O
registers	B-General_Concept
and	O
a	O
condition-hold	O
register	O
;	O
three	O
bits	O
in	O
the	O
microinstruction	B-Device
format	O
select	O
among	O
nearly	O
50	O
conditions	O
for	O
determining	O
execution	O
,	O
including	O
result	O
sign	O
and	O
overflow	O
,	O
I/O	B-General_Concept
conditions	O
,	O
and	O
loop	O
control	O
.	O
</s>
<s>
At	O
least	O
21	O
Cyberplus	O
multiprocessor	B-Operating_System
installations	O
were	O
operational	O
in	O
1986	O
.	O
</s>
<s>
These	O
parallel	O
processing	O
systems	O
include	O
from	O
1	O
to	O
256	O
Cyberplus	O
processors	O
providing	O
250	O
MFLOPS	O
each	O
,	O
which	O
are	O
connected	O
to	O
an	O
existing	O
Cyber	O
system	O
via	O
a	O
direct	O
memory	O
interconnect	O
architecture	O
(	O
MIA	O
)	O
,	O
this	O
was	O
available	O
on	O
NOS	B-Operating_System
2.2	O
for	O
the	O
Cyber	O
170/835	O
,	O
845	O
,	O
855	O
and	O
180/990	O
models	O
.	O
</s>
<s>
Physically	O
,	O
each	O
Cyberplus	O
processor	B-General_Concept
unit	O
was	O
of	O
typical	O
mainframe	B-Architecture
module	O
size	O
,	O
similar	O
to	O
the	O
Cyber	O
180	O
systems	O
,	O
with	O
the	O
exact	O
width	O
dependent	O
on	O
whether	O
the	O
optional	O
FPU	B-General_Concept
was	O
installed	O
,	O
and	O
weighed	O
approximately	O
1	O
tonne	O
.	O
</s>
<s>
A	O
fully	O
configured	O
256	O
processor	B-General_Concept
Cyberplus	O
system	O
would	O
have	O
a	O
theoretical	O
performance	O
of	O
64	O
GFLOPS	O
,	O
and	O
weigh	O
around	O
256	O
tonnes	O
.	O
</s>
<s>
The	O
Cyber	O
18	O
is	O
a	O
16-bit	O
minicomputer	B-Architecture
which	O
was	O
a	O
successor	O
to	O
the	O
CDC	B-Device
1700	I-Device
minicomputer	B-Architecture
.	O
</s>
<s>
One	O
noteworthy	O
application	O
is	O
as	O
the	O
basis	O
of	O
the	O
2550	O
—	O
a	O
communications	O
processor	B-General_Concept
used	O
by	O
CDC	B-Device
6000	I-Device
series	I-Device
and	O
Cyber	O
70/Cyber	O
170	O
mainframes	B-Architecture
.	O
</s>
<s>
STAOPS	O
also	O
produced	O
another	O
communication	O
processor	B-General_Concept
(	O
CP	O
)	O
,	O
used	O
in	O
networks	O
hosted	O
by	O
IBM	O
mainframes	B-Architecture
.	O
</s>
<s>
The	O
Cyber	O
18	O
was	O
generally	O
programmed	O
in	O
Pascal	B-Application
and	O
assembly	B-Language
language	I-Language
;	O
FORTRAN	B-Application
,	O
BASIC	O
,	O
and	O
RPG	B-Language
II	I-Language
were	O
also	O
available	O
.	O
</s>
<s>
Operating	O
systems	O
included	O
RTOS	O
(	O
Real-Time	O
Operating	O
System	O
)	O
,	O
MSOS	O
5	O
(	O
Mass	O
Storage	O
Operating	O
System	O
)	O
,	O
and	O
TIMESHARE	O
3	O
(	O
time-sharing	B-General_Concept
system	I-General_Concept
)	O
.	O
</s>
<s>
"	O
Cyber	O
18-17	O
"	O
was	O
just	O
a	O
new	O
name	O
for	O
the	O
System	O
17	O
,	O
based	O
on	O
the	O
1784	O
processor	B-General_Concept
.	O
</s>
<s>
Other	O
Cyber	O
18s	O
(	O
Cyber	O
18-05	O
,	O
18-10	O
,	O
18-20	O
,	O
and	O
18-30	O
)	O
had	O
microprogrammable	B-Device
processors	O
with	O
up	O
to	O
128K	O
words	O
of	O
memory	O
,	O
four	O
additional	O
general	O
registers	B-General_Concept
,	O
and	O
an	O
enhanced	O
instruction	O
set	O
.	O
</s>
<s>
The	O
MP32	O
had	O
the	O
Fortran	B-Application
math	O
runtime	O
library	O
package	O
built	O
into	O
its	O
microcode	B-Device
.	O
</s>
<s>
This	O
was	O
a	O
RISC	B-Architecture
processor	I-Architecture
(	O
reduced	B-Architecture
instruction	I-Architecture
set	I-Architecture
computer	I-Architecture
)	O
.	O
</s>
<s>
An	O
improved	O
version	O
known	O
as	O
the	O
Cyber	O
1000-2	O
with	O
the	O
Line	O
Termination	O
Sub-System	O
added	O
256	O
Zilog	B-General_Concept
Z80	I-General_Concept
microprocessors	B-Architecture
.	O
</s>
<s>
In	O
the	O
late	O
1980s	O
the	O
XN10	O
was	O
released	O
with	O
an	O
improved	O
processor	B-General_Concept
(	O
a	O
direct	O
memory	O
access	O
instruction	O
was	O
added	O
)	O
as	O
well	O
as	O
a	O
size	O
reduction	O
from	O
two	O
cabinets	O
to	O
one	O
.	O
</s>
<s>
The	O
Line	O
Termination	O
Sub-System	O
was	O
redesigned	O
to	O
use	O
the	O
improved	O
Z180	B-Device
microprocessor	B-Architecture
(	O
the	O
Buffer	O
Controller	O
card	O
,	O
Programmable	O
Line	O
Controller	O
card	O
and	O
two	O
Communication	O
Line	O
Interface	O
cards	O
were	O
incorporated	O
on	O
to	O
a	O
single	O
card	O
)	O
.	O
</s>
