<s>
Column	O
address	O
strobe	O
latency	O
,	O
also	O
called	O
CAS	B-Architecture
latency	I-Architecture
or	O
CL	O
,	O
is	O
the	O
delay	O
in	O
clock	O
cycles	O
between	O
the	O
READ	O
command	O
and	O
the	O
moment	O
data	O
is	O
available	O
.	O
</s>
<s>
Dynamic	O
RAM	B-Architecture
is	O
arranged	O
in	O
a	O
rectangular	O
array	O
.	O
</s>
<s>
Sending	O
a	O
logical	O
high	O
signal	O
along	O
a	O
given	O
row	O
enables	O
the	O
MOSFETs	B-Architecture
present	O
in	O
that	O
row	O
,	O
connecting	O
each	O
storage	O
capacitor	O
to	O
its	O
corresponding	O
vertical	O
bit	O
line	O
.	O
</s>
<s>
The	O
CAS	B-Architecture
latency	I-Architecture
is	O
the	O
delay	O
between	O
the	O
time	O
at	O
which	O
the	O
column	O
address	O
and	O
the	O
column	O
address	O
strobe	O
signal	O
are	O
presented	O
to	O
the	O
memory	O
module	O
and	O
the	O
time	O
at	O
which	O
the	O
corresponding	O
data	O
is	O
made	O
available	O
by	O
the	O
memory	O
module	O
.	O
</s>
<s>
Synchronous	O
DRAM	O
,	O
however	O
,	O
has	O
a	O
CAS	B-Architecture
latency	I-Architecture
that	O
is	O
dependent	O
upon	O
the	O
clock	O
rate	O
.	O
</s>
<s>
Accordingly	O
,	O
the	O
CAS	B-Architecture
latency	I-Architecture
of	O
an	O
SDRAM	O
memory	O
module	O
is	O
specified	O
in	O
clock	O
ticks	O
instead	O
of	O
absolute	O
time	O
.	O
</s>
<s>
Because	O
memory	O
modules	O
have	O
multiple	O
internal	O
banks	O
,	O
and	O
data	O
can	O
be	O
output	O
from	O
one	O
during	O
access	O
latency	O
for	O
another	O
,	O
the	O
output	O
pins	O
can	O
be	O
kept	O
100%	O
busy	O
regardless	O
of	O
the	O
CAS	B-Architecture
latency	I-Architecture
through	O
pipelining	B-General_Concept
;	O
the	O
maximum	O
attainable	O
bandwidth	O
is	O
determined	O
solely	O
by	O
the	O
clock	O
speed	O
.	O
</s>
<s>
Unfortunately	O
,	O
this	O
maximum	O
bandwidth	O
can	O
only	O
be	O
attained	O
if	O
the	O
address	O
of	O
the	O
data	O
to	O
be	O
read	O
is	O
known	O
long	O
enough	O
in	O
advance	O
;	O
if	O
the	O
address	O
of	O
the	O
data	O
being	O
accessed	O
is	O
not	O
predictable	O
,	O
pipeline	B-General_Concept
stalls	I-General_Concept
can	O
occur	O
,	O
resulting	O
in	O
a	O
loss	O
of	O
bandwidth	O
.	O
</s>
<s>
For	O
a	O
completely	O
unknown	O
memory	O
access	O
(	O
AKA	O
Random	O
access	O
)	O
,	O
the	O
relevant	O
latency	O
is	O
the	O
time	O
to	O
close	O
any	O
open	O
row	O
,	O
plus	O
the	O
time	O
to	O
open	O
the	O
desired	O
row	O
,	O
followed	O
by	O
the	O
CAS	B-Architecture
latency	I-Architecture
to	O
read	O
data	O
from	O
it	O
.	O
</s>
<s>
Due	O
to	O
spatial	B-General_Concept
locality	I-General_Concept
,	O
however	O
,	O
it	O
is	O
common	O
to	O
access	O
several	O
words	O
in	O
the	O
same	O
row	O
.	O
</s>
<s>
In	O
this	O
case	O
,	O
the	O
CAS	B-Architecture
latency	I-Architecture
alone	O
determines	O
the	O
elapsed	O
time	O
.	O
</s>
<s>
Because	O
modern	O
DRAM	O
modules	O
 '	O
CAS	B-Architecture
latencies	I-Architecture
are	O
specified	O
in	O
clock	O
ticks	O
instead	O
of	O
time	O
,	O
when	O
comparing	O
latencies	O
at	O
different	O
clock	O
speeds	O
,	O
latencies	O
must	O
be	O
translated	O
into	O
absolute	O
times	O
to	O
make	O
a	O
fair	O
comparison	O
;	O
a	O
higher	O
numerical	O
CAS	B-Architecture
latency	I-Architecture
may	O
still	O
be	O
less	O
time	O
if	O
the	O
clock	O
is	O
faster	O
.	O
</s>
<s>
Likewise	O
,	O
a	O
memory	O
module	O
which	O
is	O
underclocked	B-Device
could	O
have	O
its	O
CAS	B-Architecture
latency	I-Architecture
cycle	O
count	O
reduced	O
to	O
preserve	O
the	O
same	O
CAS	B-Architecture
latency	I-Architecture
time	O
.	O
</s>
<s>
Double	O
data	O
rate	O
(	O
DDR	O
)	O
RAM	B-Architecture
performs	O
two	O
transfers	O
per	O
clock	O
cycle	O
,	O
and	O
it	O
is	O
usually	O
described	O
by	O
this	O
transfer	O
rate	O
.	O
</s>
<s>
Because	O
the	O
CAS	B-Architecture
latency	I-Architecture
is	O
specified	O
in	O
clock	O
cycles	O
,	O
and	O
not	O
transfers	O
(	O
which	O
occur	O
on	O
both	O
the	O
rising	O
and	O
falling	O
edges	O
of	O
the	O
clock	O
)	O
,	O
it	O
is	O
important	O
to	O
ensure	O
it	O
is	O
the	O
clock	O
rate	O
(	O
half	O
of	O
the	O
transfer	O
rate	O
)	O
which	O
is	O
being	O
used	O
to	O
compute	O
CAS	B-Architecture
latency	I-Architecture
times	O
.	O
</s>
<s>
A	O
modern	O
microprocessor	O
might	O
have	O
a	O
cache	B-General_Concept
line	I-General_Concept
size	O
of	O
64	O
bytes	O
,	O
requiring	O
eight	O
transfers	O
from	O
a	O
64-bit-wide	O
(	O
eight	O
bytes	O
)	O
memory	O
to	O
fill	O
.	O
</s>
<s>
The	O
CAS	B-Architecture
latency	I-Architecture
can	O
only	O
accurately	O
measure	O
the	O
time	O
to	O
transfer	O
the	O
first	O
word	O
of	O
memory	O
;	O
the	O
time	O
to	O
transfer	O
all	O
eight	O
words	O
depends	O
on	O
the	O
data	O
transfer	O
rate	O
as	O
well	O
.	O
</s>
