<s>
C-slow	O
retiming	B-Application
is	O
a	O
technique	O
used	O
in	O
conjunction	O
with	O
retiming	B-Application
to	O
improve	O
throughput	O
of	O
a	O
digital	O
circuit	O
.	O
</s>
<s>
Each	O
register	B-General_Concept
in	O
a	O
circuit	O
is	O
replaced	O
by	O
a	O
set	O
of	O
C	O
registers	O
(	O
in	O
series	O
)	O
.	O
</s>
<s>
C-slowing	B-General_Concept
by	O
itself	O
increases	O
latency	O
,	O
but	O
throughput	O
remains	O
the	O
same	O
.	O
</s>
<s>
Increasing	O
the	O
number	O
of	O
registers	O
allows	O
optimization	O
of	O
the	O
circuit	O
through	O
retiming	B-Application
to	O
reduce	O
the	O
clock	O
period	O
of	O
the	O
circuit	O
.	O
</s>
<s>
Thus	O
,	O
for	O
computations	O
that	O
can	O
be	O
multi-threaded	O
,	O
combining	O
C-slowing	B-General_Concept
with	O
retiming	B-Application
can	O
increase	O
the	O
throughput	O
of	O
the	O
circuit	O
,	O
with	O
little	O
,	O
or	O
in	O
the	O
best	O
case	O
,	O
no	O
increase	O
in	O
latency	O
.	O
</s>
<s>
Since	O
registers	O
are	O
relatively	O
plentiful	O
in	O
FPGAs	B-Architecture
,	O
this	O
technique	O
is	O
typically	O
applied	O
to	O
circuits	O
implemented	O
with	O
FPGAs	B-Architecture
.	O
</s>
