<s>
In	O
computer	B-General_Concept
architecture	I-General_Concept
,	O
a	O
bus	O
(	O
shortened	O
form	O
of	O
the	O
Latin	O
omnibus	O
,	O
and	O
historically	O
also	O
called	O
data	B-General_Concept
highway	I-General_Concept
or	O
databus	O
)	O
is	O
a	O
communication	O
system	O
that	O
transfers	O
data	B-General_Concept
between	O
components	O
inside	O
a	O
computer	O
,	O
or	O
between	O
computers	O
.	O
</s>
<s>
This	O
expression	O
covers	O
all	O
related	O
hardware	B-Architecture
components	O
(	O
wire	O
,	O
optical	B-Architecture
fiber	I-Architecture
,	O
etc	O
.	O
)	O
</s>
<s>
Early	O
computer	B-General_Concept
buses	I-General_Concept
were	O
parallel	O
electrical	O
wires	O
with	O
multiple	O
hardware	B-Architecture
connections	O
,	O
but	O
the	O
term	O
is	O
now	O
used	O
for	O
any	O
physical	O
arrangement	O
that	O
provides	O
the	O
same	O
logical	O
function	O
as	O
a	O
parallel	O
electrical	O
busbar	O
.	O
</s>
<s>
Modern	O
computer	B-General_Concept
buses	I-General_Concept
can	O
use	O
both	O
parallel	O
and	O
bit	B-Protocol
serial	I-Protocol
connections	O
,	O
and	O
can	O
be	O
wired	O
in	O
either	O
a	O
multidrop	B-Architecture
(	O
electrical	O
parallel	O
)	O
or	O
daisy	B-Application
chain	I-Application
topology	O
,	O
or	O
connected	O
by	O
switched	O
hubs	O
,	O
as	O
in	O
the	O
case	O
of	O
Universal	B-Protocol
Serial	I-Protocol
Bus	I-Protocol
(	O
USB	B-Protocol
)	O
.	O
</s>
<s>
Computer	B-General_Concept
systems	I-General_Concept
generally	O
consist	O
of	O
three	O
main	O
parts	O
:	O
</s>
<s>
The	O
central	B-General_Concept
processing	I-General_Concept
unit	I-General_Concept
(	O
CPU	B-General_Concept
)	O
that	O
processes	O
data	B-General_Concept
,	O
</s>
<s>
I/O	B-General_Concept
(	O
input/output	B-General_Concept
)	O
devices	O
as	O
peripherals	B-Device
that	O
communicate	O
with	O
the	O
outside	O
world	O
.	O
</s>
<s>
An	O
early	O
computer	O
might	O
contain	O
a	O
hand-wired	O
CPU	B-General_Concept
of	O
vacuum	O
tubes	O
,	O
a	O
magnetic	B-General_Concept
drum	I-General_Concept
for	O
main	O
memory	O
,	O
and	O
a	O
punch	O
tape	O
and	O
printer	O
for	O
reading	O
and	O
writing	O
data	B-General_Concept
respectively	O
.	O
</s>
<s>
A	O
modern	O
system	O
might	O
have	O
a	O
multi-core	B-Architecture
CPU	I-Architecture
,	O
DDR4	O
SDRAM	O
for	O
memory	O
,	O
a	O
solid-state	B-Device
drive	I-Device
for	O
secondary	O
storage	O
,	O
a	O
graphics	B-Device
card	I-Device
and	O
LCD	B-Device
as	O
a	O
display	O
system	O
,	O
a	O
mouse	B-Device
and	O
keyboard	B-Device
for	O
interaction	O
,	O
and	O
a	O
Wi-Fi	O
connection	O
for	O
networking	B-Architecture
.	O
</s>
<s>
In	O
both	O
examples	O
,	O
computer	B-General_Concept
buses	I-General_Concept
of	O
one	O
form	O
or	O
another	O
move	O
data	B-General_Concept
between	O
all	O
of	O
these	O
devices	O
.	O
</s>
<s>
In	O
most	O
traditional	O
computer	B-General_Concept
architectures	I-General_Concept
,	O
the	O
CPU	B-General_Concept
and	O
main	O
memory	O
tend	O
to	O
be	O
tightly	O
coupled	O
.	O
</s>
<s>
A	O
microprocessor	B-Architecture
conventionally	O
is	O
a	O
single	O
chip	O
which	O
has	O
a	O
number	O
of	O
electrical	B-Protocol
connections	I-Protocol
on	O
its	O
pins	O
that	O
can	O
be	O
used	O
to	O
select	O
an	O
"	B-General_Concept
address	I-General_Concept
"	I-General_Concept
in	O
the	O
main	O
memory	O
and	O
another	O
set	O
of	O
pins	O
to	O
read	O
and	O
write	O
the	O
data	B-General_Concept
stored	O
at	O
that	O
location	O
.	O
</s>
<s>
In	O
most	O
cases	O
,	O
the	O
CPU	B-General_Concept
and	O
memory	O
share	O
signalling	O
characteristics	O
and	O
operate	O
in	O
synchrony	O
.	O
</s>
<s>
The	O
bus	O
connecting	O
the	O
CPU	B-General_Concept
and	O
memory	O
is	O
one	O
of	O
the	O
defining	O
characteristics	O
of	O
the	O
system	O
,	O
and	O
often	O
referred	O
to	O
simply	O
as	O
the	O
system	B-Architecture
bus	I-Architecture
.	O
</s>
<s>
It	O
is	O
possible	O
to	O
allow	O
peripherals	B-Device
to	O
communicate	O
with	O
memory	O
in	O
the	O
same	O
fashion	O
,	O
attaching	O
adapters	B-Device
,	O
either	O
on	O
the	O
motherboard	B-Device
or	O
in	O
the	O
form	O
of	O
expansion	B-Device
cards	I-Device
,	O
directly	O
to	O
the	O
system	B-Architecture
bus	I-Architecture
.	O
</s>
<s>
This	O
is	O
commonly	O
accomplished	O
through	O
some	O
sort	O
of	O
standardized	O
electrical	B-Protocol
connector	I-Protocol
,	O
several	O
of	O
these	O
forming	O
the	O
expansion	B-Device
bus	I-Device
or	O
local	B-Architecture
bus	I-Architecture
.	O
</s>
<s>
However	O
,	O
as	O
the	O
performance	O
differences	O
between	O
the	O
CPU	B-General_Concept
and	O
peripherals	B-Device
varies	O
widely	O
,	O
some	O
solution	O
is	O
generally	O
needed	O
to	O
ensure	O
that	O
peripherals	B-Device
do	O
not	O
slow	O
overall	O
system	O
performance	O
.	O
</s>
<s>
Others	O
use	O
smart	O
controllers	O
to	O
place	O
the	O
data	B-General_Concept
directly	O
in	O
memory	O
,	O
a	O
concept	O
known	O
as	O
direct	B-General_Concept
memory	I-General_Concept
access	I-General_Concept
.	O
</s>
<s>
As	O
the	O
number	O
of	O
potential	O
peripherals	B-Device
grew	O
,	O
using	O
an	O
expansion	B-Device
card	I-Device
for	O
every	O
peripheral	O
became	O
increasingly	O
untenable	O
.	O
</s>
<s>
This	O
has	O
led	O
to	O
the	O
introduction	O
of	O
bus	O
systems	O
designed	O
specifically	O
to	O
support	O
multiple	O
peripherals	B-Device
.	O
</s>
<s>
Common	O
examples	O
are	O
the	O
SATA	O
ports	O
in	O
modern	O
computers	O
,	O
which	O
allow	O
a	O
number	O
of	O
hard	B-Device
drives	I-Device
to	O
be	O
connected	O
without	O
the	O
need	O
for	O
a	O
card	O
.	O
</s>
<s>
However	O
,	O
these	O
high-performance	O
systems	O
are	O
generally	O
too	O
expensive	O
to	O
implement	O
in	O
low-end	O
devices	O
,	O
like	O
a	O
mouse	B-Device
.	O
</s>
<s>
This	O
has	O
led	O
to	O
the	O
parallel	O
development	O
of	O
a	O
number	O
of	O
low-performance	O
bus	O
systems	O
for	O
these	O
solutions	O
,	O
the	O
most	O
common	O
example	O
being	O
the	O
standardized	O
Universal	B-Protocol
Serial	I-Protocol
Bus	I-Protocol
(	O
USB	B-Protocol
)	O
.	O
</s>
<s>
In	O
modern	O
systems	O
the	O
performance	O
difference	O
between	O
the	O
CPU	B-General_Concept
and	O
main	O
memory	O
has	O
grown	O
so	O
great	O
that	O
increasing	O
amounts	O
of	O
high-speed	O
memory	O
is	O
built	O
directly	O
into	O
the	O
CPU	B-General_Concept
,	O
known	O
as	O
a	O
cache	B-General_Concept
.	O
</s>
<s>
In	O
such	O
systems	O
,	O
CPUs	O
communicate	O
using	O
high-performance	O
buses	O
that	O
operate	O
at	O
speeds	O
much	O
greater	O
than	O
memory	O
,	O
and	O
communicate	O
with	O
memory	O
using	O
protocols	O
similar	O
to	O
those	O
used	O
solely	O
for	O
peripherals	B-Device
in	O
the	O
past	O
.	O
</s>
<s>
These	O
system	O
buses	O
are	O
also	O
used	O
to	O
communicate	O
with	O
most	O
(	O
or	O
all	O
)	O
other	O
peripherals	B-Device
,	O
through	O
adaptors	O
,	O
which	O
in	O
turn	O
talk	O
to	O
other	O
peripherals	B-Device
and	O
controllers	O
.	O
</s>
<s>
Such	O
systems	O
are	O
architecturally	O
more	O
similar	O
to	O
multicomputers	B-Architecture
,	O
communicating	O
over	O
a	O
bus	O
rather	O
than	O
a	O
network	B-Architecture
.	O
</s>
<s>
In	O
these	O
cases	O
,	O
expansion	O
buses	O
are	O
entirely	O
separate	O
and	O
no	O
longer	O
share	O
any	O
architecture	O
with	O
their	O
host	O
CPU	B-General_Concept
(	O
and	O
may	O
in	O
fact	O
support	O
many	O
different	O
CPUs	O
,	O
as	O
is	O
the	O
case	O
with	O
PCI	B-Protocol
)	O
.	O
</s>
<s>
What	O
would	O
have	O
formerly	O
been	O
a	O
system	B-Architecture
bus	I-Architecture
is	O
now	O
often	O
known	O
as	O
a	O
front-side	B-Architecture
bus	I-Architecture
.	O
</s>
<s>
Other	O
common	O
categorization	O
systems	O
are	O
based	O
on	O
the	O
bus	O
's	O
primary	O
role	O
,	O
connecting	O
devices	O
internally	O
or	O
externally	O
,	O
PCI	B-Protocol
vs.	O
SCSI	B-Architecture
for	O
instance	O
.	O
</s>
<s>
However	O
,	O
many	O
common	O
modern	O
bus	O
systems	O
can	O
be	O
used	O
for	O
both	O
;	O
SATA	O
and	O
the	O
associated	O
eSATA	O
are	O
one	O
example	O
of	O
a	O
system	O
that	O
would	O
formerly	O
be	O
described	O
as	O
internal	O
,	O
while	O
certain	O
automotive	O
applications	O
use	O
the	O
primarily	O
external	O
IEEE	B-Protocol
1394	I-Protocol
in	O
a	O
fashion	O
more	O
similar	O
to	O
a	O
system	B-Architecture
bus	I-Architecture
.	O
</s>
<s>
Other	O
examples	O
,	O
like	O
InfiniBand	B-Architecture
and	O
I²C	O
were	O
designed	O
from	O
the	O
start	O
to	O
be	O
used	O
both	O
internally	O
and	O
externally	O
.	O
</s>
<s>
The	O
internal	B-General_Concept
bus	I-General_Concept
,	O
also	O
known	O
as	O
internal	O
data	B-General_Concept
bus	I-General_Concept
,	O
memory	O
bus	O
,	O
system	B-Architecture
bus	I-Architecture
or	O
front-side	B-Architecture
bus	I-Architecture
,	O
connects	O
all	O
the	O
internal	O
components	O
of	O
a	O
computer	O
,	O
such	O
as	O
CPU	B-General_Concept
and	O
memory	O
,	O
to	O
the	O
motherboard	B-Device
.	O
</s>
<s>
Internal	O
data	B-General_Concept
buses	I-General_Concept
are	O
also	O
referred	O
to	O
as	O
local	O
buses	O
,	O
because	O
they	O
are	O
intended	O
to	O
connect	O
to	O
local	O
devices	O
.	O
</s>
<s>
The	O
external	O
bus	O
,	O
or	O
expansion	B-Device
bus	I-Device
,	O
is	O
made	O
up	O
of	O
the	O
electronic	O
pathways	O
that	O
connect	O
the	O
different	O
external	B-Device
devices	I-Device
,	O
such	O
as	O
printer	O
etc.	O
,	O
to	O
the	O
computer	O
.	O
</s>
<s>
An	O
address	O
bus	O
is	O
a	O
bus	O
that	O
is	O
used	O
to	O
specify	O
a	O
physical	B-General_Concept
address	I-General_Concept
.	O
</s>
<s>
When	O
a	O
processor	B-General_Concept
or	O
DMA-enabled	O
device	O
needs	O
to	O
read	O
or	O
write	O
to	O
a	O
memory	B-General_Concept
location	I-General_Concept
,	O
it	O
specifies	O
that	O
memory	B-General_Concept
location	I-General_Concept
on	O
the	O
address	O
bus	O
(	O
the	O
value	O
to	O
be	O
read	O
or	O
written	O
is	O
sent	O
on	O
the	O
data	B-General_Concept
bus	I-General_Concept
)	O
.	O
</s>
<s>
For	O
example	O
,	O
a	O
system	O
with	O
a	O
32-bit	O
address	O
bus	O
can	O
address	O
232	O
(	O
4,294,967,296	O
)	O
memory	B-General_Concept
locations	I-General_Concept
.	O
</s>
<s>
If	O
each	O
memory	B-General_Concept
location	I-General_Concept
holds	O
one	O
byte	O
,	O
the	O
addressable	O
memory	O
space	O
is	O
4	O
GiB	O
.	O
</s>
<s>
Beginning	O
with	O
the	O
Mostek	O
4096	O
DRAM	O
,	O
address	O
multiplexing	O
implemented	O
with	O
multiplexers	B-Protocol
became	O
common	O
.	O
</s>
<s>
For	O
example	O
,	O
a	O
32-bit	O
address	O
bus	O
can	O
be	O
implemented	O
by	O
using	O
16	O
lines	O
and	O
sending	O
the	O
first	O
half	O
of	O
the	O
memory	B-General_Concept
address	I-General_Concept
,	O
immediately	O
followed	O
by	O
the	O
second	O
half	O
memory	B-General_Concept
address	I-General_Concept
.	O
</s>
<s>
Typically	O
two	O
additional	O
pins	O
in	O
the	O
control	B-Architecture
bus	I-Architecture
--	O
a	O
row-address	O
strobe	O
(	O
RAS	O
)	O
and	O
the	O
column-address	O
strobe	O
(	O
CAS	O
)	O
--	O
are	O
used	O
to	O
tell	O
the	O
DRAM	O
whether	O
the	O
address	O
bus	O
is	O
currently	O
sending	O
the	O
first	O
half	O
of	O
the	O
memory	B-General_Concept
address	I-General_Concept
or	O
the	O
second	O
half	O
.	O
</s>
<s>
This	O
is	O
the	O
case	O
,	O
for	O
instance	O
,	O
with	O
the	O
VESA	O
Local	B-Architecture
Bus	I-Architecture
which	O
lacks	O
the	O
two	O
least	O
significant	O
bits	O
,	O
limiting	O
this	O
bus	O
to	O
aligned	B-Application
32-bit	O
transfers	O
.	O
</s>
<s>
The	O
memory	O
bus	O
is	O
the	O
bus	O
which	O
connects	O
the	O
main	O
memory	O
to	O
the	O
memory	B-General_Concept
controller	I-General_Concept
in	O
computer	B-General_Concept
systems	I-General_Concept
.	O
</s>
<s>
Originally	O
,	O
general-purpose	O
buses	O
like	O
VMEbus	B-Architecture
and	O
the	O
S-100	B-Architecture
bus	I-Architecture
were	O
used	O
,	O
but	O
to	O
reduce	O
latency	O
,	O
modern	O
memory	O
buses	O
are	O
designed	O
to	O
connect	O
directly	O
to	O
DRAM	O
chips	O
,	O
and	O
thus	O
are	O
designed	O
by	O
chip	O
standards	O
bodies	O
such	O
as	O
JEDEC	O
.	O
</s>
<s>
An	O
exception	O
is	O
the	O
Fully	B-General_Concept
Buffered	I-General_Concept
DIMM	I-General_Concept
which	O
,	O
despite	O
being	O
carefully	O
designed	O
to	O
minimize	O
the	O
effect	O
,	O
has	O
been	O
criticized	O
for	O
its	O
higher	O
latency	O
.	O
</s>
<s>
Buses	O
can	O
be	O
parallel	O
buses	O
,	O
which	O
carry	O
data	B-General_Concept
words	O
in	O
parallel	O
on	O
multiple	O
wires	O
,	O
or	O
serial	O
buses	O
,	O
which	O
carry	O
data	B-General_Concept
in	O
bit-serial	B-Protocol
form	O
.	O
</s>
<s>
The	O
addition	O
of	O
extra	O
power	O
and	O
control	O
connections	O
,	O
differential	O
drivers	O
,	O
and	O
data	B-General_Concept
connections	O
in	O
each	O
direction	O
usually	O
means	O
that	O
most	O
serial	O
buses	O
have	O
more	O
conductors	O
than	O
the	O
minimum	O
of	O
one	O
used	O
in	O
1-Wire	O
and	O
UNI/O	O
.	O
</s>
<s>
As	O
data	B-General_Concept
rates	O
increase	O
,	O
the	O
problems	O
of	O
timing	O
skew	O
,	O
power	O
consumption	O
,	O
electromagnetic	O
interference	O
and	O
crosstalk	O
across	O
parallel	O
buses	O
become	O
more	O
and	O
more	O
difficult	O
to	O
circumvent	O
.	O
</s>
<s>
Often	O
,	O
a	O
serial	O
bus	O
can	O
be	O
operated	O
at	O
higher	O
overall	O
data	B-General_Concept
rates	O
than	O
a	O
parallel	O
bus	O
,	O
despite	O
having	O
fewer	O
electrical	B-Protocol
connections	I-Protocol
,	O
because	O
a	O
serial	O
bus	O
inherently	O
has	O
no	O
timing	O
skew	O
or	O
crosstalk	O
.	O
</s>
<s>
USB	B-Protocol
,	O
FireWire	B-Protocol
,	O
and	O
Serial	O
ATA	O
are	O
examples	O
of	O
this	O
.	O
</s>
<s>
Multidrop	B-Architecture
connections	O
do	O
not	O
work	O
well	O
for	O
fast	O
serial	O
buses	O
,	O
so	O
most	O
modern	O
serial	O
buses	O
use	O
daisy-chain	O
or	O
hub	O
designs	O
.	O
</s>
<s>
Network	B-Architecture
connections	O
such	O
as	O
Ethernet	O
are	O
not	O
generally	O
regarded	O
as	O
buses	O
,	O
although	O
the	O
difference	O
is	O
largely	O
conceptual	O
rather	O
than	O
practical	O
.	O
</s>
<s>
An	O
attribute	O
generally	O
used	O
to	O
characterize	O
a	O
bus	O
is	O
that	O
power	O
is	O
provided	O
by	O
the	O
bus	O
for	O
the	O
connected	O
hardware	B-Architecture
.	O
</s>
<s>
This	O
excludes	O
,	O
as	O
buses	O
,	O
schemes	O
such	O
as	O
serial	O
RS-232	O
,	O
parallel	O
Centronics	O
,	O
IEEE	B-Device
1284	I-Device
interfaces	O
and	O
Ethernet	O
,	O
since	O
these	O
devices	O
also	O
needed	O
separate	O
power	O
supplies	O
.	O
</s>
<s>
Universal	B-Protocol
Serial	I-Protocol
Bus	I-Protocol
devices	O
may	O
use	O
the	O
bus	O
supplied	O
power	O
,	O
but	O
often	O
use	O
a	O
separate	O
power	O
source	O
.	O
</s>
<s>
This	O
distinction	O
is	O
exemplified	O
by	O
a	O
telephone	O
system	O
with	O
a	O
connected	O
modem	B-Application
,	O
where	O
the	O
RJ11	O
connection	O
and	O
associated	O
modulated	O
signalling	O
scheme	O
is	O
not	O
considered	O
a	O
bus	O
,	O
and	O
is	O
analogous	O
to	O
an	O
Ethernet	O
connection	O
.	O
</s>
<s>
However	O
,	O
this	O
distinctionthat	O
power	O
is	O
provided	O
by	O
the	O
busis	O
not	O
the	O
case	O
in	O
many	O
avionic	O
systems	O
,	O
where	O
data	B-General_Concept
connections	O
such	O
as	O
ARINC	O
429	O
,	O
ARINC	B-Architecture
629	I-Architecture
,	O
MIL-STD-1553B	O
(	O
STANAG	O
3838	O
)	O
,	O
and	O
EFABus	O
(	O
STANAG	O
3910	O
)	O
are	O
commonly	O
referred	O
to	O
as	O
“	O
data	B-General_Concept
buses	I-General_Concept
”	O
or	O
,	O
sometimes	O
,	O
"	O
databuses	O
"	O
.	O
</s>
<s>
Such	O
avionic	O
data	B-General_Concept
buses	I-General_Concept
are	O
usually	O
characterized	O
by	O
having	O
several	O
equipments	O
or	O
Line	O
Replaceable	O
Items/Units	O
(	O
LRI/LRUs	O
)	O
connected	O
to	O
a	O
common	O
,	O
shared	O
media	O
.	O
</s>
<s>
have	O
a	O
single	O
source	O
LRI/LRU	O
or	O
,	O
as	O
with	O
ARINC	B-Architecture
629	I-Architecture
,	O
MIL-STD-1553B	O
,	O
and	O
STANAG	O
3910	O
,	O
be	O
duplex	O
,	O
allow	O
all	O
the	O
connected	O
LRI/LRUs	O
to	O
act	O
,	O
at	O
different	O
times	O
(	O
half	O
duplex	O
)	O
,	O
as	O
transmitters	O
and	O
receivers	O
of	O
data	B-General_Concept
.	O
</s>
<s>
The	O
simplest	O
system	B-Architecture
bus	I-Architecture
has	O
completely	O
separate	O
input	B-General_Concept
data	I-General_Concept
lines	O
,	O
output	O
data	B-General_Concept
lines	O
,	O
and	O
address	O
lines	O
.	O
</s>
<s>
To	O
reduce	O
cost	O
,	O
most	O
microcomputers	B-Architecture
have	O
a	O
bidirectional	O
data	B-General_Concept
bus	I-General_Concept
,	O
re-using	O
the	O
same	O
wires	O
for	O
input	B-General_Concept
and	I-General_Concept
output	I-General_Concept
at	O
different	O
times	O
.	O
</s>
<s>
Some	O
processors	O
use	O
a	O
dedicated	O
wire	O
for	O
each	O
bit	O
of	O
the	O
address	O
bus	O
,	O
data	B-General_Concept
bus	I-General_Concept
,	O
and	O
the	O
control	B-Architecture
bus	I-Architecture
.	O
</s>
<s>
For	O
example	O
,	O
the	O
64-pin	O
STEbus	B-Architecture
is	O
composed	O
of	O
8	O
physical	O
wires	O
dedicated	O
to	O
the	O
8-bit	O
data	B-General_Concept
bus	I-General_Concept
,	O
20	O
physical	O
wires	O
dedicated	O
to	O
the	O
20-bit	O
address	O
bus	O
,	O
21	O
physical	O
wires	O
dedicated	O
to	O
the	O
control	B-Architecture
bus	I-Architecture
,	O
and	O
15	O
physical	O
wires	O
dedicated	O
to	O
various	O
power	O
buses	O
.	O
</s>
<s>
Bus	O
multiplexing	O
requires	O
fewer	O
wires	O
,	O
which	O
reduces	O
costs	O
in	O
many	O
early	O
microprocessors	B-Architecture
and	O
DRAM	O
chips	O
.	O
</s>
<s>
Another	O
multiplexing	O
scheme	O
re-uses	O
the	O
address	O
bus	O
pins	O
as	O
the	O
data	B-General_Concept
bus	I-General_Concept
pins	O
,	O
an	O
approach	O
used	O
by	O
conventional	B-Protocol
PCI	I-Protocol
and	O
the	O
8086	B-General_Concept
.	O
</s>
<s>
The	O
various	O
"	O
serial	O
buses	O
"	O
can	O
be	O
seen	O
as	O
the	O
ultimate	O
limit	O
of	O
multiplexing	O
,	O
sending	O
each	O
of	O
the	O
address	O
bits	O
and	O
each	O
of	O
the	O
data	B-General_Concept
bits	O
,	O
one	O
at	O
a	O
time	O
,	O
through	O
a	O
single	O
pin	O
(	O
or	O
a	O
single	O
differential	O
pair	O
)	O
.	O
</s>
<s>
Over	O
time	O
,	O
several	O
groups	O
of	O
people	O
worked	O
on	O
various	O
computer	B-General_Concept
bus	I-General_Concept
standards	O
,	O
including	O
the	O
IEEE	O
Bus	O
Architecture	O
Standards	O
Committee	O
(	O
BASC	O
)	O
,	O
the	O
IEEE	O
"	O
Superbus	O
"	O
study	O
group	O
,	O
the	O
open	O
microprocessor	B-Architecture
initiative	O
(	O
OMI	O
)	O
,	O
the	O
open	O
microsystems	O
initiative	O
(	O
OMI	O
)	O
,	O
the	O
"	O
Gang	B-Device
of	I-Device
Nine	I-Device
"	O
that	O
developed	O
EISA	B-Device
,	O
etc	O
.	O
</s>
<s>
Early	O
computer	B-General_Concept
buses	I-General_Concept
were	O
bundles	O
of	O
wire	O
that	O
attached	O
computer	B-General_Concept
memory	I-General_Concept
and	O
peripherals	B-Device
.	O
</s>
<s>
Almost	O
always	O
,	O
there	O
was	O
one	O
bus	O
for	O
memory	O
,	O
and	O
one	O
or	O
more	O
separate	O
buses	O
for	O
peripherals	B-Device
.	O
</s>
<s>
One	O
of	O
the	O
first	O
complications	O
was	O
the	O
use	O
of	O
interrupts	B-Application
.	O
</s>
<s>
Early	O
computer	O
programs	O
performed	O
I/O	B-General_Concept
by	O
waiting	B-Operating_System
in	I-Operating_System
a	I-Operating_System
loop	I-Operating_System
for	O
the	O
peripheral	O
to	O
become	O
ready	O
.	O
</s>
<s>
Also	O
,	O
if	O
the	O
program	O
attempted	O
to	O
perform	O
those	O
other	O
tasks	O
,	O
it	O
might	O
take	O
too	O
long	O
for	O
the	O
program	O
to	O
check	O
again	O
,	O
resulting	O
in	O
loss	O
of	O
data	B-General_Concept
.	O
</s>
<s>
Engineers	O
thus	O
arranged	O
for	O
the	O
peripherals	B-Device
to	O
interrupt	B-Application
the	O
CPU	B-General_Concept
.	O
</s>
<s>
The	O
interrupts	B-Application
had	O
to	O
be	O
prioritized	O
,	O
because	O
the	O
CPU	B-General_Concept
can	O
only	O
execute	O
code	O
for	O
one	O
peripheral	O
at	O
a	O
time	O
,	O
and	O
some	O
devices	O
are	O
more	O
time-critical	O
than	O
others	O
.	O
</s>
<s>
High-end	O
systems	O
introduced	O
the	O
idea	O
of	O
channel	B-Device
controllers	I-Device
,	O
which	O
were	O
essentially	O
small	O
computers	O
dedicated	O
to	O
handling	O
the	O
input	B-General_Concept
and	I-General_Concept
output	I-General_Concept
of	O
a	O
given	O
bus	O
.	O
</s>
<s>
IBM	O
introduced	O
these	O
on	O
the	O
IBM	B-Device
709	I-Device
in	O
1958	O
,	O
and	O
they	O
became	O
a	O
common	O
feature	O
of	O
their	O
platforms	O
.	O
</s>
<s>
Other	O
high-performance	O
vendors	O
like	O
Control	O
Data	B-General_Concept
Corporation	O
implemented	O
similar	O
designs	O
.	O
</s>
<s>
Generally	O
,	O
the	O
channel	B-Device
controllers	I-Device
would	O
do	O
their	O
best	O
to	O
run	O
all	O
of	O
the	O
bus	O
operations	O
internally	O
,	O
moving	O
data	B-General_Concept
when	O
the	O
CPU	B-General_Concept
was	O
known	O
to	O
be	O
busy	O
elsewhere	O
if	O
possible	O
,	O
and	O
only	O
using	O
interrupts	B-Application
when	O
necessary	O
.	O
</s>
<s>
This	O
greatly	O
reduced	O
CPU	B-General_Concept
load	O
,	O
and	O
provided	O
better	O
overall	O
system	O
performance	O
.	O
</s>
<s>
To	O
provide	O
modularity	O
,	O
memory	O
and	O
I/O	B-General_Concept
buses	O
can	O
be	O
combined	O
into	O
a	O
unified	O
system	B-Architecture
bus	I-Architecture
.	O
</s>
<s>
The	O
simple	O
way	O
to	O
prioritize	O
interrupts	B-Application
or	O
bus	O
access	O
was	O
with	O
a	O
daisy	B-Application
chain	I-Application
.	O
</s>
<s>
Digital	O
Equipment	O
Corporation	O
(	O
DEC	O
)	O
further	O
reduced	O
cost	O
for	O
mass-produced	O
minicomputers	B-Architecture
,	O
and	O
mapped	B-Architecture
peripherals	I-Architecture
into	O
the	O
memory	O
bus	O
,	O
so	O
that	O
the	O
input	B-General_Concept
and	I-General_Concept
output	I-General_Concept
devices	O
appeared	O
to	O
be	O
memory	B-General_Concept
locations	I-General_Concept
.	O
</s>
<s>
This	O
was	O
implemented	O
in	O
the	O
Unibus	B-Device
of	O
the	O
PDP-11	B-Device
around	O
1969	O
.	O
</s>
<s>
Early	O
microcomputer	B-Architecture
bus	O
systems	O
were	O
essentially	O
a	O
passive	B-Architecture
backplane	I-Architecture
connected	O
directly	O
or	O
through	O
buffer	O
amplifiers	O
to	O
the	O
pins	O
of	O
the	O
CPU	B-General_Concept
.	O
</s>
<s>
Memory	O
and	O
other	O
devices	O
would	O
be	O
added	O
to	O
the	O
bus	O
using	O
the	O
same	O
address	O
and	O
data	B-General_Concept
pins	O
as	O
the	O
CPU	B-General_Concept
itself	O
used	O
,	O
connected	O
in	O
parallel	O
.	O
</s>
<s>
Communication	O
was	O
controlled	O
by	O
the	O
CPU	B-General_Concept
,	O
which	O
read	O
and	O
wrote	O
data	B-General_Concept
from	O
the	O
devices	O
as	O
if	O
they	O
are	O
blocks	O
of	O
memory	O
,	O
using	O
the	O
same	O
instructions	O
,	O
all	O
timed	O
by	O
a	O
central	O
clock	O
controlling	O
the	O
speed	O
of	O
the	O
CPU	B-General_Concept
.	O
</s>
<s>
Still	O
,	O
devices	O
interrupted	O
the	O
CPU	B-General_Concept
by	O
signaling	O
on	O
separate	O
CPU	B-General_Concept
pins	O
.	O
</s>
<s>
For	O
instance	O
,	O
a	O
disk	B-Device
drive	I-Device
controller	O
would	O
signal	O
the	O
CPU	B-General_Concept
that	O
new	O
data	B-General_Concept
was	O
ready	O
to	O
be	O
read	O
,	O
at	O
which	O
point	O
the	O
CPU	B-General_Concept
would	O
move	O
the	O
data	B-General_Concept
by	O
reading	O
the	O
"	O
memory	B-General_Concept
location	I-General_Concept
"	O
that	O
corresponded	O
to	O
the	O
disk	B-Device
drive	I-Device
.	O
</s>
<s>
Almost	O
all	O
early	O
microcomputers	B-Architecture
were	O
built	O
in	O
this	O
fashion	O
,	O
starting	O
with	O
the	O
S-100	B-Architecture
bus	I-Architecture
in	O
the	O
Altair	B-Architecture
8800	I-Architecture
computer	O
system	O
.	O
</s>
<s>
In	O
some	O
instances	O
,	O
most	O
notably	O
in	O
the	O
IBM	B-Device
PC	I-Device
,	O
although	O
similar	O
physical	O
architecture	O
can	O
be	O
employed	O
,	O
instructions	O
to	O
access	O
peripherals	B-Device
(	O
in	O
and	O
out	O
)	O
and	O
memory	O
(	O
mov	O
and	O
others	O
)	O
have	O
not	O
been	O
made	O
uniform	O
at	O
all	O
,	O
and	O
still	O
generate	O
distinct	O
CPU	B-General_Concept
signals	O
,	O
that	O
could	O
be	O
used	O
to	O
implement	O
a	O
separate	O
I/O	B-General_Concept
bus	I-General_Concept
.	O
</s>
<s>
Increasing	O
the	O
speed	O
of	O
the	O
CPU	B-General_Concept
becomes	O
harder	O
,	O
because	O
the	O
speed	O
of	O
all	O
the	O
devices	O
must	O
increase	O
as	O
well	O
.	O
</s>
<s>
When	O
it	O
is	O
not	O
practical	O
or	O
economical	O
to	O
have	O
all	O
devices	O
as	O
fast	O
as	O
the	O
CPU	B-General_Concept
,	O
the	O
CPU	B-General_Concept
must	O
either	O
enter	O
a	O
wait	B-Device
state	I-Device
,	O
or	O
work	O
at	O
a	O
slower	O
clock	O
frequency	O
temporarily	O
,	O
to	O
talk	O
to	O
other	O
devices	O
in	O
the	O
computer	O
.	O
</s>
<s>
While	O
acceptable	O
in	O
embedded	B-Architecture
systems	I-Architecture
,	O
this	O
problem	O
was	O
not	O
tolerated	O
for	O
long	O
in	O
general-purpose	O
,	O
user-expandable	O
computers	O
.	O
</s>
<s>
Typically	O
each	O
added	O
expansion	B-Device
card	I-Device
requires	O
many	O
jumpers	B-Device
in	O
order	O
to	O
set	O
memory	O
addresses	O
,	O
I/O	B-General_Concept
addresses	O
,	O
interrupt	B-Application
priorities	O
,	O
and	O
interrupt	B-Application
numbers	O
.	O
</s>
<s>
"	O
Second	O
generation	O
"	O
bus	O
systems	O
like	O
NuBus	B-Device
addressed	O
some	O
of	O
these	O
problems	O
.	O
</s>
<s>
They	O
typically	O
separated	O
the	O
computer	O
into	O
two	O
"	O
worlds	O
"	O
,	O
the	O
CPU	B-General_Concept
and	O
memory	O
on	O
one	O
side	O
,	O
and	O
the	O
various	O
devices	O
on	O
the	O
other	O
.	O
</s>
<s>
A	O
bus	O
controller	O
accepted	O
data	B-General_Concept
from	O
the	O
CPU	B-General_Concept
side	O
to	O
be	O
moved	O
to	O
the	O
peripherals	B-Device
side	O
,	O
thus	O
shifting	O
the	O
communications	O
protocol	O
burden	O
from	O
the	O
CPU	B-General_Concept
itself	O
.	O
</s>
<s>
This	O
allowed	O
the	O
CPU	B-General_Concept
and	O
memory	O
side	O
to	O
evolve	O
separately	O
from	O
the	O
device	O
bus	O
,	O
or	O
just	O
"	O
bus	O
"	O
.	O
</s>
<s>
Devices	O
on	O
the	O
bus	O
could	O
talk	O
to	O
each	O
other	O
with	O
no	O
CPU	B-General_Concept
intervention	O
.	O
</s>
<s>
These	O
buses	O
also	O
often	O
addressed	O
speed	O
issues	O
by	O
being	O
"	O
bigger	O
"	O
in	O
terms	O
of	O
the	O
size	O
of	O
the	O
data	B-General_Concept
path	O
,	O
moving	O
from	O
8-bit	O
parallel	O
buses	O
in	O
the	O
first	O
generation	O
,	O
to	O
16	O
or	O
32-bit	O
in	O
the	O
second	O
,	O
as	O
well	O
as	O
adding	O
software	O
setup	O
(	O
now	O
standardised	O
as	O
Plug-n-play	B-Device
)	O
to	O
supplant	O
or	O
replace	O
the	O
jumpers	B-Device
.	O
</s>
<s>
While	O
the	O
CPU	B-General_Concept
was	O
now	O
isolated	O
and	O
could	O
increase	O
speed	O
,	O
CPUs	O
and	O
memory	O
continued	O
to	O
increase	O
in	O
speed	O
much	O
faster	O
than	O
the	O
buses	O
they	O
talked	O
to	O
.	O
</s>
<s>
The	O
result	O
was	O
that	O
the	O
bus	O
speeds	O
were	O
now	O
very	O
much	O
slower	O
than	O
what	O
a	O
modern	O
system	O
needed	O
,	O
and	O
the	O
machines	O
were	O
left	O
starved	O
for	O
data	B-General_Concept
.	O
</s>
<s>
A	O
particularly	O
common	O
example	O
of	O
this	O
problem	O
was	O
that	O
video	B-Device
cards	I-Device
quickly	O
outran	O
even	O
the	O
newer	O
bus	O
systems	O
like	O
PCI	B-Protocol
,	O
and	O
computers	O
began	O
to	O
include	O
AGP	B-Architecture
just	O
to	O
drive	O
the	O
video	B-Device
card	I-Device
.	O
</s>
<s>
By	O
2004	O
AGP	B-Architecture
was	O
outgrown	O
again	O
by	O
high-end	O
video	B-Device
cards	I-Device
and	O
other	O
peripherals	B-Device
and	O
has	O
been	O
replaced	O
by	O
the	O
new	O
PCI	B-Protocol
Express	O
bus	O
.	O
</s>
<s>
An	O
increasing	O
number	O
of	O
external	B-Device
devices	I-Device
started	O
employing	O
their	O
own	O
bus	O
systems	O
as	O
well	O
.	O
</s>
<s>
When	O
disk	B-Device
drives	I-Device
were	O
first	O
introduced	O
,	O
they	O
would	O
be	O
added	O
to	O
the	O
machine	O
with	O
a	O
card	O
plugged	O
into	O
the	O
bus	O
,	O
which	O
is	O
why	O
computers	O
have	O
so	O
many	O
slots	O
on	O
the	O
bus	O
.	O
</s>
<s>
But	O
through	O
the	O
1980s	O
and	O
1990s	O
,	O
new	O
systems	O
like	O
SCSI	B-Architecture
and	O
IDE	B-Protocol
were	O
introduced	O
to	O
serve	O
this	O
need	O
,	O
leaving	O
most	O
slots	O
in	O
modern	O
systems	O
empty	O
.	O
</s>
<s>
"	O
Third	O
generation	O
"	O
buses	O
have	O
been	O
emerging	O
into	O
the	O
market	O
since	O
about	O
2001	O
,	O
including	O
HyperTransport	B-Device
and	O
InfiniBand	B-Architecture
.	O
</s>
<s>
This	O
can	O
lead	O
to	O
complex	O
problems	O
when	O
trying	O
to	O
service	O
different	O
requests	O
,	O
so	O
much	O
of	O
the	O
work	O
on	O
these	O
systems	O
concerns	O
software	O
design	O
,	O
as	O
opposed	O
to	O
the	O
hardware	B-Architecture
itself	O
.	O
</s>
<s>
In	O
general	O
,	O
these	O
third	O
generation	O
buses	O
tend	O
to	O
look	O
more	O
like	O
a	O
network	B-Architecture
than	O
the	O
original	O
concept	O
of	O
a	O
bus	O
,	O
with	O
a	O
higher	O
protocol	O
overhead	O
needed	O
than	O
early	O
systems	O
,	O
while	O
also	O
allowing	O
multiple	O
devices	O
to	O
use	O
the	O
bus	O
at	O
once	O
.	O
</s>
<s>
Buses	O
such	O
as	O
Wishbone	B-Architecture
have	O
been	O
developed	O
by	O
the	O
open	O
source	O
hardware	B-Architecture
movement	O
in	O
an	O
attempt	O
to	O
further	O
remove	O
legal	O
and	O
patent	O
constraints	O
from	O
computer	B-General_Concept
design	I-General_Concept
.	O
</s>
<s>
The	O
Compute	O
Express	O
Link	O
(	O
CXL	O
)	O
is	O
an	O
open	O
standard	O
interconnect	B-Architecture
for	O
high-speed	O
CPU-to-device	O
and	O
CPU-to-memory	O
,	O
designed	O
to	O
accelerate	O
next-generation	O
data	B-Operating_System
center	I-Operating_System
performance	O
.	O
</s>
<s>
OPTi	O
local	B-Architecture
bus	I-Architecture
used	O
on	O
early	O
Intel	B-General_Concept
80486	I-General_Concept
motherboards	B-Device
.	O
</s>
<s>
Parallel	B-Protocol
ATA	I-Protocol
(	O
also	O
known	O
as	O
Advanced	B-Protocol
Technology	I-Protocol
Attachment	I-Protocol
,	O
ATA	O
,	O
PATA	B-Protocol
,	O
IDE	B-Protocol
,	O
EIDE	O
,	O
ATAPI	O
,	O
etc	O
.	O
</s>
<s>
STD	B-Architecture
Bus	I-Architecture
(	O
for	O
STD-80	B-Architecture
 [ 8-bit ] 	O
and	O
STD32	O
 [ 16-/32-bit ] 	O
)	O
,	O
</s>
<s>
Unibus	B-Device
,	O
a	O
proprietary	O
bus	O
developed	O
by	O
Digital	O
Equipment	O
Corporation	O
for	O
their	O
PDP-11	B-Device
and	O
early	O
VAX	B-Device
computers	O
.	O
</s>
<s>
Q-Bus	B-Architecture
,	O
a	O
proprietary	O
bus	O
developed	O
by	O
Digital	O
Equipment	O
Corporation	O
for	O
their	O
PDP	B-Device
and	O
later	O
VAX	B-Device
computers	O
.	O
</s>
<s>
Many	O
field	O
buses	O
are	O
serial	O
data	B-General_Concept
buses	I-General_Concept
(	O
not	O
to	O
be	O
confused	O
with	O
the	O
parallel	O
"	O
data	B-General_Concept
bus	I-General_Concept
"	O
section	O
of	O
a	O
system	B-Architecture
bus	I-Architecture
or	O
expansion	B-Device
card	I-Device
)	O
,	O
several	O
of	O
which	O
use	O
the	O
RS-485	O
electrical	O
characteristics	O
and	O
then	O
specify	O
their	O
own	O
protocol	O
and	O
connector	O
:	O
</s>
