<s>
Burst	B-Architecture
mode	I-Architecture
is	O
a	O
generic	O
electronics	O
term	O
referring	O
to	O
any	O
situation	O
in	O
which	O
a	O
device	O
is	O
transmitting	O
data	O
repeatedly	O
without	O
going	O
through	O
all	O
the	O
steps	O
required	O
to	O
transmit	O
each	O
piece	O
of	O
data	O
in	O
a	O
separate	O
transaction	O
.	O
</s>
<s>
The	O
main	O
advantage	O
of	O
burst	B-Architecture
mode	I-Architecture
over	O
single	O
mode	O
is	O
that	O
the	O
burst	B-Architecture
mode	I-Architecture
typically	O
increases	O
the	O
throughput	O
of	O
data	O
transfer	O
.	O
</s>
<s>
In	O
case	O
of	O
burst	B-Architecture
mode	I-Architecture
,	O
it	O
is	O
usually	O
more	O
efficient	O
if	O
you	O
allow	O
a	O
master	O
to	O
complete	O
a	O
known	O
length	O
transfer	O
sequence	O
.	O
</s>
<s>
Here	O
the	O
sequential	O
latency	O
is	O
same	O
in	O
both	O
single	O
mode	O
and	O
burst	B-Architecture
mode	I-Architecture
,	O
but	O
the	O
total	O
initial	O
latency	O
is	O
decreased	O
in	O
burst	B-Architecture
mode	I-Architecture
,	O
since	O
the	O
initial	O
delay	O
(	O
usually	O
depends	O
on	O
FSM	B-Architecture
for	O
the	O
protocol	O
)	O
is	O
caused	O
only	O
once	O
in	O
burst	B-Architecture
mode	I-Architecture
.	O
</s>
<s>
Hence	O
the	O
total	O
latency	O
of	O
the	O
burst	B-Architecture
transfer	I-Architecture
is	O
reduced	O
,	O
and	O
hence	O
the	O
data	O
transfer	O
throughput	O
is	O
increased	O
.	O
</s>
<s>
A	O
beat	O
in	O
a	O
burst	B-Architecture
transfer	I-Architecture
is	O
the	O
number	O
of	O
write	O
(	O
or	O
read	O
)	O
transfers	O
from	O
master	O
to	O
slave	O
,	O
that	O
takes	O
place	O
continuously	O
in	O
a	O
transaction	O
.	O
</s>
<s>
In	O
a	O
burst	B-Architecture
transfer	I-Architecture
,	O
the	O
address	O
for	O
write	O
or	O
read	O
transfer	O
is	O
just	O
an	O
incremental	O
value	O
of	O
previous	O
address	O
.	O
</s>
<s>
Hence	O
in	O
a	O
4-beat	O
incremental	O
burst	B-Architecture
transfer	I-Architecture
(	O
write	O
or	O
read	O
)	O
,	O
if	O
the	O
starting	O
address	O
is	O
'	O
A	O
 '	O
,	O
then	O
the	O
consecutive	O
addresses	O
will	O
be	O
'	O
A+m	O
 '	O
,	O
'	O
A+2*m	O
 '	O
,	O
'	O
A+3*m	O
 '	O
.	O
</s>
<s>
Similarly	O
,	O
in	O
a	O
8-beat	O
incremental	O
burst	B-Architecture
transfer	I-Architecture
(	O
write	O
or	O
read	O
)	O
,	O
the	O
addresses	O
will	O
be	O
'	O
A	O
 '	O
,	O
'	O
A+n	O
 '	O
,	O
'	O
A+2*n	O
 '	O
,	O
'	O
A+3*n	O
 '	O
,	O
'	O
A+4*n	O
 '	O
,	O
'	O
A+5*n	O
 '	O
,	O
'	O
A+6*n	O
 '	O
,	O
'	O
A+7*n	O
 '	O
.	O
</s>
<s>
Q	O
:	O
-	O
A	O
certain	O
SoC	O
master	O
uses	O
a	O
burst	B-Architecture
mode	I-Architecture
to	O
communicate	O
(	O
write	O
or	O
read	O
)	O
with	O
its	O
peripheral	O
slave	O
.	O
</s>
<s>
Calculate	O
the	O
total	O
latency	O
for	O
single	O
mode	O
(	O
no-burst	O
mode	O
)	O
,	O
4-beat	O
burst	B-Architecture
mode	I-Architecture
,	O
8-beat	O
burst	B-Architecture
mode	I-Architecture
and	O
16-beat	O
burst	B-Architecture
mode	I-Architecture
.	O
</s>
<s>
Calculate	O
the	O
throughput	O
factor	O
increase	O
for	O
each	O
burst	B-Architecture
mode	I-Architecture
.	O
</s>
<s>
The	O
usual	O
reason	O
for	O
having	O
a	O
burst	B-Architecture
mode	I-Architecture
capability	O
,	O
or	O
using	O
burst	B-Architecture
mode	I-Architecture
,	O
is	O
to	O
increase	O
data	O
throughput	O
.	O
</s>
<s>
The	O
steps	O
left	O
out	O
while	O
performing	O
a	O
burst	B-Architecture
mode	I-Architecture
transaction	O
may	O
include	O
:	O
</s>
<s>
In	O
the	O
case	O
of	O
DMA	B-General_Concept
,	O
the	O
DMA	B-General_Concept
controller	I-General_Concept
and	O
the	O
device	O
are	O
given	O
exclusive	O
access	O
to	O
the	O
bus	O
without	O
interruption	O
;	O
the	O
CPU	O
is	O
also	O
freed	O
from	O
handling	O
device	O
interrupts	O
.	O
</s>
<s>
The	O
actual	O
manner	O
in	O
which	O
burst	B-Architecture
modes	I-Architecture
work	O
varies	O
from	O
one	O
type	O
of	O
device	O
to	O
another	O
;	O
however	O
,	O
devices	O
that	O
have	O
some	O
sort	O
of	O
a	O
standard	O
burst	B-Architecture
mode	I-Architecture
include	O
the	O
following	O
:	O
</s>
