<s>
In	O
computer	B-General_Concept
architecture	I-General_Concept
,	O
a	O
branch	B-General_Concept
target	I-General_Concept
predictor	I-General_Concept
is	O
the	O
part	O
of	O
a	O
processor	O
that	O
predicts	O
the	O
target	O
of	O
a	O
taken	O
conditional	B-General_Concept
branch	I-General_Concept
or	O
an	O
unconditional	B-General_Concept
branch	I-General_Concept
instruction	I-General_Concept
before	O
the	O
target	B-General_Concept
of	I-General_Concept
the	I-General_Concept
branch	I-General_Concept
instruction	I-General_Concept
is	O
computed	O
by	O
the	O
execution	O
unit	O
of	O
the	O
processor	O
.	O
</s>
<s>
Branch	O
target	O
prediction	O
is	O
not	O
the	O
same	O
as	O
branch	B-General_Concept
prediction	I-General_Concept
which	O
attempts	O
to	O
guess	O
whether	O
a	O
conditional	B-General_Concept
branch	I-General_Concept
will	O
be	O
taken	O
or	O
not-taken	O
(	O
i.e.	O
,	O
binary	O
)	O
.	O
</s>
<s>
In	O
more	O
parallel	B-Operating_System
processor	I-Operating_System
designs	O
,	O
as	O
the	O
instruction	O
cache	O
latency	O
grows	O
longer	O
and	O
the	O
fetch	O
width	O
grows	O
wider	O
,	O
branch	O
target	O
extraction	O
becomes	O
a	O
bottleneck	O
.	O
</s>
<s>
If	O
it	O
were	O
not	O
fast	O
enough	O
,	O
it	O
could	O
be	O
parallelized	B-Operating_System
,	O
by	O
predicting	O
target	O
addresses	O
of	O
target	O
branches	O
.	O
</s>
