<s>
In	O
computer	B-General_Concept
architecture	I-General_Concept
,	O
a	O
branch	B-General_Concept
predictor	I-General_Concept
is	O
a	O
digital	O
circuit	O
that	O
tries	O
to	O
guess	O
which	O
way	O
a	O
branch	B-General_Concept
(	O
e.g.	O
,	O
an	O
if	B-Language
–	I-Language
then	I-Language
–	I-Language
else	I-Language
structure	I-Language
)	O
will	O
go	O
before	O
this	O
is	O
known	O
definitively	O
.	O
</s>
<s>
The	O
purpose	O
of	O
the	O
branch	B-General_Concept
predictor	I-General_Concept
is	O
to	O
improve	O
the	O
flow	O
in	O
the	O
instruction	B-General_Concept
pipeline	I-General_Concept
.	O
</s>
<s>
Branch	B-General_Concept
predictors	I-General_Concept
play	O
a	O
critical	O
role	O
in	O
achieving	O
high	O
performance	O
in	O
many	O
modern	O
pipelined	B-General_Concept
microprocessor	B-Architecture
architectures	O
such	O
as	O
x86	B-Operating_System
.	O
</s>
<s>
Two-way	O
branching	O
is	O
usually	O
implemented	O
with	O
a	O
conditional	B-General_Concept
jump	I-General_Concept
instruction	O
.	O
</s>
<s>
A	O
conditional	B-General_Concept
jump	I-General_Concept
can	O
either	O
be	O
"	O
taken	O
"	O
and	O
jump	O
to	O
a	O
different	O
place	O
in	O
program	O
memory	O
,	O
or	O
it	O
can	O
be	O
"	O
not	O
taken	O
"	O
and	O
continue	O
execution	O
immediately	O
after	O
the	O
conditional	B-General_Concept
jump	I-General_Concept
.	O
</s>
<s>
It	O
is	O
not	O
known	O
for	O
certain	O
whether	O
a	O
conditional	B-General_Concept
jump	I-General_Concept
will	O
be	O
taken	O
or	O
not	O
taken	O
until	O
the	O
condition	O
has	O
been	O
calculated	O
and	O
the	O
conditional	B-General_Concept
jump	I-General_Concept
has	O
passed	O
the	O
execution	O
stage	O
in	O
the	O
instruction	B-General_Concept
pipeline	I-General_Concept
(	O
see	O
fig	O
.	O
</s>
<s>
Without	O
branch	B-General_Concept
prediction	I-General_Concept
,	O
the	O
processor	O
would	O
have	O
to	O
wait	O
until	O
the	O
conditional	B-General_Concept
jump	I-General_Concept
instruction	O
has	O
passed	O
the	O
execute	O
stage	O
before	O
the	O
next	B-General_Concept
instruction	I-General_Concept
can	O
enter	O
the	O
fetch	O
stage	O
in	O
the	O
pipeline	O
.	O
</s>
<s>
The	O
branch	B-General_Concept
predictor	I-General_Concept
attempts	O
to	O
avoid	O
this	O
waste	O
of	O
time	O
by	O
trying	O
to	O
guess	O
whether	O
the	O
conditional	B-General_Concept
jump	I-General_Concept
is	O
most	O
likely	O
to	O
be	O
taken	O
or	O
not	O
taken	O
.	O
</s>
<s>
The	O
branch	B-General_Concept
that	O
is	O
guessed	O
to	O
be	O
the	O
most	O
likely	O
is	O
then	O
fetched	O
and	O
speculatively	B-General_Concept
executed	I-General_Concept
.	O
</s>
<s>
If	O
it	O
is	O
later	O
detected	O
that	O
the	O
guess	O
was	O
wrong	O
,	O
then	O
the	O
speculatively	B-General_Concept
executed	I-General_Concept
or	O
partially	O
executed	O
instructions	O
are	O
discarded	O
and	O
the	O
pipeline	O
starts	O
over	O
with	O
the	O
correct	O
branch	B-General_Concept
,	O
incurring	O
a	O
delay	O
.	O
</s>
<s>
The	O
time	O
that	O
is	O
wasted	O
in	O
case	O
of	O
a	O
branch	B-General_Concept
misprediction	I-General_Concept
is	O
equal	O
to	O
the	O
number	O
of	O
stages	O
in	O
the	O
pipeline	O
from	O
the	O
fetch	O
stage	O
to	O
the	O
execute	O
stage	O
.	O
</s>
<s>
Modern	O
microprocessors	B-Architecture
tend	O
to	O
have	O
quite	O
long	O
pipelines	O
so	O
that	O
the	O
misprediction	B-General_Concept
delay	O
is	O
between	O
10	O
and	O
20	O
clock	O
cycles	O
.	O
</s>
<s>
As	O
a	O
result	O
,	O
making	O
a	O
pipeline	O
longer	O
increases	O
the	O
need	O
for	O
a	O
more	O
advanced	O
branch	B-General_Concept
predictor	I-General_Concept
.	O
</s>
<s>
The	O
first	O
time	O
a	O
conditional	B-General_Concept
jump	I-General_Concept
instruction	O
is	O
encountered	O
,	O
there	O
is	O
not	O
much	O
information	O
to	O
base	O
a	O
prediction	O
on	O
.	O
</s>
<s>
But	O
the	O
branch	B-General_Concept
predictor	I-General_Concept
keeps	O
records	O
of	O
whether	O
branches	O
are	O
taken	O
or	O
not	O
taken	O
.	O
</s>
<s>
When	O
it	O
encounters	O
a	O
conditional	B-General_Concept
jump	I-General_Concept
that	O
has	O
been	O
seen	O
several	O
times	O
before	O
,	O
then	O
it	O
can	O
base	O
the	O
prediction	O
on	O
the	O
history	O
.	O
</s>
<s>
The	O
branch	B-General_Concept
predictor	I-General_Concept
may	O
,	O
for	O
example	O
,	O
recognize	O
that	O
the	O
conditional	B-General_Concept
jump	I-General_Concept
is	O
taken	O
more	O
often	O
than	O
not	O
,	O
or	O
that	O
it	O
is	O
taken	O
every	O
second	O
time	O
.	O
</s>
<s>
Branch	B-General_Concept
prediction	I-General_Concept
is	O
not	O
the	O
same	O
as	O
branch	B-General_Concept
target	I-General_Concept
prediction	I-General_Concept
.	O
</s>
<s>
Branch	B-General_Concept
prediction	I-General_Concept
attempts	O
to	O
guess	O
whether	O
a	O
conditional	B-General_Concept
jump	I-General_Concept
will	O
be	O
taken	O
or	O
not	O
.	O
</s>
<s>
Branch	B-General_Concept
target	I-General_Concept
prediction	I-General_Concept
attempts	O
to	O
guess	O
the	O
target	O
of	O
a	O
taken	O
conditional	B-Language
or	O
unconditional	O
jump	O
before	O
it	O
is	O
computed	O
by	O
decoding	O
and	O
executing	O
the	O
instruction	O
itself	O
.	O
</s>
<s>
Branch	B-General_Concept
prediction	I-General_Concept
and	O
branch	B-General_Concept
target	I-General_Concept
prediction	I-General_Concept
are	O
often	O
combined	O
into	O
the	O
same	O
circuitry	O
.	O
</s>
<s>
Static	O
prediction	O
is	O
the	O
simplest	O
branch	B-General_Concept
prediction	I-General_Concept
technique	O
because	O
it	O
does	O
not	O
rely	O
on	O
information	O
about	O
the	O
dynamic	O
history	O
of	O
code	O
executing	O
.	O
</s>
<s>
Instead	O
,	O
it	O
predicts	O
the	O
outcome	O
of	O
a	O
branch	B-General_Concept
based	O
solely	O
on	O
the	O
branch	B-General_Concept
instruction	I-General_Concept
.	O
</s>
<s>
The	O
early	O
implementations	O
of	O
SPARC	B-Architecture
and	O
MIPS	B-Device
(	O
two	O
of	O
the	O
first	O
commercial	O
RISC	B-Architecture
architectures	I-Architecture
)	O
used	O
single-direction	O
static	O
branch	B-General_Concept
prediction	I-General_Concept
:	O
they	O
always	O
predict	O
that	O
a	O
conditional	B-General_Concept
jump	I-General_Concept
will	O
not	O
be	O
taken	O
,	O
so	O
they	O
always	O
fetch	O
the	O
next	O
sequential	O
instruction	O
.	O
</s>
<s>
Only	O
when	O
the	O
branch	B-General_Concept
or	O
jump	O
is	O
evaluated	O
and	O
found	O
to	O
be	O
taken	O
,	O
does	O
the	O
instruction	B-General_Concept
pointer	I-General_Concept
get	O
set	O
to	O
a	O
non-sequential	O
address	B-General_Concept
.	O
</s>
<s>
Both	O
CPUs	B-General_Concept
evaluate	O
branches	O
in	O
the	O
decode	O
stage	O
and	O
have	O
a	O
single	O
cycle	O
instruction	O
fetch	O
.	O
</s>
<s>
As	O
a	O
result	O
,	O
the	O
branch	B-General_Concept
target	O
recurrence	O
is	O
two	O
cycles	O
long	O
,	O
and	O
the	O
machine	O
always	O
fetches	O
the	O
instruction	O
immediately	O
after	O
any	O
taken	O
branch	B-General_Concept
.	O
</s>
<s>
Both	O
architectures	O
define	O
branch	B-General_Concept
delay	I-General_Concept
slots	I-General_Concept
in	O
order	O
to	O
utilize	O
these	O
fetched	O
instructions	O
.	O
</s>
<s>
A	O
backward	O
branch	B-General_Concept
is	O
one	O
that	O
has	O
a	O
target	O
address	B-General_Concept
that	O
is	O
lower	O
than	O
its	O
own	O
address	B-General_Concept
.	O
</s>
<s>
Some	O
processors	O
allow	O
branch	B-General_Concept
prediction	I-General_Concept
hints	O
to	O
be	O
inserted	O
into	O
the	O
code	O
to	O
tell	O
whether	O
the	O
static	O
prediction	O
should	O
be	O
taken	O
or	O
not	O
taken	O
.	O
</s>
<s>
The	O
Intel	B-General_Concept
Pentium	I-General_Concept
4	I-General_Concept
accepts	O
branch	B-General_Concept
prediction	I-General_Concept
hints	O
,	O
but	O
this	O
feature	O
was	O
abandoned	O
in	O
later	O
Intel	O
processors	O
.	O
</s>
<s>
Static	O
prediction	O
is	O
used	O
as	O
a	O
fall-back	O
technique	O
in	O
some	O
processors	O
with	O
dynamic	B-General_Concept
branch	I-General_Concept
prediction	I-General_Concept
when	O
dynamic	O
predictors	O
do	O
not	O
have	O
sufficient	O
information	O
to	O
use	O
.	O
</s>
<s>
Both	O
the	O
Motorola	O
MPC7450	O
(	O
G4e	O
)	O
and	O
the	O
Intel	B-General_Concept
Pentium	I-General_Concept
4	I-General_Concept
use	O
this	O
technique	O
as	O
a	O
fall-back	O
.	O
</s>
<s>
In	O
static	O
prediction	O
,	O
all	O
decisions	O
are	O
made	O
at	O
compile	B-Language
time	O
,	O
before	O
the	O
execution	O
of	O
the	O
program	O
.	O
</s>
<s>
Dynamic	B-General_Concept
branch	I-General_Concept
prediction	I-General_Concept
uses	O
information	O
about	O
taken	O
or	O
not	O
taken	O
branches	O
gathered	O
at	O
run-time	O
to	O
predict	O
the	O
outcome	O
of	O
a	O
branch	B-General_Concept
.	O
</s>
<s>
Using	O
a	O
random	O
or	O
pseudorandom	O
bit	O
(	O
a	O
pure	O
guess	O
)	O
would	O
guarantee	O
every	O
branch	B-General_Concept
a	O
50%	O
correct	O
prediction	O
rate	O
,	O
which	O
cannot	O
be	O
improved	O
(	O
or	O
worsened	O
)	O
by	O
reordering	O
instructions	O
.	O
</s>
<s>
(	O
With	O
the	O
simplest	O
static	O
prediction	O
of	O
"	O
assume	O
take	O
"	O
,	O
compilers	B-Language
can	O
reorder	O
instructions	O
to	O
get	O
better	O
than	O
50%	O
correct	O
prediction	O
.	O
)	O
</s>
<s>
Some	O
superscalar	B-General_Concept
processors	I-General_Concept
(	O
MIPS	B-Device
R8000	B-General_Concept
,	O
Alpha	B-General_Concept
21264	I-General_Concept
,	O
and	O
Alpha	B-General_Concept
21464	I-General_Concept
(	O
EV8	O
)	O
)	O
fetch	O
each	O
line	O
of	O
instructions	O
with	O
a	O
pointer	O
to	O
the	O
next	O
line	O
.	O
</s>
<s>
This	O
next-line	O
predictor	O
handles	O
branch	B-General_Concept
target	I-General_Concept
prediction	I-General_Concept
as	O
well	O
as	O
branch	B-General_Concept
direction	O
prediction	O
.	O
</s>
<s>
When	O
a	O
next-line	O
predictor	O
points	O
to	O
aligned	O
groups	O
of	O
2	O
,	O
4	O
,	O
or	O
8	O
instructions	O
,	O
the	O
branch	B-General_Concept
target	O
will	O
usually	O
not	O
be	O
the	O
first	O
instruction	O
fetched	O
,	O
and	O
so	O
the	O
initial	O
instructions	O
fetched	O
are	O
wasted	O
.	O
</s>
<s>
Assuming	O
for	O
simplicity	O
,	O
a	O
uniform	O
distribution	O
of	O
branch	B-General_Concept
targets	O
,	O
0.5	O
,	O
1.5	O
,	O
and	O
3.5	O
instructions	O
fetched	O
are	O
discarded	O
,	O
respectively	O
.	O
</s>
<s>
Since	O
the	O
branch	B-General_Concept
itself	O
will	O
generally	O
not	O
be	O
the	O
last	O
instruction	O
in	O
an	O
aligned	O
group	O
,	O
instructions	O
after	O
the	O
taken	O
branch	B-General_Concept
(	O
or	O
its	O
delay	B-General_Concept
slot	I-General_Concept
)	O
will	O
be	O
discarded	O
.	O
</s>
<s>
Once	O
again	O
,	O
assuming	O
a	O
uniform	O
distribution	O
of	O
branch	B-General_Concept
instruction	I-General_Concept
placements	O
,	O
0.5	O
,	O
1.5	O
,	O
and	O
3.5	O
instructions	O
fetched	O
are	O
discarded	O
.	O
</s>
<s>
The	O
discarded	O
instructions	O
at	O
the	O
branch	B-General_Concept
and	O
destination	O
lines	O
add	O
up	O
to	O
nearly	O
a	O
complete	O
fetch	O
cycle	O
,	O
even	O
for	O
a	O
single-cycle	O
next-line	O
predictor	O
.	O
</s>
<s>
A	O
1-bit	O
saturating	B-Algorithm
counter	I-Algorithm
(	O
essentially	O
a	O
flip-flop	B-General_Concept
)	O
records	O
the	O
last	O
outcome	O
of	O
the	O
branch	B-General_Concept
.	O
</s>
<s>
This	O
is	O
the	O
most	O
simple	O
version	O
of	O
dynamic	O
branch	B-General_Concept
predictor	I-General_Concept
possible	O
,	O
although	O
it	O
is	O
not	O
very	O
accurate	O
.	O
</s>
<s>
A	O
2-bit	O
saturating	B-Algorithm
counter	I-Algorithm
is	O
a	O
state	B-Architecture
machine	I-Architecture
with	O
four	O
states	O
:	O
</s>
<s>
When	O
a	O
branch	B-General_Concept
is	O
evaluated	O
,	O
the	O
corresponding	O
state	B-Architecture
machine	I-Architecture
is	O
updated	O
.	O
</s>
<s>
The	O
advantage	O
of	O
the	O
two-bit	O
counter	O
scheme	O
over	O
a	O
one-bit	O
scheme	O
is	O
that	O
a	O
conditional	B-General_Concept
jump	I-General_Concept
has	O
to	O
deviate	O
twice	O
from	O
what	O
it	O
has	O
done	O
most	O
in	O
the	O
past	O
before	O
the	O
prediction	O
changes	O
.	O
</s>
<s>
For	O
example	O
,	O
a	O
loop-closing	O
conditional	B-General_Concept
jump	I-General_Concept
is	O
mispredicted	O
once	O
rather	O
than	O
twice	O
.	O
</s>
<s>
The	O
original	O
,	O
non-MMX	O
Intel	B-Device
Pentium	I-Device
processor	I-Device
uses	O
a	O
saturating	B-Algorithm
counter	I-Algorithm
,	O
though	O
with	O
an	O
imperfect	O
implementation	O
.	O
</s>
<s>
On	O
the	O
SPEC'89	O
benchmarks	O
,	O
very	O
large	O
bimodal	O
predictors	O
saturate	O
at	O
93.5	O
%	O
correct	O
,	O
once	O
every	O
branch	B-General_Concept
maps	O
to	O
a	O
unique	O
counter	O
.	O
</s>
<s>
The	O
predictor	O
table	O
is	O
indexed	O
with	O
the	O
instruction	O
address	B-General_Concept
bits	O
,	O
so	O
that	O
the	O
processor	O
can	O
fetch	O
a	O
prediction	O
for	O
every	O
instruction	O
before	O
the	O
instruction	O
is	O
decoded	O
.	O
</s>
<s>
The	O
Two-Level	O
Branch	B-General_Concept
Predictor	I-General_Concept
,	O
also	O
referred	O
to	O
as	O
Correlation-Based	O
Branch	B-General_Concept
Predictor	I-General_Concept
,	O
uses	O
a	O
two-dimensional	O
table	O
of	O
counters	O
,	O
also	O
called	O
"	O
Pattern	O
History	O
Table	O
"	O
.	O
</s>
<s>
Conditional	B-General_Concept
jumps	I-General_Concept
that	O
are	O
taken	O
every	O
second	O
time	O
or	O
have	O
some	O
other	O
regularly	O
recurring	O
pattern	O
are	O
not	O
predicted	O
well	O
by	O
the	O
saturating	B-Algorithm
counter	I-Algorithm
.	O
</s>
<s>
A	O
two-level	O
adaptive	O
predictor	O
remembers	O
the	O
history	O
of	O
the	O
last	O
n	O
occurrences	O
of	O
the	O
branch	B-General_Concept
and	O
uses	O
one	O
saturating	B-Algorithm
counter	I-Algorithm
for	O
each	O
of	O
the	O
possible	O
2n	O
history	O
patterns	O
.	O
</s>
<s>
This	O
means	O
that	O
the	O
last	O
two	O
occurrences	O
of	O
the	O
branch	B-General_Concept
are	O
stored	O
in	O
a	O
two-bit	O
shift	B-General_Concept
register	I-General_Concept
.	O
</s>
<s>
This	O
branch	B-General_Concept
history	O
register	O
can	O
have	O
four	O
different	O
binary	O
values	O
,	O
00	O
,	O
01	O
,	O
10	O
,	O
and	O
11	O
,	O
where	O
zero	O
means	O
"	O
not	O
taken	O
"	O
and	O
one	O
means	O
"	O
taken	O
"	O
.	O
</s>
<s>
A	O
pattern	O
history	O
table	O
contains	O
four	O
entries	O
per	O
branch	B-General_Concept
,	O
one	O
for	O
each	O
of	O
the	O
22	O
=	O
4	O
possible	O
branch	B-General_Concept
histories	O
,	O
and	O
each	O
entry	O
in	O
the	O
table	O
contains	O
a	O
two-bit	O
saturating	B-Algorithm
counter	I-Algorithm
of	O
the	O
same	O
type	O
as	O
in	O
figure	O
2	O
for	O
each	O
branch	B-General_Concept
.	O
</s>
<s>
The	O
branch	B-General_Concept
history	O
register	O
is	O
used	O
for	O
choosing	O
which	O
of	O
the	O
four	O
saturating	O
counters	O
to	O
use	O
.	O
</s>
<s>
Assume	O
,	O
for	O
example	O
,	O
that	O
a	O
conditional	B-General_Concept
jump	I-General_Concept
is	O
taken	O
every	O
third	O
time	O
.	O
</s>
<s>
The	O
branch	B-General_Concept
sequence	O
is	O
001001001	O
...	O
</s>
<s>
Variants	O
of	O
this	O
prediction	O
method	O
are	O
used	O
in	O
most	O
modern	O
microprocessors	B-Architecture
.	O
</s>
<s>
A	O
two-level	O
branch	B-General_Concept
predictor	I-General_Concept
where	O
the	O
second	O
level	O
is	O
replaced	O
with	O
a	O
neural	B-Architecture
network	I-Architecture
has	O
been	O
proposed	O
.	O
</s>
<s>
A	O
local	O
branch	B-General_Concept
predictor	I-General_Concept
has	O
a	O
separate	O
history	O
buffer	O
for	O
each	O
conditional	B-General_Concept
jump	I-General_Concept
instruction	O
.	O
</s>
<s>
The	O
history	O
buffer	O
is	O
separate	O
for	O
each	O
conditional	B-General_Concept
jump	I-General_Concept
instruction	O
,	O
while	O
the	O
pattern	O
history	O
table	O
may	O
be	O
separate	O
as	O
well	O
or	O
it	O
may	O
be	O
shared	O
between	O
all	O
conditional	B-General_Concept
jumps	I-General_Concept
.	O
</s>
<s>
The	O
Intel	B-Device
Pentium	I-Device
MMX	O
,	O
Pentium	B-General_Concept
II	I-General_Concept
,	O
and	O
Pentium	B-General_Concept
III	I-General_Concept
have	O
local	O
branch	B-General_Concept
predictors	I-General_Concept
with	O
a	O
local	O
4-bit	O
history	O
and	O
a	O
local	O
pattern	O
history	O
table	O
with	O
16	O
entries	O
for	O
each	O
conditional	B-General_Concept
jump	I-General_Concept
.	O
</s>
<s>
On	O
the	O
SPEC'89	O
benchmarks	O
,	O
very	O
large	O
local	B-General_Concept
predictors	I-General_Concept
saturate	O
at	O
97.1	O
%	O
correct	O
.	O
</s>
<s>
A	O
global	O
branch	B-General_Concept
predictor	I-General_Concept
does	O
not	O
keep	O
a	O
separate	O
history	O
record	O
for	O
each	O
conditional	B-General_Concept
jump	I-General_Concept
.	O
</s>
<s>
Instead	O
it	O
keeps	O
a	O
shared	O
history	O
of	O
all	O
conditional	B-General_Concept
jumps	I-General_Concept
.	O
</s>
<s>
The	O
advantage	O
of	O
a	O
shared	O
history	O
is	O
that	O
any	O
correlation	O
between	O
different	O
conditional	B-General_Concept
jumps	I-General_Concept
is	O
part	O
of	O
making	O
the	O
predictions	O
.	O
</s>
<s>
The	O
disadvantage	O
is	O
that	O
the	O
history	O
is	O
diluted	O
by	O
irrelevant	O
information	O
if	O
the	O
different	O
conditional	B-General_Concept
jumps	I-General_Concept
are	O
uncorrelated	O
,	O
and	O
that	O
the	O
history	O
buffer	O
may	O
not	O
include	O
any	O
bits	O
from	O
the	O
same	O
branch	B-General_Concept
if	O
there	O
are	O
many	O
other	O
branches	O
in	O
between	O
.	O
</s>
<s>
This	O
scheme	O
is	O
better	O
than	O
the	O
saturating	B-Algorithm
counter	I-Algorithm
scheme	O
only	O
for	O
large	O
table	O
sizes	O
,	O
and	O
it	O
is	O
rarely	O
as	O
good	O
as	O
local	O
prediction	O
.	O
</s>
<s>
Hence	O
,	O
the	O
big	O
pattern	O
history	O
table	O
must	O
be	O
shared	O
among	O
all	O
conditional	B-General_Concept
jumps	I-General_Concept
.	O
</s>
<s>
A	O
two-level	O
adaptive	O
predictor	O
with	O
globally	O
shared	O
history	O
buffer	O
and	O
pattern	O
history	O
table	O
is	O
called	O
a	O
"	O
gshare	B-General_Concept
"	O
predictor	O
if	O
it	O
xors	O
the	O
global	O
history	O
and	O
branch	B-General_Concept
PC	O
,	O
and	O
"	O
gselect	O
"	O
if	O
it	O
concatenates	O
them	O
.	O
</s>
<s>
Global	O
branch	B-General_Concept
prediction	I-General_Concept
is	O
used	O
in	O
AMD	O
processors	O
,	O
and	O
in	O
Intel	B-Architecture
Pentium	I-Architecture
M	I-Architecture
,	O
Core	B-Device
,	O
Core	B-Device
2	I-Device
,	O
and	O
Silvermont-based	O
Atom	B-Device
processors	I-Device
.	O
</s>
<s>
An	O
alloyed	O
branch	B-General_Concept
predictor	I-General_Concept
combines	O
the	O
local	O
and	O
global	O
prediction	O
principles	O
by	O
concatenating	O
local	O
and	O
global	O
branch	B-General_Concept
histories	O
,	O
possibly	O
with	O
some	O
bits	O
from	O
the	O
program	B-General_Concept
counter	I-General_Concept
as	O
well	O
.	O
</s>
<s>
Tests	O
indicate	O
that	O
the	O
VIA	B-Device
Nano	I-Device
processor	O
may	O
be	O
using	O
this	O
technique	O
.	O
</s>
<s>
An	O
agree	O
predictor	O
is	O
a	O
two-level	O
adaptive	O
predictor	O
with	O
globally	O
shared	O
history	O
buffer	O
and	O
pattern	O
history	O
table	O
,	O
and	O
an	O
additional	O
local	O
saturating	B-Algorithm
counter	I-Algorithm
.	O
</s>
<s>
The	O
outputs	O
of	O
the	O
local	O
and	O
the	O
global	B-General_Concept
predictors	I-General_Concept
are	O
XORed	O
with	O
each	O
other	O
to	O
give	O
the	O
final	O
prediction	O
.	O
</s>
<s>
Scott	O
McFarling	O
proposed	O
combined	O
branch	B-General_Concept
prediction	I-General_Concept
in	O
his	O
1993	O
paper	O
.	O
</s>
<s>
On	O
the	O
SPEC'89	O
benchmarks	O
,	O
such	O
a	O
predictor	O
is	O
about	O
as	O
good	O
as	O
the	O
local	B-General_Concept
predictor	I-General_Concept
.	O
</s>
<s>
Predictors	O
like	O
gshare	B-General_Concept
use	O
multiple	O
table	O
entries	O
to	O
track	O
the	O
behavior	O
of	O
any	O
particular	O
branch	B-General_Concept
.	O
</s>
<s>
A	O
conditional	B-General_Concept
jump	I-General_Concept
that	O
controls	O
a	O
loop	O
is	O
best	O
predicted	O
with	O
a	O
special	O
loop	O
predictor	O
.	O
</s>
<s>
A	O
conditional	B-General_Concept
jump	I-General_Concept
in	O
the	O
bottom	O
of	O
a	O
loop	O
that	O
repeats	O
N	O
times	O
will	O
be	O
taken	O
N-1	O
times	O
and	O
then	O
not	O
taken	O
once	O
.	O
</s>
<s>
If	O
the	O
conditional	B-General_Concept
jump	I-General_Concept
is	O
placed	O
at	O
the	O
top	O
of	O
the	O
loop	O
,	O
it	O
will	O
be	O
not	O
taken	O
N-1	O
times	O
and	O
then	O
taken	O
once	O
.	O
</s>
<s>
A	O
conditional	B-General_Concept
jump	I-General_Concept
that	O
goes	O
many	O
times	O
one	O
way	O
and	O
then	O
the	O
other	O
way	O
once	O
is	O
detected	O
as	O
having	O
loop	O
behavior	O
.	O
</s>
<s>
Such	O
a	O
conditional	B-General_Concept
jump	I-General_Concept
can	O
be	O
predicted	O
easily	O
with	O
a	O
simple	O
counter	O
.	O
</s>
<s>
A	O
loop	O
predictor	O
is	O
part	O
of	O
a	O
hybrid	O
predictor	O
where	O
a	O
meta-predictor	O
detects	O
whether	O
the	O
conditional	B-General_Concept
jump	I-General_Concept
has	O
loop	O
behavior	O
.	O
</s>
<s>
An	O
indirect	B-Language
jump	I-Language
instruction	O
can	O
choose	O
among	O
more	O
than	O
two	O
branches	O
.	O
</s>
<s>
Some	O
processors	O
have	O
specialized	O
indirect	B-Language
branch	I-Language
predictors	O
.	O
</s>
<s>
Newer	O
processors	O
from	O
Intel	O
and	O
AMD	O
can	O
predict	O
indirect	B-Language
branches	I-Language
by	O
using	O
a	O
two-level	O
adaptive	O
predictor	O
.	O
</s>
<s>
The	O
zEC12	B-Device
and	O
later	O
z/Architecture	B-Device
processors	O
from	O
IBM	O
support	O
a	O
instruction	O
that	O
can	O
preload	O
the	O
branch	B-General_Concept
predictor	I-General_Concept
entry	O
for	O
a	O
given	O
instruction	O
with	O
a	O
branch	B-General_Concept
target	O
address	B-General_Concept
constructed	O
by	O
adding	O
the	O
contents	O
of	O
a	O
general-purpose	O
register	O
to	O
an	O
immediate	O
displacement	O
value	O
.	O
</s>
<s>
Processors	O
without	O
this	O
mechanism	O
will	O
simply	O
predict	O
an	O
indirect	B-Language
jump	I-Language
to	O
go	O
to	O
the	O
same	O
target	O
as	O
it	O
did	O
last	O
time	O
.	O
</s>
<s>
The	O
return	B-Language
instruction	I-Language
is	O
an	O
indirect	B-Language
jump	I-Language
that	O
reads	O
its	O
target	O
address	B-General_Concept
from	O
the	O
call	B-General_Concept
stack	I-General_Concept
.	O
</s>
<s>
Many	O
microprocessors	B-Architecture
have	O
a	O
separate	O
prediction	O
mechanism	O
for	O
return	B-Language
instructions	I-Language
.	O
</s>
<s>
This	O
mechanism	O
is	O
based	O
on	O
a	O
so-called	O
return	O
stack	O
buffer	O
,	O
which	O
is	O
a	O
local	O
mirror	O
of	O
the	O
call	B-General_Concept
stack	I-General_Concept
.	O
</s>
<s>
The	O
trade-off	O
between	O
fast	O
branch	B-General_Concept
prediction	I-General_Concept
and	O
good	O
branch	B-General_Concept
prediction	I-General_Concept
is	O
sometimes	O
dealt	O
with	O
by	O
having	O
two	O
branch	B-General_Concept
predictors	I-General_Concept
.	O
</s>
<s>
The	O
first	O
branch	B-General_Concept
predictor	I-General_Concept
is	O
fast	O
and	O
simple	O
.	O
</s>
<s>
The	O
second	O
branch	B-General_Concept
predictor	I-General_Concept
,	O
which	O
is	O
slower	O
,	O
more	O
complicated	O
,	O
and	O
with	O
bigger	O
tables	O
,	O
will	O
override	O
a	O
possibly	O
wrong	O
prediction	O
made	O
by	O
the	O
first	O
predictor	O
.	O
</s>
<s>
The	O
Alpha	B-General_Concept
21264	I-General_Concept
and	O
Alpha	O
EV8	O
microprocessors	B-Architecture
used	O
a	O
fast	O
single-cycle	O
next-line	O
predictor	O
to	O
handle	O
the	O
branch	B-General_Concept
target	O
recurrence	O
and	O
provide	O
a	O
simple	O
and	O
fast	O
branch	B-General_Concept
prediction	I-General_Concept
.	O
</s>
<s>
Because	O
the	O
next-line	O
predictor	O
is	O
so	O
inaccurate	O
,	O
and	O
the	O
branch	B-General_Concept
resolution	O
recurrence	O
takes	O
so	O
long	O
,	O
both	O
cores	O
have	O
two-cycle	O
secondary	O
branch	B-General_Concept
predictors	I-General_Concept
that	O
can	O
override	O
the	O
prediction	O
of	O
the	O
next-line	O
predictor	O
at	O
the	O
cost	O
of	O
a	O
single	O
lost	O
fetch	O
cycle	O
.	O
</s>
<s>
The	O
Intel	B-Device
Core	I-Device
i7	I-Device
has	O
two	O
branch	B-General_Concept
target	I-General_Concept
buffers	I-General_Concept
and	O
possibly	O
two	O
or	O
more	O
branch	B-General_Concept
predictors	I-General_Concept
.	O
</s>
<s>
Machine	O
learning	O
for	O
branch	B-General_Concept
prediction	I-General_Concept
using	O
LVQ	B-Algorithm
and	O
multi-layer	B-Algorithm
perceptrons	I-Algorithm
,	O
called	O
"	O
neural	B-Architecture
branch	B-General_Concept
prediction	I-General_Concept
"	O
,	O
was	O
proposed	O
by	O
Lucian	O
Vintan	O
(	O
Lucian	O
Blaga	O
University	O
of	O
Sibiu	O
)	O
.	O
</s>
<s>
One	O
year	O
later	O
he	O
developed	O
the	O
perceptron	B-Algorithm
branch	B-General_Concept
predictor	I-General_Concept
.	O
</s>
<s>
The	O
neural	B-Architecture
branch	B-General_Concept
predictor	I-General_Concept
research	O
was	O
developed	O
much	O
further	O
by	O
Daniel	O
Jimenez	O
.	O
</s>
<s>
In	O
2001	O
,	O
the	O
first	O
perceptron	B-Algorithm
predictor	O
was	O
presented	O
that	O
was	O
feasible	O
to	O
implement	O
in	O
hardware	O
.	O
</s>
<s>
The	O
first	O
commercial	O
implementation	O
of	O
a	O
perceptron	B-Algorithm
branch	B-General_Concept
predictor	I-General_Concept
was	O
in	O
AMD	O
's	O
Piledriver	O
microarchitecture	O
.	O
</s>
<s>
The	O
main	O
advantage	O
of	O
the	O
neural	B-Architecture
predictor	O
is	O
its	O
ability	O
to	O
exploit	O
long	O
histories	O
while	O
requiring	O
only	O
linear	O
resource	O
growth	O
.	O
</s>
<s>
He	O
also	O
used	O
a	O
gshare/perceptron	O
overriding	O
hybrid	O
predictors	O
.	O
</s>
<s>
The	O
main	O
disadvantage	O
of	O
the	O
perceptron	B-Algorithm
predictor	O
is	O
its	O
high	O
latency	O
.	O
</s>
<s>
In	O
order	O
to	O
reduce	O
the	O
prediction	O
latency	O
,	O
Jimenez	O
proposed	O
in	O
2003	O
the	O
fast-path	O
neural	B-Architecture
predictor	O
,	O
where	O
the	O
perceptron	B-Algorithm
predictor	O
chooses	O
its	O
weights	O
according	O
to	O
the	O
current	O
branch	B-General_Concept
's	O
path	O
,	O
rather	O
than	O
according	O
to	O
the	O
branch	B-General_Concept
's	O
PC	O
.	O
</s>
<s>
Most	O
of	O
the	O
state-of-the-art	O
branch	B-General_Concept
predictors	I-General_Concept
are	O
using	O
a	O
perceptron	B-Algorithm
predictor	O
(	O
see	O
Intel	O
's	O
"	O
Championship	O
Branch	B-General_Concept
Prediction	I-General_Concept
Competition	O
"	O
)	O
.	O
</s>
<s>
Intel	O
already	O
implements	O
this	O
idea	O
in	O
one	O
of	O
the	O
IA-64	B-General_Concept
'	O
s	O
simulators	O
(	O
2003	O
)	O
.	O
</s>
<s>
The	O
AMD	O
Ryzen	O
multi-core	O
processor	O
's	O
Infinity	O
Fabric	O
and	O
the	O
Samsung	B-Application
Exynos	O
processor	O
include	O
a	O
perceptron-based	O
neural	B-Architecture
branch	B-General_Concept
predictor	I-General_Concept
.	O
</s>
<s>
The	O
IBM	B-Device
7030	I-Device
Stretch	I-Device
,	O
designed	O
in	O
the	O
late	O
1950s	O
,	O
pre-executes	O
all	O
unconditional	B-General_Concept
branches	I-General_Concept
and	O
any	O
conditional	B-General_Concept
branches	I-General_Concept
that	O
depended	O
on	O
the	O
index	O
registers	O
.	O
</s>
<s>
For	O
other	O
conditional	B-General_Concept
branches	I-General_Concept
,	O
the	O
first	O
two	O
production	O
models	O
implemented	O
predict	O
untaken	O
;	O
subsequent	O
models	O
were	O
changed	O
to	O
implement	O
predictions	O
based	O
on	O
the	O
current	O
values	O
of	O
the	O
indicator	O
bits	O
(	O
corresponding	O
to	O
today	O
's	O
condition	O
codes	O
)	O
.	O
</s>
<s>
The	O
Stretch	O
designers	O
had	O
considered	O
static	O
hint	O
bits	O
in	O
the	O
branch	B-General_Concept
instructions	I-General_Concept
early	O
in	O
the	O
project	O
but	O
decided	O
against	O
them	O
.	O
</s>
<s>
Misprediction	B-General_Concept
recovery	O
was	O
provided	O
by	O
the	O
lookahead	O
unit	O
on	O
Stretch	O
,	O
and	O
part	O
of	O
Stretch	O
's	O
reputation	O
for	O
less-than-stellar	O
performance	O
was	O
blamed	O
on	O
the	O
time	O
required	O
for	O
misprediction	B-General_Concept
recovery	O
.	O
</s>
<s>
Subsequent	O
IBM	O
large	O
computer	B-General_Concept
designs	I-General_Concept
did	O
not	O
use	O
branch	B-General_Concept
prediction	I-General_Concept
with	O
speculative	B-General_Concept
execution	I-General_Concept
until	O
the	O
IBM	B-Device
3090	I-Device
in	O
1985	O
.	O
</s>
<s>
Two-bit	B-General_Concept
predictors	I-General_Concept
were	O
introduced	O
by	O
Tom	O
McWilliams	O
and	O
Curt	O
Widdoes	O
in	O
1977	O
for	O
the	O
Lawrence	O
Livermore	O
National	O
Lab	O
S-1	O
supercomputer	O
and	O
independently	O
by	O
Jim	O
Smith	O
in	O
1979	O
at	O
CDC	O
.	O
</s>
<s>
Microprogrammed	O
processors	O
,	O
popular	O
from	O
the	O
1960s	O
to	O
the	O
1980s	O
and	O
beyond	O
,	O
took	O
multiple	O
cycles	O
per	O
instruction	O
,	O
and	O
generally	O
did	O
not	O
require	O
branch	B-General_Concept
prediction	I-General_Concept
.	O
</s>
<s>
However	O
,	O
in	O
addition	O
to	O
the	O
IBM	B-Device
3090	I-Device
,	O
there	O
are	O
several	O
other	O
examples	O
of	O
microprogrammed	O
designs	O
that	O
incorporated	O
branch	B-General_Concept
prediction	I-General_Concept
.	O
</s>
<s>
The	O
Burroughs	B-Language
B4900	I-Language
,	O
a	O
microprogrammed	O
COBOL	O
machine	O
released	O
around	O
1982	O
,	O
was	O
pipelined	B-General_Concept
and	O
used	O
branch	B-General_Concept
prediction	I-General_Concept
.	O
</s>
<s>
The	O
B4900	O
branch	B-General_Concept
prediction	I-General_Concept
history	O
state	O
is	O
stored	O
back	O
into	O
the	O
in-memory	O
instructions	O
during	O
program	O
execution	O
.	O
</s>
<s>
The	O
B4900	O
implements	O
4-state	O
branch	B-General_Concept
prediction	I-General_Concept
by	O
using	O
4	O
semantically	O
equivalent	O
branch	B-General_Concept
opcodes	O
to	O
represent	O
each	O
branch	B-General_Concept
operator	O
type	O
.	O
</s>
<s>
The	O
opcode	O
used	O
indicated	O
the	O
history	O
of	O
that	O
particular	O
branch	B-General_Concept
instruction	I-General_Concept
.	O
</s>
<s>
If	O
the	O
hardware	O
determines	O
that	O
the	O
branch	B-General_Concept
prediction	I-General_Concept
state	O
of	O
a	O
particular	O
branch	B-General_Concept
needs	O
to	O
be	O
updated	O
,	O
it	O
rewrites	O
the	O
opcode	O
with	O
the	O
semantically	O
equivalent	O
opcode	O
that	O
hinted	O
the	O
proper	O
history	O
.	O
</s>
<s>
The	O
DEC	O
VAX	B-Device
9000	I-Device
,	O
announced	O
in	O
1989	O
,	O
is	O
both	O
microprogrammed	O
and	O
pipelined	B-General_Concept
,	O
and	O
performs	O
branch	B-General_Concept
prediction	I-General_Concept
.	O
</s>
<s>
The	O
first	O
commercial	O
RISC	B-Architecture
processors	I-Architecture
,	O
the	O
MIPS	B-Device
R2000	I-Device
and	O
R3000	B-Device
and	O
the	O
earlier	O
SPARC	B-Architecture
processors	O
,	O
do	O
only	O
trivial	O
"	O
not-taken	O
"	O
branch	B-General_Concept
prediction	I-General_Concept
.	O
</s>
<s>
Because	O
they	O
use	O
branch	B-General_Concept
delay	I-General_Concept
slots	I-General_Concept
,	O
fetched	O
just	O
one	O
instruction	O
per	O
cycle	O
,	O
and	O
execute	O
in-order	O
,	O
there	O
is	O
no	O
performance	O
loss	O
.	O
</s>
<s>
The	O
later	O
R4000	B-General_Concept
uses	O
the	O
same	O
trivial	O
"	O
not-taken	O
"	O
branch	B-General_Concept
prediction	I-General_Concept
,	O
and	O
loses	O
two	O
cycles	O
to	O
each	O
taken	O
branch	B-General_Concept
because	O
the	O
branch	B-General_Concept
resolution	O
recurrence	O
is	O
four	O
cycles	O
long	O
.	O
</s>
<s>
Branch	B-General_Concept
prediction	I-General_Concept
became	O
more	O
important	O
with	O
the	O
introduction	O
of	O
pipelined	B-General_Concept
superscalar	B-General_Concept
processors	I-General_Concept
like	O
the	O
Intel	B-Device
Pentium	I-Device
,	O
DEC	O
Alpha	B-General_Concept
21064	I-General_Concept
,	O
the	O
MIPS	B-Device
R8000	B-General_Concept
,	O
and	O
the	O
IBM	B-Device
POWER	I-Device
series	O
.	O
</s>
<s>
The	O
DEC	O
Alpha	B-General_Concept
21264	I-General_Concept
(	O
EV6	O
)	O
uses	O
a	O
next-line	O
predictor	O
overridden	O
by	O
a	O
combined	O
local	B-General_Concept
predictor	I-General_Concept
and	O
global	B-General_Concept
predictor	I-General_Concept
,	O
where	O
the	O
combining	O
choice	O
is	O
made	O
by	O
a	O
bimodal	O
predictor	O
.	O
</s>
<s>
The	O
AMD	B-Device
K8	I-Device
has	O
a	O
combined	O
bimodal	O
and	O
global	B-General_Concept
predictor	I-General_Concept
,	O
where	O
the	O
combining	O
choice	O
is	O
another	O
bimodal	O
predictor	O
.	O
</s>
<s>
The	O
Alpha	B-General_Concept
21464	I-General_Concept
(	O
EV8	O
,	O
cancelled	O
late	O
in	O
design	O
)	O
had	O
a	O
minimum	O
branch	B-General_Concept
misprediction	I-General_Concept
penalty	O
of	O
14	O
cycles	O
.	O
</s>
<s>
In	O
2018	O
a	O
catastrophic	O
security	O
vulnerability	O
called	O
Spectre	B-Error_Name
was	O
made	O
public	O
by	O
Google	O
's	O
Project	B-Application
Zero	I-Application
and	O
other	O
researchers	O
.	O
</s>
<s>
Affecting	O
virtually	O
all	O
modern	O
CPUs	B-General_Concept
,	O
the	O
vulnerability	O
involves	O
extracting	O
private	O
data	O
from	O
the	O
leftover	O
data	O
caches	O
of	O
branch	B-General_Concept
mispredictions	I-General_Concept
.	O
</s>
