<s>
A	O
branch	O
is	O
an	O
instruction	O
in	O
a	O
computer	B-Application
program	I-Application
that	O
can	O
cause	O
a	O
computer	O
to	O
begin	O
executing	O
a	O
different	O
instruction	O
sequence	O
and	O
thus	O
deviate	O
from	O
its	O
default	O
behavior	O
of	O
executing	O
instructions	O
in	O
order	O
.	O
</s>
<s>
Branch	O
(	O
or	O
branching	O
,	O
branched	O
)	O
may	O
also	O
refer	O
to	O
the	O
act	O
of	O
switching	O
execution	O
to	O
a	O
different	O
instruction	O
sequence	O
as	O
a	O
result	O
of	O
executing	O
a	O
branch	B-General_Concept
instruction	I-General_Concept
.	O
</s>
<s>
Branch	B-General_Concept
instructions	I-General_Concept
are	O
used	O
to	O
implement	O
control	O
flow	O
in	O
program	O
loops	O
and	O
conditionals	B-Language
(	O
i.e.	O
,	O
executing	O
a	O
particular	O
sequence	O
of	O
instructions	O
only	O
if	O
certain	O
conditions	O
are	O
satisfied	O
)	O
.	O
</s>
<s>
A	O
branch	B-General_Concept
instruction	I-General_Concept
can	O
be	O
either	O
an	O
unconditional	B-General_Concept
branch	I-General_Concept
,	O
which	O
always	O
results	O
in	O
branching	O
,	O
or	O
a	O
conditional	B-General_Concept
branch	I-General_Concept
,	O
which	O
may	O
or	O
may	O
not	O
cause	O
branching	O
depending	O
on	O
some	O
condition	O
.	O
</s>
<s>
Also	O
,	O
depending	O
on	O
how	O
it	O
specifies	O
the	O
address	O
of	O
the	O
new	O
instruction	O
sequence	O
(	O
the	O
"	O
target	O
"	O
address	O
)	O
,	O
a	O
branch	B-General_Concept
instruction	I-General_Concept
is	O
generally	O
classified	O
as	O
direct	O
,	O
indirect	O
or	O
relative	O
,	O
meaning	O
that	O
the	O
instruction	O
contains	O
the	O
target	O
address	O
,	O
or	O
it	O
specifies	O
where	O
the	O
target	O
address	O
is	O
to	O
be	O
found	O
(	O
e.g.	O
,	O
a	O
register	O
or	O
memory	O
location	O
)	O
,	O
or	O
it	O
specifies	O
the	O
difference	O
between	O
the	O
current	O
and	O
target	O
addresses	O
.	O
</s>
<s>
Branch	B-General_Concept
instructions	I-General_Concept
can	O
alter	O
the	O
contents	O
of	O
the	O
CPU	B-Device
's	O
Program	B-General_Concept
Counter	I-General_Concept
(	O
or	O
PC	O
)	O
(	O
or	O
Instruction	B-General_Concept
Pointer	I-General_Concept
on	O
Intel	O
microprocessors	O
)	O
.	O
</s>
<s>
Therefore	O
,	O
a	O
branch	O
,	O
if	O
executed	O
,	O
causes	O
the	O
CPU	B-Device
to	O
execute	O
code	O
from	O
a	O
new	O
memory	O
address	O
,	O
changing	O
the	O
program	O
logic	O
according	O
to	O
the	O
algorithm	O
planned	O
by	O
the	O
programmer	O
.	O
</s>
<s>
These	O
may	O
or	O
may	O
not	O
result	O
in	O
the	O
PC	O
being	O
loaded	O
or	O
modified	O
with	O
some	O
new	O
,	O
different	O
value	O
other	O
than	O
what	O
it	O
ordinarily	O
would	O
have	O
been	O
(	O
being	O
incremented	O
past	O
the	O
current	B-General_Concept
instruction	I-General_Concept
to	O
point	O
to	O
the	O
following	O
,	O
next	B-General_Concept
instruction	I-General_Concept
)	O
.	O
</s>
<s>
Jumps	O
typically	O
have	O
unconditional	O
and	O
conditional	B-Language
forms	O
where	O
the	O
latter	O
may	O
be	O
taken	O
or	O
not	O
taken	O
(	O
the	O
PC	O
is	O
modified	O
or	O
not	O
)	O
depending	O
on	O
some	O
condition	O
.	O
</s>
<s>
The	O
term	O
branch	O
can	O
also	O
be	O
used	O
when	O
referring	O
to	O
programs	O
in	O
high-level	B-Language
programming	I-Language
languages	I-Language
.	O
</s>
<s>
In	O
these	O
branches	O
usually	O
take	O
the	O
form	O
of	O
conditional	B-Language
statements	O
of	O
various	O
forms	O
that	O
encapsulate	O
the	O
instruction	O
sequence	O
that	O
will	O
be	O
executed	O
if	O
the	O
conditions	O
are	O
satisfied	O
.	O
</s>
<s>
Unconditional	B-General_Concept
branch	I-General_Concept
instructions	I-General_Concept
such	O
as	O
GOTO	B-Application
are	O
used	O
to	O
unconditionally	O
jump	O
to	O
a	O
different	O
instruction	O
sequence	O
.	O
</s>
<s>
If	O
the	O
algorithm	O
requires	O
a	O
conditional	B-General_Concept
branch	I-General_Concept
,	O
the	O
GOTO	B-Application
(	O
or	O
GOSUB	O
subroutine	O
call	O
)	O
is	O
preceded	O
by	O
an	O
IF-THEN	B-Language
statement	I-Language
specifying	O
the	O
condition(s )	O
.	O
</s>
<s>
All	O
high	B-Language
level	I-Language
languages	I-Language
support	O
algorithms	O
that	O
can	O
re-use	O
code	O
as	O
a	O
loop	O
,	O
a	O
control	O
structure	O
that	O
repeats	O
a	O
sequence	O
of	O
instructions	O
until	O
some	O
condition	O
is	O
satisfied	O
that	O
causes	O
the	O
loop	O
to	O
terminate	O
.	O
</s>
<s>
Loops	O
also	O
qualify	O
as	O
branch	B-General_Concept
instructions	I-General_Concept
.	O
</s>
<s>
At	O
the	O
machine	O
level	O
,	O
loops	O
are	O
implemented	O
as	O
ordinary	O
conditional	B-General_Concept
jumps	I-General_Concept
that	O
redirect	O
execution	O
to	O
repeating	O
code	O
.	O
</s>
<s>
In	O
CPUs	B-Device
with	O
flag	B-General_Concept
registers	I-General_Concept
,	O
an	O
earlier	O
instruction	O
sets	O
a	O
condition	O
in	O
the	O
flag	B-General_Concept
register	I-General_Concept
.	O
</s>
<s>
The	O
earlier	O
instruction	O
may	O
be	O
arithmetic	B-General_Concept
,	I-General_Concept
or	I-General_Concept
a	I-General_Concept
logic	I-General_Concept
instruction	O
.	O
</s>
<s>
This	O
temporary	O
information	O
is	O
often	O
stored	O
in	O
a	O
flag	B-General_Concept
register	I-General_Concept
but	O
may	O
also	O
be	O
located	O
elsewhere	O
.	O
</s>
<s>
A	O
flag	B-General_Concept
register	I-General_Concept
design	O
is	O
simple	O
in	O
slower	O
,	O
simple	O
computers	O
.	O
</s>
<s>
In	O
fast	O
computers	O
a	O
flag	B-General_Concept
register	I-General_Concept
can	O
place	O
a	O
bottleneck	O
on	O
speed	O
,	O
because	O
instructions	O
that	O
could	O
otherwise	O
operate	O
in	O
parallel	O
(	O
in	O
several	O
execution	B-General_Concept
units	I-General_Concept
)	O
need	O
to	O
set	O
the	O
flag	O
bits	O
in	O
a	O
particular	O
sequence	O
.	O
</s>
<s>
In	O
simple	O
computer	B-General_Concept
designs	I-General_Concept
,	O
comparison	O
branches	O
execute	O
more	O
arithmetic	O
and	O
can	O
use	O
more	O
power	O
than	O
flag	B-General_Concept
register	I-General_Concept
branches	O
.	O
</s>
<s>
In	O
fast	O
computer	B-General_Concept
designs	I-General_Concept
comparison	O
branches	O
can	O
run	O
faster	O
than	O
flag	B-General_Concept
register	I-General_Concept
branches	O
,	O
because	O
comparison	O
branches	O
can	O
access	O
the	O
registers	O
with	O
more	O
parallelism	O
,	O
using	O
the	O
same	O
CPU	B-Device
mechanisms	O
as	O
a	O
calculation	O
.	O
</s>
<s>
Some	O
early	O
and	O
simple	O
CPU	B-Device
architectures	O
,	O
still	O
found	O
in	O
microcontrollers	O
,	O
may	O
not	O
implement	O
a	O
conditional	B-General_Concept
jump	I-General_Concept
,	O
but	O
rather	O
only	O
a	O
conditional	B-Language
"	O
skip	O
the	O
next	B-General_Concept
instruction	I-General_Concept
"	O
operation	O
.	O
</s>
<s>
A	O
conditional	B-General_Concept
jump	I-General_Concept
or	O
call	O
is	O
thus	O
implemented	O
as	O
a	O
conditional	B-Language
skip	O
of	O
an	O
unconditional	O
jump	O
or	O
call	O
instruction	O
.	O
</s>
<s>
Depending	O
on	O
the	O
computer	B-General_Concept
architecture	I-General_Concept
,	O
the	O
assembly	B-Language
language	I-Language
mnemonic	O
for	O
a	O
jump	O
instruction	O
is	O
typically	O
some	O
shortened	O
form	O
of	O
the	O
word	O
jump	O
or	O
the	O
word	O
branch	O
,	O
often	O
along	O
with	O
other	O
informative	O
letters	O
(	O
or	O
an	O
extra	O
parameter	O
)	O
representing	O
the	O
condition	O
.	O
</s>
<s>
condition	O
or	O
result	O
x86	O
PDP-11	O
,	O
VAX	O
ARM	O
(	O
partly	O
6502	B-General_Concept
)	O
equation	O
zero	O
(	O
implies	O
equal	O
for	O
sub/cmp	O
)	O
JZ	O
;	O
JNZ	O
BEQ	O
;	O
BNE	O
BEQ	O
;	O
BNE	O
zero	O
;	O
not	O
zero	O
negative	O
(	O
N	O
)	O
,	O
sign	O
(	O
S	O
)	O
,	O
or	O
minus	O
(	O
M	O
)	O
JS	O
;	O
JNS	O
BMI	O
;	O
BPL	O
BMI	O
;	O
BPL	O
negative	O
;	O
not	O
negative	O
arithmetic	O
overflow	O
(	O
flag	O
called	O
O	O
or	O
V	O
)	O
JO	O
;	O
JNO	O
BVS	O
;	O
BVC	O
BVS	O
;	O
BVC	O
overflow	O
;	O
not	O
overflow	O
carry	O
(	O
from	O
add	O
,	O
cmp	O
,	O
shift	O
,	O
etc	O
.	O
)	O
</s>
<s>
ARM	O
,	O
6502	B-General_Concept
,	O
the	O
PIC	O
,	O
and	O
some	O
others	O
,	O
do	O
the	O
opposite	O
for	O
subtractive	O
operations	O
.	O
</s>
<s>
To	O
achieve	O
high	O
performance	O
,	O
modern	O
processors	O
are	O
pipelined	B-General_Concept
.	O
</s>
<s>
They	O
consist	O
of	O
multiple	O
parts	O
that	O
each	O
partially	O
process	O
an	O
instruction	O
,	O
feed	O
their	O
results	O
to	O
the	O
next	O
stage	O
in	O
the	O
pipeline	O
,	O
and	O
start	O
working	O
on	O
the	O
next	B-General_Concept
instruction	I-General_Concept
in	O
the	O
program	O
.	O
</s>
<s>
Conditional	B-General_Concept
branch	I-General_Concept
instructions	O
make	O
it	O
impossible	O
to	O
know	O
this	O
sequence	O
.	O
</s>
<s>
So	O
conditional	B-General_Concept
branches	I-General_Concept
can	O
cause	O
"	O
stalls	O
"	O
in	O
which	O
the	O
pipeline	O
has	O
to	O
be	O
restarted	O
on	O
a	O
different	O
part	O
of	O
the	O
program	O
.	O
</s>
<s>
Several	O
techniques	O
improve	O
speed	O
by	O
reducing	O
stalls	O
from	O
conditional	B-General_Concept
branches	I-General_Concept
.	O
</s>
<s>
Historically	O
,	O
branch	B-General_Concept
prediction	I-General_Concept
took	O
statistics	O
,	O
and	O
used	O
the	O
result	O
to	O
optimize	O
code	O
.	O
</s>
<s>
To	O
permit	O
this	O
,	O
CPUs	B-Device
must	O
be	O
designed	O
with	O
(	O
or	O
at	O
least	O
have	O
)	O
predictable	O
branch	O
timing	O
.	O
</s>
<s>
Some	O
CPUs	B-Device
have	O
instruction	O
sets	O
(	O
such	O
as	O
the	O
Power	B-Architecture
ISA	I-Architecture
)	O
that	O
were	O
designed	O
with	O
"	O
branch	O
hints	O
"	O
so	O
that	O
a	O
compiler	O
can	O
tell	O
a	O
CPU	B-Device
how	O
each	O
branch	O
is	O
to	O
be	O
taken	O
.	O
</s>
<s>
The	O
problem	O
with	O
software	O
branch	B-General_Concept
prediction	I-General_Concept
is	O
that	O
it	O
requires	O
a	O
complex	O
software	O
development	O
process	O
.	O
</s>
<s>
To	O
run	O
any	O
software	O
,	O
hardware	O
branch	B-General_Concept
predictors	I-General_Concept
moved	O
the	O
statistics	O
into	O
the	O
electronics	O
.	O
</s>
<s>
Branch	B-General_Concept
predictors	I-General_Concept
are	O
parts	O
of	O
a	O
processor	O
that	O
guess	O
the	O
outcome	O
of	O
a	O
conditional	B-General_Concept
branch	I-General_Concept
.	O
</s>
<s>
An	O
example	O
of	O
a	O
simple	O
hardware	O
branch	B-General_Concept
prediction	I-General_Concept
scheme	O
is	O
to	O
assume	O
that	O
all	O
backward	O
branches	O
(	O
i.e.	O
</s>
<s>
to	O
a	O
smaller	O
program	B-General_Concept
counter	I-General_Concept
)	O
are	O
taken	O
(	O
because	O
they	O
are	O
part	O
of	O
a	O
loop	O
)	O
,	O
and	O
all	O
forward	O
branches	O
(	O
to	O
a	O
larger	O
program	B-General_Concept
counter	I-General_Concept
)	O
are	O
not	O
taken	O
(	O
because	O
they	O
leave	O
a	O
loop	O
)	O
.	O
</s>
<s>
Better	O
branch	B-General_Concept
predictors	I-General_Concept
are	O
developed	O
and	O
validated	O
statistically	O
by	O
running	O
them	O
in	O
simulation	O
on	O
a	O
variety	O
of	O
test	O
programs	O
.	O
</s>
<s>
Faster	O
,	O
more	O
expensive	O
computers	O
can	O
then	O
run	O
faster	O
by	O
investing	O
in	O
better	O
branch	B-General_Concept
prediction	I-General_Concept
electronics	O
.	O
</s>
<s>
In	O
a	O
CPU	B-Device
with	O
hardware	O
branch	B-General_Concept
prediction	I-General_Concept
,	O
branch	O
hints	O
let	O
the	O
compiler	O
's	O
presumably	O
superior	O
branch	B-General_Concept
prediction	I-General_Concept
override	O
the	O
hardware	O
's	O
more	O
simplistic	O
branch	B-General_Concept
prediction	I-General_Concept
.	O
</s>
<s>
It	O
is	O
often	O
possible	O
to	O
use	O
bitwise	O
operations	O
,	O
conditional	B-General_Concept
moves	I-General_Concept
or	O
other	O
predication	B-General_Concept
instead	O
of	O
branches	O
.	O
</s>
<s>
Another	O
technique	O
is	O
a	O
branch	B-General_Concept
delay	I-General_Concept
slot	I-General_Concept
.	O
</s>
<s>
This	O
approach	O
was	O
historically	O
popular	O
in	O
RISC	B-Architecture
computers	O
.	O
</s>
<s>
In	O
a	O
family	O
of	O
compatible	O
CPUs	B-Device
,	O
it	O
complicates	O
multicycle	O
CPUs	B-Device
(	O
with	O
no	O
pipeline	O
)	O
,	O
faster	O
CPUs	B-Device
with	O
longer-than-expected	O
pipelines	O
,	O
and	O
superscalar	O
CPUs	B-Device
(	O
which	O
can	O
execute	O
instructions	O
out	O
of	O
order	O
.	O
)	O
</s>
