<s>
Berkeley	B-General_Concept
RISC	I-General_Concept
is	O
one	O
of	O
two	O
seminal	O
research	O
projects	O
into	O
reduced	B-Architecture
instruction	I-Architecture
set	I-Architecture
computer	I-Architecture
(	O
RISC	B-Architecture
)	O
based	O
microprocessor	B-Architecture
design	O
taking	O
place	O
under	O
the	O
Defense	O
Advanced	O
Research	O
Projects	O
Agency	O
VLSI	O
Project	O
.	O
</s>
<s>
RISC	B-Architecture
was	O
led	O
by	O
David	O
Patterson	O
(	O
who	O
coined	O
the	O
term	O
RISC	B-Architecture
)	O
at	O
the	O
University	O
of	O
California	O
,	O
Berkeley	O
between	O
1980	O
and	O
1984	O
.	O
</s>
<s>
The	O
other	O
project	O
took	O
place	O
a	O
short	O
distance	O
away	O
at	O
Stanford	O
University	O
under	O
their	O
MIPS	B-General_Concept
effort	O
starting	O
in	O
1981	O
and	O
running	O
until	O
1984	O
.	O
</s>
<s>
Berkeley	O
's	O
project	O
was	O
so	O
successful	O
that	O
it	O
became	O
the	O
name	O
for	O
all	O
similar	O
designs	O
to	O
follow	O
;	O
even	O
the	O
MIPS	B-General_Concept
would	O
become	O
known	O
as	O
a	O
"	O
RISC	B-Architecture
processor	I-Architecture
"	O
.	O
</s>
<s>
The	O
Berkeley	B-General_Concept
RISC	I-General_Concept
design	O
was	O
later	O
commercialized	O
by	O
Sun	O
Microsystems	O
as	O
the	O
SPARC	B-Architecture
architecture	O
,	O
and	O
inspired	O
the	O
ARM	B-Architecture
architecture	I-Architecture
.	O
</s>
<s>
Both	O
RISC	B-Architecture
and	O
MIPS	B-General_Concept
were	O
developed	O
from	O
the	O
realization	O
that	O
the	O
vast	O
majority	O
of	O
programs	O
did	O
not	O
use	O
the	O
vast	O
majority	O
of	O
a	O
processor	O
's	O
instructions	O
.	O
</s>
<s>
In	O
a	O
famous	O
1978	O
paper	O
,	O
Andrew	O
S	O
.	O
Tanenbaum	O
demonstrated	O
that	O
a	O
complex	O
10,000	O
line	O
high-level	O
program	O
could	O
be	O
represented	O
using	O
a	O
simplified	O
instruction	B-General_Concept
set	I-General_Concept
architecture	I-General_Concept
using	O
an	O
8-bit	O
fixed-length	O
opcode	O
.	O
</s>
<s>
This	O
was	O
roughly	O
the	O
same	O
conclusion	O
reached	O
at	O
IBM	O
,	O
whose	O
studies	O
of	O
their	O
own	O
code	O
running	O
on	O
mainframes	O
like	O
the	O
IBM	B-Application
360	I-Application
used	O
only	O
a	O
small	O
subset	O
of	O
all	O
the	O
instructions	O
available	O
.	O
</s>
<s>
These	O
realizations	O
were	O
taking	O
place	O
as	O
the	O
microprocessor	B-Architecture
market	O
was	O
moving	O
from	O
8	O
to	O
16-bit	B-Device
with	O
32-bit	O
designs	O
about	O
to	O
appear	O
.	O
</s>
<s>
For	O
instance	O
,	O
the	O
National	B-Device
Semiconductor	I-Device
NS32000	I-Device
started	O
out	O
as	O
an	O
effort	O
to	O
produce	O
a	O
single-chip	O
implementation	O
of	O
the	O
VAX-11	O
,	O
which	O
had	O
a	O
rich	O
instruction	B-General_Concept
set	I-General_Concept
with	O
a	O
wide	O
variety	O
of	O
addressing	B-Language
modes	I-Language
.	O
</s>
<s>
The	O
Motorola	B-Device
68000	I-Device
was	O
similar	O
in	O
general	O
layout	O
.	O
</s>
<s>
To	O
provide	O
this	O
rich	O
set	O
of	O
instructions	O
,	O
CPUs	O
used	O
microcode	B-Device
to	O
decode	O
the	O
user-visible	O
instruction	O
into	O
a	O
series	O
of	O
internal	O
operations	O
.	O
</s>
<s>
This	O
microcode	B-Device
represented	O
perhaps	O
to	O
of	O
the	O
transistors	O
of	O
the	O
overall	O
design	O
.	O
</s>
<s>
The	O
RISC	B-Architecture
concept	O
was	O
to	O
take	O
advantage	O
of	O
both	O
of	O
these	O
,	O
producing	O
a	O
CPU	O
that	O
was	O
the	O
same	O
level	O
of	O
complexity	O
as	O
the	O
68000	B-Device
,	O
but	O
much	O
faster	O
.	O
</s>
<s>
To	O
do	O
this	O
,	O
RISC	B-Architecture
concentrated	O
on	O
adding	O
many	O
more	O
registers	B-General_Concept
,	O
small	O
bits	O
of	O
memory	O
holding	O
temporary	O
values	O
that	O
can	O
be	O
accessed	O
very	O
rapidly	O
.	O
</s>
<s>
By	O
providing	O
more	O
registers	B-General_Concept
,	O
and	O
making	O
sure	O
the	O
compilers	O
actually	O
used	O
them	O
,	O
programs	O
should	O
run	O
much	O
faster	O
.	O
</s>
<s>
Transistor	O
for	O
transistor	O
,	O
a	O
RISC	B-Architecture
design	O
would	O
outperform	O
a	O
conventional	O
CPU	O
,	O
hopefully	O
by	O
a	O
lot	O
.	O
</s>
<s>
For	O
instance	O
,	O
the	O
ADD	O
instruction	O
of	O
a	O
traditional	O
design	O
would	O
generally	O
come	O
in	O
several	O
flavours	O
,	O
one	O
that	O
added	O
the	O
numbers	O
in	O
two	O
registers	B-General_Concept
and	O
placed	O
it	O
in	O
a	O
third	O
,	O
another	O
that	O
added	O
numbers	O
found	O
in	O
main	O
memory	O
and	O
put	O
the	O
result	O
in	O
a	O
register	O
,	O
etc	O
.	O
</s>
<s>
The	O
RISC	B-Architecture
designs	O
,	O
on	O
the	O
other	O
hand	O
,	O
included	O
only	O
a	O
single	O
flavour	O
of	O
any	O
particular	O
instruction	O
,	O
the	O
ADD	O
,	O
for	O
instance	O
,	O
would	O
always	O
use	O
registers	B-General_Concept
for	O
all	O
operands	O
.	O
</s>
<s>
This	O
forced	O
the	O
programmer	O
to	O
write	O
additional	O
instructions	O
to	O
load	O
the	O
values	O
from	O
memory	O
,	O
if	O
needed	O
,	O
making	O
a	O
RISC	B-Architecture
program	O
"	O
less	O
dense	O
"	O
.	O
</s>
<s>
Since	O
a	O
RISC	B-Architecture
design	O
's	O
ADD	O
would	O
actually	O
require	O
four	O
instructions	O
(	O
two	O
loads	O
,	O
an	O
add	O
,	O
and	O
a	O
save	O
)	O
,	O
the	O
machine	O
would	O
have	O
to	O
do	O
much	O
more	O
memory	O
access	O
to	O
read	O
the	O
extra	O
instructions	O
,	O
potentially	O
slowing	O
it	O
down	O
considerably	O
.	O
</s>
<s>
For	O
instance	O
,	O
a	O
string	O
of	O
instructions	O
carrying	O
out	O
a	O
series	O
of	O
mathematical	O
operations	O
might	O
require	O
only	O
a	O
few	O
loads	O
from	O
memory	O
,	O
while	O
the	O
majority	O
of	O
the	O
numbers	O
being	O
used	O
would	O
be	O
either	O
constants	O
in	O
the	O
instructions	O
,	O
or	O
intermediate	O
values	O
left	O
in	O
the	O
registers	B-General_Concept
from	O
prior	O
calculations	O
.	O
</s>
<s>
In	O
a	O
sense	O
,	O
in	O
this	O
technique	O
some	O
registers	B-General_Concept
are	O
used	O
to	O
shadow	O
memory	O
locations	O
,	O
so	O
that	O
the	O
registers	B-General_Concept
are	O
used	O
as	O
proxies	O
for	O
the	O
memory	O
locations	O
until	O
their	O
final	O
values	O
after	O
a	O
group	O
of	O
instructions	O
have	O
been	O
determined	O
.	O
</s>
<s>
To	O
the	O
casual	O
observer	O
,	O
it	O
was	O
not	O
clear	O
that	O
the	O
RISC	B-Architecture
concept	O
would	O
improve	O
performance	O
,	O
and	O
it	O
might	O
even	O
make	O
it	O
worse	O
.	O
</s>
<s>
Where	O
the	O
two	O
projects	O
,	O
RISC	B-Architecture
and	O
MIPS	B-General_Concept
,	O
differed	O
was	O
in	O
the	O
handling	O
of	O
the	O
registers	B-General_Concept
.	O
</s>
<s>
MIPS	B-General_Concept
simply	O
added	O
lots	O
of	O
registers	B-General_Concept
and	O
left	O
it	O
to	O
the	O
compilers	O
(	O
or	O
assembly	B-Language
language	I-Language
programmers	O
)	O
to	O
make	O
use	O
of	O
them	O
.	O
</s>
<s>
RISC	B-Architecture
,	O
on	O
the	O
other	O
hand	O
,	O
added	O
circuitry	O
to	O
the	O
CPU	O
to	O
assist	O
the	O
compiler	O
.	O
</s>
<s>
RISC	B-Architecture
used	O
the	O
concept	O
of	O
register	B-General_Concept
windows	I-General_Concept
,	O
in	O
which	O
the	O
entire	O
"	O
register	O
file	O
"	O
was	O
broken	O
down	O
into	O
blocks	O
,	O
allowing	O
the	O
compiler	O
to	O
"	O
see	O
"	O
one	O
block	O
for	O
global	O
variables	O
,	O
and	O
another	O
for	O
local	O
variables	O
.	O
</s>
<s>
In	O
the	O
Berkeley	O
design	O
,	O
then	O
,	O
a	O
register	B-General_Concept
window	I-General_Concept
was	O
a	O
set	O
of	O
several	O
registers	B-General_Concept
,	O
enough	O
of	O
them	O
that	O
the	O
entire	O
procedure	O
stack	O
frame	O
would	O
most	O
likely	O
fit	O
entirely	O
within	O
the	O
register	B-General_Concept
window	I-General_Concept
.	O
</s>
<s>
A	O
single	O
instruction	O
is	O
called	O
to	O
set	O
up	O
a	O
new	O
block	O
of	O
registers	B-General_Concept
—	O
a	O
new	O
register	B-General_Concept
window	I-General_Concept
—	O
and	O
then	O
,	O
with	O
operands	O
passed	O
into	O
the	O
procedure	O
in	O
the	O
"	O
low	O
end	O
"	O
of	O
the	O
new	O
window	O
,	O
the	O
program	O
jumps	O
into	O
the	O
procedure	O
.	O
</s>
<s>
The	O
register	B-General_Concept
windows	I-General_Concept
are	O
set	O
up	O
to	O
overlap	O
at	O
the	O
ends	O
,	O
so	O
that	O
the	O
results	O
from	O
the	O
call	O
simply	O
"	O
appear	O
"	O
in	O
the	O
window	O
of	O
the	O
caller	O
,	O
with	O
no	O
data	O
having	O
to	O
be	O
copied	O
.	O
</s>
<s>
On	O
the	O
downside	O
,	O
this	O
approach	O
means	O
that	O
procedures	O
with	O
large	O
numbers	O
of	O
local	O
variables	O
are	O
problematic	O
,	O
and	O
ones	O
with	O
fewer	O
lead	O
to	O
registers	B-General_Concept
—	O
an	O
expensive	O
resource	O
—	O
being	O
wasted	O
.	O
</s>
<s>
There	O
are	O
a	O
finite	O
number	O
of	O
register	B-General_Concept
windows	I-General_Concept
in	O
the	O
design	O
,	O
e.g.	O
,	O
eight	O
,	O
so	O
procedures	O
can	O
only	O
be	O
nested	O
that	O
many	O
levels	O
deep	O
before	O
the	O
register	B-General_Concept
windowing	I-General_Concept
mechanism	O
reaches	O
its	O
limit	O
;	O
once	O
the	O
last	O
window	O
is	O
reached	O
,	O
no	O
new	O
window	O
can	O
be	O
set	O
up	O
for	O
another	O
nested	O
call	O
.	O
</s>
<s>
And	O
if	O
procedures	O
are	O
only	O
nested	O
a	O
few	O
levels	O
deep	O
,	O
registers	B-General_Concept
in	O
the	O
windows	O
above	O
the	O
deepest	O
call	O
nesting	O
level	O
can	O
never	O
be	O
accessed	O
at	O
all	O
,	O
so	O
these	O
are	O
completely	O
wasted	O
.	O
</s>
<s>
It	O
was	O
Stanford	O
's	O
work	O
on	O
compilers	O
that	O
led	O
them	O
to	O
ignore	O
the	O
register	B-General_Concept
window	I-General_Concept
concept	O
,	O
believing	O
that	O
an	O
efficient	O
compiler	O
could	O
make	O
better	O
use	O
of	O
the	O
registers	B-General_Concept
than	O
a	O
fixed	O
system	O
in	O
hardware	O
.	O
</s>
<s>
(	O
The	O
same	O
reasoning	O
would	O
apply	O
for	O
a	O
smart	O
assembly	B-Language
language	I-Language
programmer	O
.	O
)	O
</s>
<s>
The	O
first	O
attempt	O
to	O
implement	O
the	O
RISC	B-Architecture
concept	O
was	O
originally	O
named	O
Gold	O
.	O
</s>
<s>
The	O
team	O
had	O
to	O
spend	O
considerable	O
amounts	O
of	O
time	O
improving	O
or	O
re-writing	O
the	O
tools	O
,	O
and	O
even	O
with	O
these	O
new	O
tools	O
it	O
took	O
just	O
under	O
an	O
hour	O
to	O
extract	O
the	O
design	O
on	O
a	O
VAX-11/780	O
.	O
</s>
<s>
The	O
final	O
design	O
,	O
named	O
RISC	B-Architecture
I	O
,	O
was	O
published	O
in	O
Association	O
for	O
Computing	O
Machinery	O
(	O
ACM	O
)	O
International	O
Symposium	O
on	O
Computer	O
Architecture	O
(	O
ISCA	O
)	O
in	O
1981	O
.	O
</s>
<s>
It	O
had	O
44,500	O
transistors	O
implementing	O
31	O
instructions	O
and	O
a	O
register	O
file	O
containing	O
78	O
32-bit	O
registers	B-General_Concept
.	O
</s>
<s>
This	O
allowed	O
for	O
six	O
register	B-General_Concept
windows	I-General_Concept
containing	O
14	O
registers	B-General_Concept
.	O
</s>
<s>
Of	O
those	O
14	O
registers	B-General_Concept
,	O
4	O
were	O
overlapped	O
from	O
the	O
prior	O
window	O
.	O
</s>
<s>
The	O
total	O
is	O
then	O
:	O
10*6	O
registers	B-General_Concept
in	O
windows	O
+	O
18	O
globals	O
=	O
78	O
registers	B-General_Concept
total	O
.	O
</s>
<s>
RISC	B-Architecture
I	O
also	O
featured	O
a	O
two-stage	O
instruction	B-General_Concept
pipeline	I-General_Concept
for	O
additional	O
speed	O
,	O
but	O
without	O
the	O
complex	O
instruction	O
re-ordering	O
of	O
more	O
modern	O
designs	O
.	O
</s>
<s>
This	O
makes	O
conditional	O
branches	O
a	O
problem	O
,	O
because	O
the	O
compiler	O
has	O
to	O
fill	O
the	O
instruction	O
following	O
a	O
conditional	O
branch	O
(	O
the	O
so-called	O
branch	B-General_Concept
delay	I-General_Concept
slot	I-General_Concept
)	O
,	O
with	O
something	O
selected	O
to	O
be	O
"	O
safe	O
"	O
(	O
i.e.	O
,	O
not	O
dependent	O
on	O
the	O
outcome	O
of	O
the	O
conditional	O
)	O
.	O
</s>
<s>
Sometimes	O
the	O
only	O
suitable	O
instruction	O
in	O
this	O
case	O
is	O
NOP	B-Language
.	O
</s>
<s>
A	O
notable	O
number	O
of	O
later	O
RISC-style	O
designs	O
still	O
require	O
the	O
consideration	O
of	O
branch	O
delay	O
.	O
</s>
<s>
After	O
a	O
month	O
of	O
validation	O
and	O
debugging	O
,	O
the	O
design	O
was	O
sent	O
to	O
the	O
innovative	O
MOSIS	B-Architecture
service	O
for	O
production	O
on	O
June	O
22	O
,	O
1981	O
,	O
using	O
a	O
2	O
μm	O
(	O
2,000	O
nm	O
)	O
process	O
.	O
</s>
<s>
The	O
first	O
working	O
RISC	B-Architecture
I	O
"	O
computer	O
"	O
(	O
actually	O
a	O
checkout	O
board	O
)	O
ran	O
on	O
June	O
11	O
.	O
</s>
<s>
Simulations	O
using	O
a	O
variety	O
of	O
small	O
programs	O
compared	O
the	O
4MHz	O
RISC	B-Architecture
I	O
to	O
the	O
5MHz	O
32-bit	O
VAX	B-Device
11/780	I-Device
and	O
the	O
5MHz	O
16-bit	B-Device
Zilog	B-Device
Z8000	I-Device
showed	O
this	O
clearly	O
.	O
</s>
<s>
Program	O
size	O
was	O
about	O
30%	O
larger	O
than	O
the	O
VAX	B-Device
but	O
very	O
close	O
to	O
that	O
of	O
the	O
Z8000	B-Device
,	O
validating	O
the	O
argument	O
that	O
the	O
higher	O
code	O
density	O
of	O
CISC	O
designs	O
was	O
not	O
actually	O
all	O
that	O
impressive	O
in	O
reality	O
.	O
</s>
<s>
In	O
terms	O
of	O
overall	O
performance	O
,	O
the	O
RISC	B-Architecture
I	O
was	O
twice	O
as	O
fast	O
as	O
the	O
VAX	B-Device
,	O
and	O
about	O
four	O
times	O
that	O
of	O
the	O
Z8000	B-Device
.	O
</s>
<s>
Even	O
though	O
the	O
RISC	B-Architecture
design	O
had	O
run	O
slower	O
than	O
the	O
VAX	B-Device
,	O
it	O
made	O
no	O
difference	O
to	O
the	O
importance	O
of	O
the	O
design	O
.	O
</s>
<s>
RISC	B-Architecture
allowed	O
for	O
the	O
production	O
of	O
a	O
true	O
32-bit	O
processor	O
on	O
a	O
real	O
chip	O
die	O
using	O
what	O
was	O
already	O
an	O
older	O
fab	O
.	O
</s>
<s>
Traditional	O
designs	O
simply	O
could	O
not	O
do	O
this	O
;	O
with	O
so	O
much	O
of	O
the	O
chip	O
surface	O
dedicated	O
to	O
decoder	O
logic	O
,	O
a	O
true	O
32-bit	O
design	O
like	O
the	O
Motorola	B-Device
68020	I-Device
required	O
newer	O
fabs	O
before	O
becoming	O
practical	O
.	O
</s>
<s>
Using	O
the	O
same	O
fabs	O
,	O
RISC	B-Architecture
I	O
could	O
have	O
largely	O
outperformed	O
the	O
competition	O
.	O
</s>
<s>
On	O
February	O
12	O
,	O
2015	O
,	O
IEEE	O
installed	O
a	O
plaque	O
at	O
UC	O
Berkeley	O
to	O
commemorate	O
the	O
contribution	O
of	O
RISC-I	O
.	O
</s>
<s>
UC	O
Berkeley	O
students	O
designed	O
and	O
built	O
the	O
first	O
VLSI	O
reduced	B-Architecture
instruction	I-Architecture
set	I-Architecture
computer	I-Architecture
in	O
1981	O
.	O
</s>
<s>
The	O
simplified	O
instructions	O
of	O
RISC-I	O
reduced	O
the	O
hardware	O
for	O
instruction	O
decode	O
and	O
control	O
,	O
which	O
enabled	O
a	O
flat	O
32-bit	O
address	O
space	O
,	O
a	O
large	O
set	O
of	O
registers	B-General_Concept
,	O
and	O
pipelined	O
execution	O
.	O
</s>
<s>
A	O
good	O
match	O
to	O
C	B-Language
programs	I-Language
and	O
the	O
Unix	B-Application
operating	I-Application
system	I-Application
,	O
RISC-I	O
influenced	O
instruction	B-General_Concept
sets	I-General_Concept
widely	O
used	O
today	O
,	O
including	O
those	O
for	O
game	O
consoles	O
,	O
smartphones	O
and	O
tablets	O
.	O
</s>
<s>
While	O
the	O
RISC	B-Architecture
I	O
design	O
ran	O
into	O
delays	O
,	O
work	O
at	O
Berkeley	O
had	O
already	O
turned	O
to	O
the	O
new	O
Blue	O
design	O
.	O
</s>
<s>
Whereas	O
Gold	O
contained	O
a	O
total	O
of	O
78	O
registers	B-General_Concept
in	O
6	O
windows	O
,	O
Blue	O
contained	O
138	O
registers	B-General_Concept
broken	O
into	O
8	O
windows	O
of	O
16	O
registers	B-General_Concept
each	O
,	O
with	O
another	O
10	O
globals	O
.	O
</s>
<s>
This	O
expansion	O
of	O
the	O
register	O
file	O
increases	O
the	O
chance	O
that	O
a	O
given	O
procedure	O
can	O
fit	O
all	O
of	O
its	O
local	O
storage	O
in	O
registers	B-General_Concept
,	O
and	O
increase	O
the	O
nesting	O
depth	O
.	O
</s>
<s>
Nevertheless	O
,	O
the	O
larger	O
register	O
file	O
required	O
fewer	O
transistors	O
,	O
and	O
the	O
final	O
Blue	O
design	O
,	O
fabbed	O
as	O
RISC	B-Architecture
II	O
,	O
implemented	O
all	O
of	O
the	O
RISC	B-Architecture
instruction	I-Architecture
set	I-Architecture
with	O
only	O
40,760	O
transistors	O
.	O
</s>
<s>
The	O
other	O
major	O
change	O
was	O
to	O
include	O
an	O
instruction-format	O
expander	O
,	O
which	O
invisibly	O
"	O
up-converted	O
"	O
16-bit	B-Device
instructions	O
into	O
a	O
32-bit	O
format	O
.	O
</s>
<s>
This	O
allowed	O
smaller	O
instructions	O
,	O
typically	O
things	O
with	O
one	O
or	O
no	O
operands	O
,	O
like	O
NOP	B-Language
,	O
to	O
be	O
stored	O
in	O
memory	O
in	O
a	O
smaller	O
16-bit	B-Device
format	O
,	O
and	O
for	O
two	O
such	O
instructions	O
to	O
be	O
packed	O
into	O
a	O
single	O
machine	O
word	O
.	O
</s>
<s>
The	O
instructions	O
would	O
be	O
invisibly	O
expanded	O
back	O
to	O
32-bit	O
versions	O
before	O
they	O
reached	O
the	O
arithmetic	B-General_Concept
logic	I-General_Concept
unit	I-General_Concept
(	O
ALU	O
)	O
,	O
meaning	O
that	O
no	O
changes	O
were	O
needed	O
in	O
the	O
core	O
logic	O
.	O
</s>
<s>
RISC	B-Architecture
II	O
proved	O
to	O
be	O
much	O
more	O
successful	O
in	O
silicon	O
and	O
in	O
testing	O
outperformed	O
almost	O
all	O
minicomputers	O
on	O
almost	O
all	O
tasks	O
.	O
</s>
<s>
For	O
instance	O
,	O
performance	O
ranged	O
from	O
85%	O
of	O
VAX	B-Device
speed	O
to	O
256%	O
on	O
a	O
variety	O
of	O
loads	O
.	O
</s>
<s>
RISC	B-Architecture
II	O
was	O
also	O
benched	O
against	O
the	O
famous	O
Motorola	B-Device
68000	I-Device
,	O
then	O
considered	O
to	O
be	O
the	O
best	O
commercial	O
chip	O
implementation	O
,	O
and	O
outperformed	O
it	O
by	O
140%	O
to	O
420%	O
.	O
</s>
<s>
Work	O
on	O
the	O
original	O
RISC	B-Architecture
designs	O
ended	O
with	O
RISC	B-Architecture
II	O
,	O
but	O
the	O
concept	O
lived	O
on	O
at	O
Berkeley	O
.	O
</s>
<s>
The	O
basic	O
core	O
was	O
re-used	O
in	O
SOAR	O
in	O
1984	O
,	O
basically	O
a	O
RISC	B-Architecture
converted	O
to	O
run	O
Smalltalk	B-Application
(	O
in	O
the	O
same	O
way	O
that	O
it	O
could	O
be	O
claimed	O
RISC	B-Architecture
ran	O
C	B-Language
)	O
,	O
and	O
later	O
in	O
the	O
similar	O
VLSI-BAM	O
that	O
ran	O
Prolog	B-Language
instead	O
of	O
Smalltalk	B-Application
.	O
</s>
<s>
Another	O
effort	O
was	O
SPUR	O
,	O
which	O
was	O
a	O
full	O
set	O
of	O
chips	O
needed	O
to	O
build	O
a	O
full	O
32-bit	O
workstation	B-Device
.	O
</s>
<s>
RISC	B-Architecture
is	O
less	O
famous	O
,	O
but	O
more	O
influential	O
,	O
for	O
being	O
the	O
basis	O
of	O
the	O
commercial	O
SPARC	B-Architecture
processor	O
design	O
from	O
Sun	O
Microsystems	O
.	O
</s>
<s>
It	O
was	O
the	O
SPARC	B-Architecture
that	O
first	O
clearly	O
demonstrated	O
the	O
power	O
of	O
the	O
RISC	B-Architecture
concept	O
;	O
when	O
they	O
shipped	O
in	O
the	O
first	O
Sun-4s	B-Device
they	O
outperformed	O
anything	O
on	O
the	O
market	O
.	O
</s>
<s>
This	O
led	O
to	O
virtually	O
every	O
Unix	B-Application
vendor	O
hurrying	O
for	O
a	O
RISC	B-Architecture
design	O
of	O
their	O
own	O
,	O
leading	O
to	O
designs	O
like	O
the	O
DEC	B-Device
Alpha	I-Device
and	O
PA-RISC	B-Device
,	O
while	O
Silicon	O
Graphics	O
(	O
SGI	O
)	O
purchased	O
MIPS	B-General_Concept
Computer	O
Systems	O
.	O
</s>
<s>
By	O
1986	O
,	O
most	O
large	O
chip	O
vendors	O
followed	O
,	O
working	O
on	O
efforts	O
like	O
the	O
Motorola	B-Architecture
88000	I-Architecture
,	O
Fairchild	B-General_Concept
Clipper	I-General_Concept
,	O
AMD	B-General_Concept
29000	I-General_Concept
and	O
the	O
PowerPC	B-Architecture
.	O
</s>
<s>
Sun	O
Microsystems	O
introduced	O
the	O
Scalable	B-Architecture
Processor	I-Architecture
Architecture	I-Architecture
(	O
SPARC	B-Architecture
)	O
RISC	B-Architecture
in	O
1987	O
.	O
</s>
<s>
Building	O
on	O
UC	O
Berkeley	B-General_Concept
RISC	I-General_Concept
and	O
Sun	O
compiler	O
and	O
operating	O
system	O
developments	O
,	O
SPARC	B-Architecture
architecture	O
was	O
highly	O
adaptable	O
to	O
evolving	O
semiconductor	O
,	O
software	O
,	O
and	O
system	O
technology	O
and	O
user	O
needs	O
.	O
</s>
<s>
The	O
architecture	O
delivered	O
the	O
highest	O
performance	O
,	O
scalable	O
workstations	B-Device
and	O
servers	O
,	O
for	O
engineering	O
,	O
business	O
,	O
Internet	O
,	O
and	O
cloud	O
computing	O
uses	O
.	O
</s>
<s>
Techniques	O
developed	O
for	O
and	O
alongside	O
the	O
idea	O
of	O
the	O
reduced	B-Architecture
instruction	I-Architecture
set	I-Architecture
have	O
also	O
been	O
adopted	O
in	O
successively	O
more	O
powerful	O
implementations	O
and	O
extensions	O
of	O
the	O
traditional	O
"	O
complex	O
"	O
x86	B-Operating_System
architecture	I-Operating_System
.	O
</s>
<s>
Much	O
of	O
a	O
modern	O
microprocessor	B-Architecture
's	O
transistor	O
count	O
is	O
devoted	O
to	O
large	O
caches	O
,	O
many	O
pipeline	B-General_Concept
stages	O
,	O
superscalar	B-General_Concept
instruction	O
dispatch	O
,	O
branch	B-General_Concept
prediction	I-General_Concept
and	O
other	O
modern	O
techniques	O
which	O
are	O
applicable	O
regardless	O
of	O
instruction	O
architecture	O
.	O
</s>
<s>
The	O
amount	O
of	O
silicon	O
dedicated	O
to	O
instruction	O
decoding	O
on	O
a	O
modern	O
x86	B-Operating_System
implementation	O
is	O
proportionately	O
quite	O
small	O
,	O
so	O
the	O
distinction	O
between	O
"	O
complex	O
"	O
and	O
RISC	B-Architecture
processor	I-Architecture
implementations	O
has	O
become	O
blurred	O
.	O
</s>
