<s>
The	B-Architecture
Berkeley	I-Architecture
IRAM	I-Architecture
project	I-Architecture
was	O
a	O
19962004	O
research	O
project	O
in	O
the	O
Computer	O
Science	O
Division	O
of	O
the	O
University	O
of	O
California	O
,	O
Berkeley	O
which	O
explored	O
computer	B-General_Concept
architecture	I-General_Concept
enabled	O
by	O
the	O
wide	O
bandwidth	O
between	O
memory	O
and	O
processor	O
made	O
possible	O
when	O
both	O
are	O
designed	O
on	O
the	O
same	O
integrated	O
circuit	O
(	O
chip	O
)	O
.	O
</s>
<s>
Since	O
it	O
was	O
envisioned	O
that	O
such	O
a	O
chip	O
would	O
consist	O
primarily	O
of	O
random-access	B-Architecture
memory	I-Architecture
(	O
RAM	B-Architecture
)	O
,	O
with	O
a	O
smaller	O
part	O
needed	O
for	O
the	O
central	B-General_Concept
processing	I-General_Concept
unit	I-General_Concept
(	O
CPU	O
)	O
,	O
the	O
research	O
team	O
used	O
the	O
term	O
"	O
Intelligent	O
RAM	B-Architecture
"	O
(	O
or	O
IRAM	O
)	O
to	O
describe	O
a	O
chip	O
with	O
this	O
architecture	O
.	O
</s>
<s>
Like	O
the	O
J	B-Device
–	I-Device
Machine	I-Device
project	O
at	O
MIT	O
,	O
the	O
primary	O
objective	O
of	O
the	O
research	O
was	O
to	O
avoid	O
the	O
Von	O
Neumann	O
bottleneck	O
which	O
occurs	O
when	O
the	O
connection	O
between	O
memory	O
and	O
CPU	O
is	O
a	O
relatively	O
narrow	O
memory	O
bus	O
between	O
separate	O
integrated	O
circuits	O
.	O
</s>
<s>
For	O
this	O
reason	O
,	O
the	O
integration	O
of	O
memory	O
and	O
processor	O
in	O
the	O
same	O
chip	O
has	O
(	O
for	O
the	O
most	O
part	O
)	O
been	O
limited	O
to	O
static	B-Architecture
random-access	I-Architecture
memory	I-Architecture
(	O
SRAM	O
)	O
,	O
which	O
may	O
be	O
implemented	O
using	O
circuit	O
technology	O
optimized	O
for	O
logic	O
performance	O
,	O
rather	O
than	O
the	O
denser	O
and	O
lower-cost	O
dynamic	O
random-access	B-Architecture
memory	I-Architecture
(	O
DRAM	O
)	O
,	O
which	O
is	O
not	O
.	O
</s>
<s>
For	O
this	O
reason	O
computer	B-General_Concept
architecture	I-General_Concept
employing	O
a	O
hierarchy	O
of	O
memory	O
systems	O
has	O
developed	O
,	O
in	O
which	O
static	O
memory	O
is	O
integrated	O
with	O
the	O
microprocessor	O
for	O
temporary	O
,	O
easily	O
accessible	O
storage	O
(	O
or	O
cache	O
)	O
of	O
data	O
which	O
is	O
also	O
retained	O
off-chip	O
in	O
DRAM	O
.	O
</s>
<s>
While	O
it	O
is	O
fair	O
to	O
say	O
that	O
Berkeley	O
IRAM	O
did	O
not	O
achieve	O
the	O
recognition	O
that	O
Berkeley	B-General_Concept
RISC	I-General_Concept
received	O
,	O
the	O
IRAM	O
project	O
was	O
nevertheless	O
influential	O
.	O
</s>
<s>
Its	O
publications	O
were	O
early	O
advocates	O
of	O
the	O
incorporation	O
of	O
vector	O
processing	O
and	O
vector	O
instruction	O
sets	O
into	O
microprocessors	O
,	O
and	O
several	O
commercial	O
microprocessors	O
,	O
such	O
as	O
the	O
Intel	O
Advanced	B-General_Concept
Vector	I-General_Concept
Extensions	I-General_Concept
(	O
AVX	O
)	O
,	O
subsequently	O
adopted	O
vector	O
processing	O
instruction	O
set	O
extensions	O
.	O
</s>
