<s>
The	O
Bellmac	B-General_Concept
32	I-General_Concept
is	O
a	O
microprocessor	B-Architecture
developed	O
by	O
Bell	O
Labs	O
 '	O
processor	O
division	O
in	O
1980	O
,	O
implemented	O
using	O
CMOS	B-Device
technology	O
and	O
was	O
the	O
first	O
microprocessor	B-Architecture
that	O
could	O
move	O
32	O
bits	O
in	O
one	O
clock	O
cycle	O
.	O
</s>
<s>
The	O
microprocessor	B-Architecture
contains	O
150,000	O
transistors	O
and	O
improved	O
on	O
the	O
speed	O
of	O
CMOS	B-Device
design	O
by	O
using	O
"	O
domino	O
circuits	O
"	O
.	O
</s>
<s>
It	O
was	O
designed	O
with	O
the	O
C	B-Language
programming	I-Language
language	I-Language
in	O
mind	O
.	O
</s>
<s>
After	O
its	O
creation	O
,	O
an	O
improved	O
version	O
was	O
produced	O
called	O
the	O
Bellmac	O
32A	O
,	O
then	O
cancelled	O
along	O
with	O
its	O
successor	O
,	O
the	O
"	B-Application
Hobbit	I-Application
"	I-Application
C-language	B-Application
Reduced	I-Application
Instruction	I-Application
Set	I-Application
Processor	I-Application
(	O
CRISP	O
)	O
.	O
</s>
<s>
The	O
Bellmac	B-General_Concept
32	I-General_Concept
processor	O
was	O
developed	O
by	O
AT&T	O
engineers	O
in	O
three	O
different	O
Bell	O
Labs	O
locations	O
:	O
Indian	O
Hill	O
,	O
Holmdel	O
and	O
Murray	O
Hill	O
.	O
</s>
<s>
The	O
development	O
of	O
the	O
Bellmac	B-General_Concept
32	I-General_Concept
produced	O
a	O
novel	O
circuit	O
design	O
technique	O
called	O
domino	B-General_Concept
logic	I-General_Concept
,	O
deemed	O
a	O
breakthrough	O
for	O
the	O
production	O
of	O
the	O
microprocessor	B-Architecture
.	O
</s>
<s>
Followup	O
design	O
meetings	O
resulted	O
in	O
the	O
Bellmac	O
32A	O
project	O
,	O
as	O
a	O
second	O
generation	O
of	O
the	O
Bellmac	O
microprocessor	B-Architecture
.	O
</s>
<s>
The	O
project	O
once	O
again	O
selected	O
CMOS	B-Device
technology	O
and	O
fixed	O
the	O
target	O
clock	O
frequency	O
at	O
6.2MHz	O
.	O
</s>
<s>
With	O
this	O
change	O
,	O
the	O
Bellmac	B-General_Concept
32	I-General_Concept
was	O
renamed	O
to	O
WE	B-General_Concept
32000	I-General_Concept
.	O
</s>
<s>
Updated	O
versions	O
of	O
the	O
chip	O
included	O
the	O
WE	B-General_Concept
32100	I-General_Concept
,	O
announced	O
in	O
June	O
1984	O
,	O
and	O
the	O
WE	O
32200	O
.	O
</s>
<s>
The	O
Bellmac	B-General_Concept
32	I-General_Concept
has	O
a	O
pipelined	B-General_Concept
architecture	I-General_Concept
with	O
an	O
instruction	O
fetch	O
unit	O
that	O
serves	O
to	O
control	O
access	O
to	O
main	O
memory	O
,	O
and	O
an	O
execution	O
unit	O
which	O
serves	O
to	O
monitor	O
the	O
process	O
and	O
manipulate	O
data	O
.	O
</s>
<s>
The	O
Bellmac	B-General_Concept
32	I-General_Concept
architecture	O
provides	O
a	O
variety	O
of	O
conveniences	O
for	O
programming	O
language	O
implementers	O
.	O
</s>
<s>
Four	O
privilege	O
levels	O
are	O
supported	O
by	O
the	O
Bellmac	B-General_Concept
32	I-General_Concept
architecture	O
.	O
</s>
<s>
For	O
the	O
exception-related	O
features	O
of	O
the	O
Bellmac	B-General_Concept
32	I-General_Concept
to	O
function	O
,	O
an	O
operating	O
system	O
kernel	O
is	O
also	O
expected	O
to	O
reside	O
in	O
each	O
process	O
's	O
virtual	O
address	O
space	O
since	O
an	O
exception	O
,	O
relying	O
on	O
a	O
controlled	O
transfer	O
,	O
will	O
not	O
change	O
the	O
virtual	O
memory	O
configuration	O
.	O
</s>
<s>
Although	O
various	O
operations	O
provided	O
by	O
the	O
Bellmac	B-General_Concept
32	I-General_Concept
architecture	O
support	O
high-level	O
languages	O
generally	O
,	O
specific	O
instructions	O
are	O
provided	O
that	O
support	O
C	B-Language
language	I-Language
conventions	O
,	O
notably	O
the	O
string	O
copy	O
and	O
string	O
end	O
instructions	O
which	O
rely	O
on	O
the	O
C	B-Language
language	I-Language
representation	O
of	O
terminating	O
character	O
strings	O
with	O
a	O
zero	B-Algorithm
byte	O
.	O
</s>
<s>
Bellmac	B-General_Concept
32	I-General_Concept
has	O
sixteen	O
32-bit	O
registers	O
.	O
</s>
<s>
Three	O
of	O
these	O
(	O
ISP	O
,	O
PCBP	O
,	O
PSW	O
)	O
are	O
privileged	O
,	O
used	O
to	O
support	O
the	O
operating	O
system	O
and	O
can	O
be	O
written	O
only	O
when	O
the	O
microprocessor	B-Architecture
is	O
in	O
kernel	O
mode	O
.	O
</s>
<s>
This	O
microprocessor	B-Architecture
has	O
169	O
instructions	O
,	O
which	O
are	O
optimized	O
for	O
executing	O
programs	O
written	O
in	O
the	O
C	B-Language
programming	I-Language
language	I-Language
.	O
</s>
<s>
Accordingly	O
,	O
the	O
format	O
of	O
character	O
strings	O
is	O
adapted	O
to	O
C	B-Language
language	I-Language
specifications	O
,	O
for	O
example	O
.	O
</s>
<s>
The	O
Bellmac	B-General_Concept
32	I-General_Concept
implements	O
multiple	O
types	O
of	O
memory	O
addressing	O
,	O
such	O
as	O
linear	O
,	O
immediate	O
8	O
,	O
16	O
or	O
32	O
bits	O
,	O
registration	O
,	O
register	O
indirect	O
,	O
short	O
shift	O
,	O
absolute	O
and	O
indirect	O
displacement	O
of	O
8	O
,	O
16	O
or	O
32	O
bits	O
.	O
</s>
<s>
The	O
WE	O
32x00	O
processors	O
were	O
used	O
in	O
the	O
AT&T	O
Computer	O
Systems	O
 '	O
3B	B-Device
series	I-Device
computers	I-Device
,	O
being	O
unveiled	O
as	O
commercially	O
available	O
products	O
in	O
the	O
form	O
of	O
the	O
3B2	B-Device
,	O
3B5	O
and	O
3B20	O
ranges	O
at	O
the	O
spring	O
1984	O
Comdex	O
show	O
.	O
</s>
<s>
In	O
mid-1985	O
,	O
AT&T	O
started	O
to	O
offer	O
the	O
WE	B-General_Concept
32100	I-General_Concept
and	O
associated	O
chipset	O
,	O
along	O
with	O
"	O
board-level	O
"	O
evaluation	O
systems	O
,	O
to	O
other	O
manufacturers	O
.	O
</s>
