<s>
The	O
back	B-Algorithm
end	I-Algorithm
of	I-Algorithm
line	I-Algorithm
(	O
BEOL	B-Algorithm
)	O
is	O
the	O
second	O
portion	O
of	O
IC	B-Architecture
fabrication	I-Architecture
where	O
the	O
individual	O
devices	O
(	O
transistors	O
,	O
capacitors	O
,	O
resistors	O
,	O
etc	O
.	O
)	O
</s>
<s>
get	O
interconnected	O
with	O
wiring	O
on	O
the	O
wafer	B-Architecture
,	O
the	O
metalization	O
layer	O
.	O
</s>
<s>
BEOL	B-Algorithm
generally	O
begins	O
when	O
the	O
first	O
layer	O
of	O
metal	O
is	O
deposited	O
on	O
the	O
wafer	B-Architecture
.	O
</s>
<s>
BEOL	B-Algorithm
includes	O
contacts	O
,	O
insulating	O
layers	O
(	O
dielectrics	O
)	O
,	O
metal	O
levels	O
,	O
and	O
bonding	O
sites	O
for	O
chip-to-package	O
connections	O
.	O
</s>
<s>
After	O
the	O
last	O
FEOL	B-Algorithm
step	O
,	O
there	O
is	O
a	O
wafer	B-Architecture
with	O
isolated	O
transistors	O
(	O
without	O
any	O
wires	O
)	O
.	O
</s>
<s>
In	O
BEOL	B-Algorithm
part	O
of	O
fabrication	B-Architecture
stage	O
contacts	O
(	O
pads	O
)	O
,	O
interconnect	O
wires	O
,	O
vias	O
and	O
dielectric	O
structures	O
are	O
formed	O
.	O
</s>
<s>
For	O
modern	O
IC	O
process	O
,	O
more	O
than	O
10	O
metal	O
layers	O
can	O
be	O
added	O
in	O
the	O
BEOL	B-Algorithm
.	O
</s>
<s>
Steps	O
of	O
the	O
BEOL	B-Algorithm
:	O
</s>
<s>
Vias	O
filled	O
by	O
Metal	B-Algorithm
CVD	I-Algorithm
process	O
.	O
</s>
<s>
After	O
BEOL	B-Algorithm
there	O
is	O
a	O
"	O
back-end	O
process	O
"	O
(	O
also	O
called	O
post-fab	O
)	O
,	O
which	O
is	O
done	O
not	O
in	O
the	O
cleanroom	O
,	O
often	O
by	O
a	O
different	O
company	O
.	O
</s>
<s>
It	O
includes	O
wafer	B-Algorithm
test	I-Algorithm
,	O
wafer	B-Algorithm
backgrinding	I-Algorithm
,	O
die	O
separation	O
,	O
die	O
tests	O
,	O
IC	B-Algorithm
packaging	I-Algorithm
and	O
final	O
test	O
.	O
</s>
