<s>
In	O
personal	B-Device
computer	I-Device
microprocessor	B-Architecture
architecture	O
,	O
a	O
back-side	B-Architecture
bus	I-Architecture
(	O
BSB	O
)	O
,	O
or	O
backside	B-Architecture
bus	I-Architecture
,	O
was	O
a	O
computer	B-General_Concept
bus	I-General_Concept
used	O
on	O
early	O
Intel	O
platforms	O
to	O
connect	O
the	O
CPU	B-General_Concept
to	O
CPU	B-General_Concept
cache	I-General_Concept
memory	I-General_Concept
,	O
usually	O
off-die	O
L2	O
.	O
</s>
<s>
If	O
a	O
design	O
utilizes	O
it	O
along	O
with	O
a	O
front-side	B-Architecture
bus	I-Architecture
(	O
FSB	O
)	O
,	O
it	O
is	O
said	O
to	O
use	O
a	O
dual-bus	O
architecture	O
,	O
or	O
in	O
Intel	O
's	O
terminology	O
Dual	B-Architecture
Independent	I-Architecture
Bus	I-Architecture
(	O
DIB	O
)	O
architecture	O
.	O
</s>
<s>
The	O
back-side	B-Architecture
bus	I-Architecture
architecture	O
evolved	O
when	O
newer	O
processors	O
like	O
the	O
second-generation	O
Pentium	B-General_Concept
III	I-General_Concept
began	O
to	O
incorporate	O
on-die	O
L2	O
cache	O
,	O
which	O
at	O
the	O
time	O
was	O
advertised	O
as	O
Advanced	O
Transfer	O
Cache	O
,	O
but	O
Intel	O
continued	O
to	O
refer	O
to	O
the	O
Dual	B-Architecture
Independent	I-Architecture
Bus	I-Architecture
till	O
the	O
end	O
of	O
Pentium	B-General_Concept
III	I-General_Concept
.	O
</s>
<s>
BSB	O
is	O
an	O
improvement	O
over	O
the	O
older	O
practice	O
of	O
using	O
a	O
single	O
system	B-Architecture
bus	I-Architecture
,	O
because	O
a	O
single	O
bus	O
typically	O
became	O
a	O
severe	O
bottleneck	O
as	O
CPUs	O
and	O
memory	O
speeds	O
increased	O
.	O
</s>
<s>
Due	O
to	O
its	O
dedicated	O
nature	O
,	O
the	O
back-side	B-Architecture
bus	I-Architecture
can	O
be	O
optimized	O
for	O
communication	O
with	O
cache	O
,	O
thus	O
eliminating	O
protocol	O
overheads	O
and	O
additional	O
signals	O
that	O
are	O
required	O
on	O
a	O
general-purpose	O
bus	O
.	O
</s>
<s>
Cache	O
connected	O
with	O
a	O
BSB	O
was	O
initially	O
external	O
to	O
the	O
microprocessor	B-Architecture
die	O
,	O
but	O
now	O
is	O
usually	O
on-die	O
.	O
</s>
<s>
In	O
the	O
latter	O
case	O
,	O
the	O
BSB	O
clock	O
frequency	O
is	O
typically	O
equal	O
to	O
the	O
processor	O
's	O
,	O
and	O
the	O
back-side	B-Architecture
bus	I-Architecture
can	O
also	O
be	O
made	O
much	O
wider	O
(	O
256-bit	O
,	O
512-bit	O
)	O
than	O
either	O
off-chip	O
or	O
on-chip	O
FSB	O
.	O
</s>
<s>
The	O
dual-bus	O
architecture	O
was	O
used	O
in	O
a	O
number	O
of	O
designs	O
,	O
including	O
the	O
IBM	O
and	O
Freescale	O
(	O
formerly	O
the	O
semiconductor	O
division	O
of	O
Motorola	O
)	O
PowerPC	B-Architecture
processors	I-Architecture
(	O
certain	O
PowerPC	B-Architecture
604	O
models	O
,	O
the	O
PowerPC	B-Device
7xx	I-Device
family	O
,	O
and	O
the	O
Freescale	O
7xxx	B-General_Concept
line	O
)	O
,	O
as	O
well	O
as	O
the	O
Intel	B-Device
Pentium	I-Device
Pro	I-Device
,	O
Pentium	B-General_Concept
II	I-General_Concept
and	O
early	O
Pentium	B-General_Concept
III	I-General_Concept
processors	O
,	O
</s>
