<s>
The	O
Atmel	B-Device
AVR	I-Device
instruction	I-Device
set	I-Device
is	O
the	O
machine	B-Language
language	I-Language
for	O
the	O
Atmel	B-Architecture
AVR	I-Architecture
,	O
a	O
modified	B-Device
Harvard	I-Device
architecture	I-Device
8-bit	O
RISC	B-Architecture
single	B-Architecture
chip	I-Architecture
microcontroller	I-Architecture
which	O
was	O
developed	O
by	O
Atmel	O
in	O
1996	O
.	O
</s>
<s>
The	O
AVR	O
was	O
one	O
of	O
the	O
first	O
microcontroller	B-Architecture
families	O
to	O
use	O
on-chip	O
flash	B-Device
memory	I-Device
for	O
program	O
storage	O
.	O
</s>
<s>
C	O
Carry	B-Algorithm
flag	I-Algorithm
.	O
</s>
<s>
The	O
INC	O
and	O
DEC	O
instructions	O
do	O
not	O
modify	O
the	O
carry	B-Algorithm
flag	I-Algorithm
,	O
so	O
they	O
may	O
be	O
used	O
to	O
loop	O
over	O
multi-byte	O
arithmetic	O
operations	O
.	O
</s>
<s>
Z	O
Zero	B-Algorithm
flag	I-Algorithm
.	O
</s>
<s>
N	O
Negative	B-Algorithm
flag	I-Algorithm
.	O
</s>
<s>
V	O
Overflow	B-Algorithm
flag	I-Algorithm
.	O
</s>
<s>
S	O
Sign	B-Algorithm
flag	I-Algorithm
.	O
</s>
<s>
H	O
Half-carry	B-Device
flag	I-Device
.	O
</s>
<s>
I	O
Interrupt	B-Device
flag	I-Device
.	O
</s>
<s>
I/O	O
registers	O
have	O
a	O
dedicated	O
6-bit	O
address	O
space	O
,	O
the	O
lower	O
half	O
of	O
which	O
is	O
bit-addressable	O
;	O
some	O
parts	O
have	O
I/O	O
registers	O
outside	O
this	O
address	O
space	O
,	O
which	O
are	O
called	O
"	O
extended	O
I/O	O
"	O
and	O
are	O
only	O
accessible	O
as	O
memory-mapped	B-Architecture
I/O	I-Architecture
in	O
the	O
data	O
address	O
space	O
.	O
</s>
<s>
The	O
data	O
address	O
space	O
maps	O
the	O
32	O
general-purpose	O
registers	O
,	O
all	O
the	O
I/O	O
registers	O
(	O
including	O
those	O
also	O
accessible	O
through	O
the	O
I/O	B-Architecture
address	I-Architecture
space	O
)	O
,	O
and	O
the	O
RAM	O
;	O
it	O
can	O
be	O
addressed	O
either	O
directly	O
or	O
indirectly	O
through	O
the	O
X	O
,	O
Y	O
and	O
Z	O
pointer	O
registers	O
,	O
prepended	O
if	O
necessary	O
by	O
RAMPX	O
,	O
RAMPY	O
and	O
RAMPZ	O
respectively	O
.	O
</s>
<s>
The	O
EEPROM	B-General_Concept
is	O
memory-mapped	O
in	O
some	O
devices	O
;	O
in	O
others	O
,	O
it	O
is	O
not	O
directly	O
addressable	O
and	O
is	O
instead	O
accessed	O
through	O
address	O
,	O
data	O
and	O
control	O
I/O	O
registers	O
.	O
</s>
<s>
These	O
are	O
usually	O
written	O
as	O
"	O
(	O
)	O
"	O
through	O
"	O
(	O
)	O
"	O
,	O
where	O
the	O
first	O
item	O
is	O
the	O
I/O	B-Architecture
address	I-Architecture
and	O
the	O
second	O
,	O
in	O
parentheses	O
,	O
the	O
data	O
address	O
.	O
</s>
<s>
IO5	O
is	O
a	O
5-bit	O
I/O	B-Architecture
address	I-Architecture
covering	O
the	O
bit-addressable	O
part	O
of	O
the	O
I/O	B-Architecture
address	I-Architecture
space	O
,	O
i.e.	O
</s>
<s>
Not	O
all	O
instructions	O
are	O
implemented	O
in	O
all	O
Atmel	B-Architecture
AVR	I-Architecture
controllers	O
.	O
</s>
<s>
The	O
XMEGA	B-Architecture
cores	O
do	O
not	O
add	O
new	O
instructions	O
per	O
se	O
,	O
but	O
make	O
some	O
significant	O
changes	O
:	O
</s>
<s>
The	O
memory	O
map	O
is	O
reorganized	O
,	O
eliminating	O
memory-mapping	O
of	O
the	O
processor	O
register	O
file	O
(	O
so	O
I/O	B-Architecture
ports	I-Architecture
begin	O
at	O
RAM	O
address	O
0	O
)	O
and	O
expanding	O
the	O
I/O	B-Architecture
port	I-Architecture
range	O
.	O
</s>
<s>
Now	O
the	O
first	O
4K	O
is	O
special	O
function	O
registers	O
,	O
the	O
second	O
4K	O
is	O
data	O
flash	B-Device
,	O
and	O
normal	O
RAM	O
begins	O
at	O
8K	O
.	O
</s>
<s>
Other	O
multi-byte	O
registers	O
are	O
provided	O
with	O
shadow	O
registers	O
to	O
enable	O
atomic	B-General_Concept
read	O
and	O
write	O
.	O
</s>
<s>
When	O
the	O
lowest-order	O
byte	O
is	O
read	O
,	O
the	O
higher-order	O
bytes	O
are	O
copied	O
to	O
the	O
shadow	O
registers	O
,	O
so	O
reading	O
them	O
later	O
produces	O
a	O
snapshot	B-Application
of	O
the	O
register	O
at	O
the	O
time	O
of	O
the	O
first	O
read	O
.	O
</s>
<s>
Later	O
XMEGA	B-Architecture
cores	O
(	O
specifically	O
,	O
the	O
B	O
,	O
C	O
,	O
and	O
AU	O
models	O
such	O
as	O
the	O
ATxmega16A4U	O
,	O
but	O
not	O
the	O
earlier	O
A	O
,	O
D	O
and	O
E	O
models	O
such	O
as	O
the	O
ATxmega16D4	O
)	O
add	O
four	O
atomic	B-General_Concept
read-modify-write	B-Operating_System
instructions	O
:	O
exchange	O
(	O
XCH	O
)	O
,	O
load-and-set	O
,	O
load-and-clear	O
,	O
and	O
load-and-toggle	O
.	O
</s>
<s>
These	O
help	O
coordinate	O
with	O
direct	B-General_Concept
memory	I-General_Concept
access	I-General_Concept
peripherals	O
,	O
notably	O
a	O
USB	B-Protocol
controller	O
.	O
</s>
<s>
It	O
omits	O
all	O
RAM	O
except	O
for	O
the	O
32	O
registers	O
mapped	O
at	O
address	O
0	O
–	O
31	O
and	O
the	O
I/O	B-Architecture
ports	I-Architecture
at	O
addresses	O
32	O
–	O
95	O
.	O
</s>
<s>
A	O
second	O
,	O
more	O
successful	O
attempt	O
to	O
subset	O
the	O
AVR	B-Device
instruction	I-Device
set	I-Device
is	O
the	O
"	O
AVR	O
tiny	O
"	O
core	O
.	O
</s>
<s>
The	O
registers	O
are	O
also	O
not	O
memory-mapped	O
,	O
with	O
I/O	B-Architecture
ports	I-Architecture
from	O
0	O
–	O
63	O
and	O
general-purpose	O
RAM	O
beginning	O
at	O
address	O
64	O
.	O
</s>
<s>
The	O
smallest	O
cores	O
have	O
≤256	O
bytes	O
of	O
data	O
address	O
space	O
(	O
meaning	O
≤128	O
bytes	O
of	O
RAM	O
after	O
I/O	B-Architecture
ports	I-Architecture
and	O
other	O
reserved	O
addresses	O
are	O
removed	O
)	O
and	O
≤8192	O
bytes	O
(	O
8	O
KiB	O
)	O
of	O
program	O
ROM	O
.	O
</s>
<s>
The	O
Atmel	B-Architecture
AVR	I-Architecture
uses	O
many	O
split	O
fields	O
,	O
where	O
bits	O
are	O
not	O
contiguous	O
in	O
the	O
instruction	O
word	O
.	O
</s>
