<s>
Athlon	B-Architecture
is	O
the	O
brand	O
name	O
applied	O
to	O
a	O
series	O
of	O
x86-compatible	B-Operating_System
microprocessors	B-Architecture
designed	O
and	O
manufactured	O
by	O
AMD	O
.	O
</s>
<s>
The	O
original	O
Athlon	B-Architecture
(	O
now	O
called	O
Athlon	B-Architecture
Classic	O
)	O
was	O
the	O
first	O
seventh-generation	O
x86	B-Operating_System
processor	O
and	O
the	O
first	O
desktop	O
processor	O
to	O
reach	O
speeds	O
of	O
one	O
gigahertz	O
(	O
GHz	O
)	O
.	O
</s>
<s>
Over	O
the	O
years	O
AMD	O
has	O
used	O
the	O
Athlon	B-Architecture
name	O
with	O
the	O
64-bit	O
Athlon	B-Architecture
64	O
architecture	O
,	O
the	O
Athlon	B-Architecture
II	O
,	O
and	O
Accelerated	B-Architecture
Processing	I-Architecture
Unit	I-Architecture
(	O
APU	O
)	O
chips	O
targeting	O
the	O
Socket	O
AM1	O
desktop	O
SoC	B-Architecture
architecture	O
,	O
and	O
Socket	O
AM4	O
Zen	O
microarchitecture	O
.	O
</s>
<s>
The	O
modern	O
Zen-based	O
Athlon	B-Architecture
with	O
a	O
Radeon	B-Device
Graphics	I-Device
processor	O
was	O
introduced	O
in	O
2019	O
as	O
AMD	O
's	O
highest-performance	O
entry-level	O
processor	O
.	O
</s>
<s>
Athlon	B-Architecture
comes	O
from	O
the	O
Ancient	O
Greek	O
(	O
athlon	B-Architecture
)	O
,	O
meaning	O
"	O
(	O
sport	O
)	O
contest	O
"	O
,	O
or	O
"	O
prize	O
of	O
a	O
contest	O
"	O
,	O
or	O
"	O
place	O
of	O
a	O
contest	O
;	O
arena	O
"	O
.	O
</s>
<s>
With	O
the	O
Athlon	B-Architecture
name	O
originally	O
used	O
for	O
AMD	O
's	O
high-end	O
processors	O
,	O
AMD	O
currently	O
uses	O
Athlon	B-Architecture
for	O
budget	O
APUs	O
with	O
integrated	O
graphics	O
.	O
</s>
<s>
AMD	O
positions	O
the	O
Athlon	B-Architecture
against	O
its	O
rival	O
,	O
the	O
Intel	B-General_Concept
Pentium	I-General_Concept
.	O
</s>
<s>
The	O
first	O
Athlon	B-Architecture
processor	O
was	O
a	O
result	O
of	O
AMD	O
's	O
development	O
of	O
K7	B-Architecture
processors	O
in	O
the	O
1990s	O
.	O
</s>
<s>
AMD	O
founder	O
and	O
then-CEO	O
Jerry	O
Sanders	O
aggressively	O
pursued	O
strategic	O
partnerships	O
and	O
engineering	O
talent	O
in	O
the	O
late	O
1990s	O
,	O
working	O
to	O
build	O
on	O
earlier	O
successes	O
in	O
the	O
PC	O
market	O
with	O
the	O
AMD	B-Architecture
K6	I-Architecture
processor	O
line	O
.	O
</s>
<s>
One	O
major	O
partnership	O
announced	O
in	O
1998	O
paired	O
AMD	O
with	O
semiconductor	O
giant	O
Motorola	O
to	O
co-develop	O
copper-based	O
semiconductor	O
technology	O
,	O
resulting	O
in	O
the	O
K7	B-Architecture
project	O
being	O
the	O
first	O
commercial	O
processor	O
to	O
utilize	O
copper	O
fabrication	O
technology	O
.	O
</s>
<s>
The	O
K7	B-Architecture
design	O
team	O
was	O
led	O
by	O
Dirk	O
Meyer	O
,	O
who	O
had	O
previously	O
worked	O
as	O
a	O
lead	O
engineer	O
at	O
DEC	O
on	O
multiple	O
Alpha	B-Device
microprocessors	B-Architecture
.	O
</s>
<s>
When	O
DEC	O
was	O
sold	O
to	O
Compaq	O
in	O
1998	O
and	O
discontinued	O
Alpha	B-Device
processor	I-Device
development	O
,	O
Sanders	O
brought	O
most	O
of	O
the	O
Alpha	B-Device
design	O
team	O
to	O
the	O
K7	B-Architecture
project	O
.	O
</s>
<s>
This	O
added	O
to	O
the	O
previously	O
acquired	O
NexGen	O
K6	B-Architecture
team	O
,	O
which	O
already	O
included	O
engineers	O
such	O
as	O
Vinod	O
Dham	O
.	O
</s>
<s>
The	O
AMD	B-Architecture
Athlon	I-Architecture
processor	O
launched	O
on	O
June	O
23	O
,	O
1999	O
,	O
with	O
general	O
availability	O
by	O
August	O
1999	O
.	O
</s>
<s>
Subsequently	O
,	O
from	O
August	O
1999	O
until	O
January	O
2002	O
,	O
this	O
initial	O
K7	B-Architecture
processor	O
was	O
the	O
fastest	O
x86	B-Operating_System
chip	O
in	O
the	O
world	O
.	O
</s>
<s>
Wrote	O
the	O
Los	O
Angeles	O
Times	O
on	O
October5	O
,	O
1999	O
:	O
"	O
AMD	O
has	O
historically	O
trailed	O
Intel	O
’s	O
fastest	O
processors	O
,	O
but	O
has	O
overtaken	O
the	O
industry	O
leader	O
with	O
the	O
new	O
Athlon	B-Architecture
.	O
</s>
<s>
Analysts	O
say	O
the	O
Athlon	B-Architecture
,	O
which	O
will	O
be	O
used	O
by	O
Compaq	O
,	O
IBM	O
and	O
other	O
manufacturers	O
in	O
their	O
most	O
powerful	O
PCs	O
,	O
is	O
significantly	O
faster	O
than	O
Intel	O
’s	O
flagship	O
Pentium	B-General_Concept
III	O
,	O
which	O
runs	O
at	O
a	O
top	O
speed	O
of	O
600MHz.	O
"	O
</s>
<s>
By	O
working	O
with	O
Motorola	O
,	O
AMD	O
had	O
been	O
able	O
to	O
refine	O
copper	O
interconnect	O
manufacturing	O
about	O
one	O
year	O
before	O
Intel	O
,	O
with	O
the	O
revised	O
process	O
permitting	O
180-nanometer	B-Algorithm
processor	O
production	O
.	O
</s>
<s>
The	O
accompanying	O
die-shrink	O
resulted	O
in	O
lower	O
power	O
consumption	O
,	O
permitting	O
AMD	O
to	O
increase	O
Athlon	B-Architecture
clock	O
speeds	O
to	O
the	O
1GHz	O
range	O
.	O
</s>
<s>
The	O
Athlon	B-Architecture
architecture	O
also	O
used	O
the	O
EV6	O
bus	O
licensed	O
from	O
DEC	O
as	O
its	O
main	O
system	O
bus	O
,	O
allowing	O
AMD	O
to	O
develop	O
its	O
own	O
products	O
without	O
needing	O
to	O
license	O
Intel	O
's	O
GTL+	B-General_Concept
bus	O
.	O
</s>
<s>
By	O
the	O
summer	O
of	O
2000	O
,	O
AMD	O
was	O
shipping	O
Athlons	B-Architecture
at	O
high	O
volume	O
,	O
and	O
the	O
chips	O
were	O
being	O
used	O
in	O
systems	O
by	O
Gateway	O
,	O
Hewlett-Packard	O
,	O
and	O
Fujitsu	O
Siemens	O
Computers	O
among	O
others	O
.	O
</s>
<s>
The	O
second-generation	O
Athlon	B-Architecture
,	O
the	O
Thunderbird	O
,	O
debuted	O
in	O
2000	O
.	O
</s>
<s>
AMD	O
released	O
the	O
AthlonXP	O
the	O
following	O
year	O
,	O
and	O
the	O
AthlonXP	O
's	O
immediate	O
successor	O
,	O
the	O
Athlon	B-Architecture
64	O
,	O
was	O
an	O
AMD64-architecture	O
microprocessor	B-Architecture
released	O
in	O
2003	O
.	O
</s>
<s>
After	O
the	O
2007	O
launch	O
of	O
the	O
Phenom	O
processors	O
,	O
the	O
Athlon	B-Architecture
name	O
was	O
also	O
used	O
for	O
mid-range	O
processors	O
,	O
positioned	O
above	O
brands	O
such	O
as	O
Sempron	O
.	O
</s>
<s>
The	O
Athlon	B-Architecture
64	O
X2	O
was	O
released	O
in	O
2005	O
as	O
the	O
first	O
native	O
dual-core	O
desktop	O
CPU	O
designed	O
by	O
AMD	O
,	O
and	O
the	O
Athlon	B-Architecture
X2	O
was	O
a	O
subsequent	O
family	O
based	O
on	O
the	O
Athlon64X2	O
.	O
</s>
<s>
Introduced	O
in	O
2009	O
,	O
Athlon	B-Architecture
II	O
was	O
a	O
dual-core	O
family	O
of	O
Athlon	B-Architecture
chips	O
.	O
</s>
<s>
A	O
USD$55	O
low-power	O
Athlon	B-Architecture
200GE	O
with	O
a	O
Radeon	B-Device
graphics	I-Device
processor	O
was	O
introduced	O
in	O
September	O
2018	O
,	O
sitting	O
under	O
the	O
Ryzen	O
3	O
2200G	O
.	O
</s>
<s>
This	O
iteration	O
of	O
Athlon	B-Architecture
used	O
AMD	O
's	O
Zen-based	O
Raven	O
Ridge	O
core	O
,	O
which	O
in	O
turn	O
had	O
debuted	O
in	O
Ryzen	O
with	O
Radeon	B-Device
graphics	I-Device
processors	O
.	O
</s>
<s>
With	O
the	O
release	O
,	O
AMD	O
began	O
using	O
the	O
Athlon	B-Architecture
brand	O
name	O
to	O
refer	O
to	O
"	O
low-cost	O
,	O
high-volume	O
products	O
"	O
,	O
in	O
a	O
situation	O
similar	O
to	O
both	O
Intel	O
's	O
Celeron	B-Device
and	O
Pentium	B-General_Concept
Gold	O
.	O
</s>
<s>
The	O
modern	O
Athlon	B-Architecture
3000G	O
was	O
introduced	O
in	O
2019	O
and	O
was	O
positioned	O
as	O
AMD	O
's	O
highest-performance	O
entry-level	O
processor	O
.	O
</s>
<s>
AMD	O
positions	O
the	O
Athlon	B-Architecture
against	O
its	O
rival	O
,	O
the	O
Intel	B-General_Concept
Pentium	I-General_Concept
.	O
</s>
<s>
While	O
CPU	O
processing	O
performance	O
is	O
in	O
the	O
same	O
ballpark	O
,	O
the	O
Athlon	B-Architecture
3000G	O
uses	O
Radeon	B-Device
Vega	I-Device
graphics	O
,	O
which	O
are	O
rated	O
as	O
more	O
powerful	O
than	O
the	O
Pentium	B-General_Concept
's	O
Intel	B-Application
UHD	I-Application
Graphics	I-Application
.	O
</s>
<s>
The	O
AMD	O
Athlon	B-Architecture
processor	O
launched	O
on	O
June	O
23	O
,	O
1999	O
,	O
with	O
general	O
availability	O
by	O
August	O
1999	O
.	O
</s>
<s>
Subsequently	O
,	O
from	O
August	O
1999	O
until	O
January	O
2002	O
,	O
this	O
initial	O
K7	B-Architecture
processor	O
was	O
the	O
fastest	O
x86	B-Operating_System
chip	O
in	O
the	O
world	O
.	O
</s>
<s>
In	O
commercial	O
terms	O
,	O
the	O
Athlon	B-Architecture
"	O
Classic	O
"	O
was	O
an	O
enormous	O
success	O
.	O
</s>
<s>
The	O
Athlon	B-Architecture
Classic	O
is	O
a	O
cartridge-based	O
processor	O
,	O
named	O
Slot	O
A	O
and	O
similar	O
to	O
Intel	O
's	O
cartridge	O
Slot	O
1	O
used	O
for	O
PentiumII	O
and	O
PentiumIII	O
.	O
</s>
<s>
It	O
used	O
the	O
same	O
,	O
commonly	O
available	O
,	O
physical	O
242-pin	O
connector	O
used	O
by	O
Intel	O
Slot1	O
processors	O
but	O
rotated	O
by	O
180degrees	O
to	O
connect	O
the	O
processor	O
to	O
the	O
motherboard	B-Device
.	O
</s>
<s>
The	O
cartridge	O
assembly	O
allowed	O
the	O
use	O
of	O
higher-speed	O
cache	O
memory	O
modules	O
than	O
could	O
be	O
put	O
on	O
(	O
or	O
reasonably	O
bundled	O
with	O
)	O
motherboards	B-Device
at	O
the	O
time	O
.	O
</s>
<s>
Similar	O
to	O
the	O
PentiumII	O
and	O
the	O
Katmai-based	O
PentiumIII	O
,	O
the	O
Athlon	B-Architecture
Classic	O
contained	O
512KB	O
of	O
L2	O
cache	O
.	O
</s>
<s>
This	O
high-speed	O
SRAM	B-Architecture
cache	O
was	O
run	O
at	O
a	O
divisor	O
of	O
the	O
processor	O
clock	O
and	O
was	O
accessed	O
via	O
its	O
own	O
64-bit	O
back-side	B-Architecture
bus	I-Architecture
,	O
allowing	O
the	O
processor	O
to	O
service	O
both	O
front-side	B-Architecture
bus	I-Architecture
requests	O
and	O
cache	O
accesses	O
simultaneously	O
,	O
as	O
compared	O
to	O
pushing	O
everything	O
through	O
the	O
front-side	B-Architecture
bus	I-Architecture
.	O
</s>
<s>
The	O
Argon-based	O
Athlon	B-Architecture
contained	O
22	O
million	O
transistors	O
and	O
measured	O
184mm2	O
.	O
</s>
<s>
"	O
Pluto	O
"	O
and	O
"	O
Orion	O
"	O
Athlons	B-Architecture
were	O
fabricated	O
in	O
a	O
0.18μm	O
process	O
.	O
</s>
<s>
The	O
Athlon	B-Architecture
's	O
CPU	B-General_Concept
cache	I-General_Concept
consisted	O
of	O
the	O
typical	O
two	O
levels	O
.	O
</s>
<s>
Athlon	B-Architecture
was	O
the	O
first	O
x86	B-Operating_System
processor	O
with	O
a	O
128KB	O
split	O
level-1	O
cache	O
;	O
a	O
2-way	B-General_Concept
associative	I-General_Concept
cache	O
separated	O
into	O
2×64KB	O
for	O
data	O
and	O
instructions	O
(	O
a	O
concept	O
from	O
Harvard	B-Architecture
architecture	I-Architecture
)	O
.	O
</s>
<s>
SRAM	B-Architecture
cache	O
designs	O
at	O
the	O
time	O
were	O
incapable	O
of	O
keeping	O
up	O
with	O
the	O
Athlon	B-Architecture
's	O
clock	O
scalability	O
,	O
resulting	O
in	O
compromised	O
CPU	O
clock	O
speeds	O
in	O
some	O
computers	O
.	O
</s>
<s>
With	O
later	O
Athlon	B-Architecture
models	O
,	O
AMD	O
would	O
integrate	O
the	O
L2	O
cache	O
onto	O
the	O
processor	O
itself	O
,	O
removing	O
dependence	O
on	O
external	O
cache	O
chips	O
.	O
</s>
<s>
The	O
Slot-A	O
Athlons	B-Architecture
were	O
the	O
first	O
multiplier-locked	O
CPUs	O
from	O
AMD	O
,	O
preventing	O
users	O
from	O
setting	O
their	O
own	O
desired	O
clock	O
speed	O
.	O
</s>
<s>
This	O
was	O
done	O
by	O
AMD	O
in	O
part	O
to	O
hinder	O
CPU	O
remarking	O
and	O
overclocking	B-Application
by	O
resellers	O
,	O
which	O
could	O
result	O
in	O
inconsistent	O
performance	O
.	O
</s>
<s>
AMD	O
designed	O
the	O
CPU	O
with	O
more	O
robust	O
x86	B-Operating_System
instruction	O
decoding	O
capabilities	O
than	O
that	O
of	O
K6	B-Architecture
,	O
to	O
enhance	O
its	O
ability	O
to	O
keep	O
more	O
data	O
in-flight	O
at	O
once	O
.	O
</s>
<s>
The	O
critical	O
branch-predictor	O
unit	O
was	O
enhanced	O
compared	O
to	O
the	O
K6	B-Architecture
.	O
</s>
<s>
Deeper	O
pipelining	B-General_Concept
with	O
more	O
stages	O
allowed	O
higher	O
clock	O
speeds	O
to	O
be	O
attained	O
.	O
</s>
<s>
Like	O
the	O
AMD	O
K5	O
and	O
K6	B-Architecture
,	O
the	O
Athlon	B-Architecture
dynamically	O
buffered	O
internal	O
micro-instructions	O
at	O
runtime	O
resulting	O
from	O
parallel	O
x86	B-Operating_System
instruction	O
decoding	O
.	O
</s>
<s>
The	O
CPU	O
is	O
an	O
out-of-order	B-General_Concept
design	O
,	O
again	O
like	O
previous	O
post-5x86	O
AMD	O
CPUs	O
.	O
</s>
<s>
The	O
Athlon	B-Architecture
utilizes	O
the	O
Alpha	B-General_Concept
21264	I-General_Concept
's	O
EV6	O
bus	O
architecture	O
with	O
double	O
data	O
rate	O
(	O
DDR	O
)	O
technology	O
.	O
</s>
<s>
AMD	O
ended	O
its	O
long-time	O
handicap	O
with	O
floating	B-Algorithm
point	I-Algorithm
x87	B-Application
performance	O
by	O
designing	O
a	O
super-pipelined	O
,	O
out-of-order	B-General_Concept
,	O
triple-issue	O
floating-point	B-General_Concept
unit	I-General_Concept
(	O
FPU	O
)	O
.	O
</s>
<s>
Each	O
of	O
its	O
three	O
units	O
could	O
independently	O
calculate	O
an	O
optimal	O
type	O
of	O
instructions	O
with	O
some	O
redundancy	O
,	O
making	O
it	O
possible	O
to	O
operate	O
on	O
more	O
than	O
one	O
floating-point	B-Algorithm
instruction	O
at	O
once	O
.	O
</s>
<s>
This	O
FPU	O
was	O
a	O
huge	O
step	O
forward	O
for	O
AMD	O
,	O
helping	O
compete	O
with	O
Intel	O
's	O
P6	B-Device
FPU	O
.	O
</s>
<s>
The	O
3DNow	B-General_Concept
!	I-General_Concept
</s>
<s>
floating-point	B-Algorithm
SIMD	B-Device
technology	O
,	O
again	O
present	O
,	O
received	O
some	O
revisions	O
and	O
was	O
renamed	O
"	O
Enhanced	O
3DNow	B-General_Concept
!	I-General_Concept
"	O
</s>
<s>
Additions	O
included	O
DSP	B-General_Concept
instructions	O
and	O
the	O
extended	B-Device
MMX	I-Device
subset	O
of	O
Intel	O
SSE	B-General_Concept
.	O
</s>
<s>
MMX	B-Architecture
,	O
3DNow	B-General_Concept
!	I-General_Concept
</s>
<s>
The	O
second-generation	O
Athlon	B-Architecture
,	O
the	O
Thunderbird	O
or	O
T-Bird	O
,	O
debuted	O
on	O
June4	O
,	O
2000	O
.	O
</s>
<s>
This	O
version	O
of	O
the	O
Athlon	B-Architecture
was	O
available	O
in	O
a	O
traditional	O
pin-grid	B-Algorithm
array	I-Algorithm
(	O
PGA	O
)	O
format	O
that	O
plugged	O
into	O
a	O
socket	O
(	O
"	O
Socket	O
A	O
"	O
)	O
on	O
the	O
motherboard	B-Device
,	O
or	O
packaged	O
as	O
a	O
SlotA	O
cartridge	O
.	O
</s>
<s>
The	O
major	O
difference	O
between	O
it	O
and	O
the	O
Athlon	B-Architecture
Classic	O
was	O
cache	O
design	O
,	O
with	O
AMD	O
adding	O
in	O
256KB	O
of	O
on-chip	O
,	O
full-speed	O
exclusive	O
cache	O
.	O
</s>
<s>
The	O
Thunderbird	O
was	O
"	O
cherished	O
by	O
many	O
for	O
its	O
overclockability	O
"	O
and	O
proved	O
commercially	O
successful	O
,	O
as	O
AMD	O
's	O
most	O
successful	O
product	O
since	O
the	O
Am386DX-40	B-Device
ten	O
years	O
earlier	O
.	O
</s>
<s>
AMD	O
's	O
new	O
fab	B-Algorithm
facility	O
in	O
Dresden	O
increased	O
production	O
for	O
AMD	O
overall	O
and	O
put	O
out	O
Thunderbirds	O
at	O
a	O
fast	O
rate	O
,	O
with	O
the	O
process	O
technology	O
improved	O
by	O
a	O
switch	O
to	O
copper	O
interconnects	O
.	O
</s>
<s>
After	O
several	O
versions	O
were	O
released	O
in	O
2000	O
and	O
2001	O
of	O
the	O
Thunderbird	O
,	O
the	O
last	O
Athlon	B-Architecture
processor	O
using	O
the	O
Thunderbird	O
core	O
was	O
released	O
in	O
2001	O
in	O
the	O
summer	O
,	O
at	O
which	O
point	O
speeds	O
were	O
at	O
1.4GHz	O
.	O
</s>
<s>
MMX	B-Architecture
,	O
3DNow	B-General_Concept
!	I-General_Concept
</s>
<s>
Overall	O
,	O
there	O
are	O
four	O
main	O
variants	O
of	O
the	O
Athlon	B-Architecture
XP	O
desktop	O
CPU	O
:	O
the	O
Palomino	O
,	O
the	O
Thoroughbred	O
,	O
the	O
Thorton	O
,	O
and	O
the	O
Barton	O
.	O
</s>
<s>
On	O
May	O
14	O
,	O
2001	O
,	O
AMD	O
released	O
the	O
Athlon	B-Architecture
XP	O
processor	O
.	O
</s>
<s>
It	O
debuted	O
as	O
the	O
Mobile	O
Athlon	B-Architecture
4	O
,	O
a	O
mobile	O
version	O
codenamed	O
Corvette	O
,	O
with	O
the	O
desktop	O
AthlonXP	O
released	O
in	O
the	O
fall	O
.	O
</s>
<s>
The	O
third-generation	O
Athlon	B-Architecture
,	O
code-named	O
Palomino	O
,	O
came	O
out	O
on	O
October9	O
,	O
2001	O
,	O
as	O
the	O
AthlonXP	O
,	O
with	O
the	O
suffix	O
signifying	O
extended	O
performance	O
and	O
unofficially	O
referencing	O
Windows	O
XP	O
.	O
</s>
<s>
Palomino	O
's	O
design	O
used	O
180nm	B-Algorithm
fabrication	O
process	O
size	O
.	O
</s>
<s>
Palomino	O
also	O
had	O
enhanced	O
K7	B-Architecture
's	O
TLB	B-Architecture
architecture	O
and	O
included	O
a	O
hardware	O
data	O
prefetch	B-General_Concept
mechanism	O
to	O
take	O
better	O
advantage	O
of	O
memory	O
bandwidth	O
.	O
</s>
<s>
Palomino	O
was	O
the	O
first	O
K7	B-Architecture
core	O
to	O
include	O
the	O
full	O
SSE	B-General_Concept
instruction	O
set	O
from	O
the	O
Intel	O
PentiumIII	O
,	O
as	O
well	O
as	O
AMD	O
's	O
3DNow	B-General_Concept
!	I-General_Concept
</s>
<s>
Palomino	O
was	O
also	O
the	O
first	O
socketed	O
Athlon	B-Architecture
officially	O
supporting	O
dual	O
processing	O
,	O
with	O
chips	O
certified	O
for	O
that	O
purpose	O
branded	O
as	O
the	O
Athlon	B-Architecture
MP	O
(	O
multi	O
processing	O
)	O
,	O
which	O
had	O
different	O
specifications	O
.	O
</s>
<s>
According	O
to	O
HardwareZone	O
,	O
it	O
was	O
possible	O
to	O
modify	O
the	O
Athlon	B-Architecture
XP	O
to	O
function	O
as	O
an	O
MP	O
.	O
</s>
<s>
The	O
fourth-generation	O
of	O
Athlon	B-Architecture
was	O
introduced	O
with	O
the	O
Thoroughbred	O
core	O
,	O
or	O
T-Bred	O
,	O
on	O
April17	O
,	O
2002	O
.	O
</s>
<s>
There	O
came	O
to	O
be	O
two	O
steppings	B-General_Concept
(	O
revisions	O
)	O
of	O
this	O
core	O
commonly	O
referred	O
to	O
as	O
Tbred-A	O
and	O
Tbred-B	O
.	O
</s>
<s>
A	O
revised	O
Thoroughbred	O
core	O
,	O
Thoroughbred-B	O
,	O
added	O
a	O
ninth	O
"	O
metal	O
layer	O
"	O
to	O
the	O
eight-layered	O
Thoroughbred-A	O
,	O
offering	O
improvement	O
in	O
headroom	O
over	O
the	O
A	O
and	O
making	O
it	O
popular	O
for	O
overclocking	B-Application
.	O
</s>
<s>
Fifth-generation	O
Athlon	B-Architecture
Barton-core	O
processors	O
were	O
released	O
in	O
early	O
2003	O
.	O
</s>
<s>
While	O
not	O
operating	O
at	O
higher	O
clock	O
rates	O
than	O
Thoroughbred-core	O
processors	O
,	O
they	O
featured	O
an	O
increased	O
L2	O
cache	O
,	O
and	O
later	O
models	O
had	O
an	O
increased	O
200MHz	O
(	O
400MT/s	O
)	O
front	B-Architecture
side	I-Architecture
bus	I-Architecture
.	O
</s>
<s>
By	O
this	O
point	O
with	O
the	O
Barton	O
,	O
the	O
four-year-old	O
Athlon	B-Architecture
EV6bus	O
architecture	O
had	O
scaled	O
to	O
its	O
limit	O
and	O
required	O
a	O
redesign	O
to	O
exceed	O
the	O
performance	O
of	O
newer	O
Intel	O
processors	O
.	O
</s>
<s>
By	O
2003	O
,	O
the	O
Pentium	B-General_Concept
4	O
had	O
become	O
more	O
than	O
competitive	O
with	O
AMD	O
's	O
processors	O
,	O
and	O
Barton	O
only	O
saw	O
a	O
small	O
performance	O
increase	O
over	O
the	O
Thoroughbred-B	O
it	O
derived	O
from	O
,	O
insufficient	O
to	O
outperform	O
the	O
Pentium4	O
.	O
</s>
<s>
The	O
K7-derived	O
Athlons	B-Architecture
such	O
as	O
Barton	O
were	O
replaced	O
in	O
September	O
2003	O
by	O
the	O
Athlon	B-Architecture
64	O
family	O
,	O
which	O
featured	O
an	O
on-chip	B-General_Concept
memory	I-General_Concept
controller	I-General_Concept
and	O
a	O
new	O
HyperTransport	B-Device
bus	O
.	O
</s>
<s>
Notably	O
,	O
the	O
2500+	O
Barton	O
with	O
11×	O
multiplier	O
was	O
effectively	O
identical	O
to	O
the	O
3200+	O
part	O
other	O
than	O
the	O
FSB	O
speed	O
it	O
was	O
binned	O
for	O
,	O
meaning	O
that	O
seamless	O
overclocking	B-Application
was	O
possible	O
more	O
often	O
than	O
not	O
.	O
</s>
<s>
The	O
Palomino	O
core	O
debuted	O
in	O
the	O
mobile	O
market	O
before	O
the	O
PC	O
market	O
,	O
where	O
it	O
was	O
branded	O
as	O
Mobile	O
Athlon	B-Architecture
4	O
with	O
the	O
codename	O
"	O
Corvette	O
"	O
.	O
</s>
<s>
It	O
distinctively	O
used	O
a	O
ceramic	B-Algorithm
interposer	O
much	O
like	O
the	O
Thunderbird	O
instead	O
of	O
the	O
organic	B-Algorithm
pin	I-Algorithm
grid	I-Algorithm
array	I-Algorithm
package	O
used	O
on	O
all	O
later	O
Palomino	O
processors	O
.	O
</s>
<s>
The	O
Mobile	O
Athlon4	O
processors	O
included	O
the	O
PowerNow	B-Device
!	I-Device
</s>
<s>
Duron	O
chips	O
also	O
included	O
PowerNow	B-Device
!	I-Device
</s>
<s>
In	O
2002	O
,	O
AMD	O
released	O
a	O
version	O
of	O
PowerNow	B-Device
!	I-Device
</s>
<s>
called	O
Cool'n'Quiet	B-Device
,	O
implemented	O
on	O
the	O
AthlonXP	O
but	O
only	O
adjusting	O
clock	O
speed	O
instead	O
of	O
voltage	O
.	O
</s>
<s>
In	O
2002	O
the	O
Athlon	B-Architecture
XP-M	O
(	O
Mobile	O
Athlon	B-Architecture
XP	O
)	O
replaced	O
the	O
Mobile	O
Athlon4	O
using	O
the	O
newer	O
Thoroughbred	O
core	O
,	O
with	O
Barton	O
cores	O
for	O
full-size	O
notebooks	O
.	O
</s>
<s>
The	O
Athlon	B-Architecture
XP-M	O
was	O
also	O
offered	O
in	O
a	O
compact	O
microPGA	O
socket	O
563	O
version	O
.	O
</s>
<s>
Mobile	O
XPs	O
were	O
not	O
multiplier-locked	O
,	O
making	O
them	O
popular	O
with	O
desktop	O
overclockers	B-Application
.	O
</s>
<s>
The	O
immediate	O
successor	O
to	O
the	O
Athlon	B-Architecture
XP	O
,	O
the	O
Athlon	B-Architecture
64	O
is	O
an	O
AMD64-architecture	O
microprocessor	B-Architecture
produced	O
by	O
AMD	O
,	O
released	O
on	O
September23	O
,	O
2003	O
.	O
</s>
<s>
The	O
Athlon	B-Architecture
64	O
X2	O
was	O
released	O
in	O
2005	O
as	O
the	O
first	O
native	O
dual-core	O
desktop	O
CPU	O
designed	O
by	O
AMD	O
using	O
an	O
Athlon64	O
.	O
</s>
<s>
The	O
Athlon	B-Architecture
X2	O
was	O
a	O
subsequent	O
family	O
of	O
microprocessors	B-Architecture
based	O
on	O
the	O
Athlon64X2	O
.	O
</s>
<s>
Athlon	B-Architecture
II	O
is	O
a	O
family	O
of	O
central	O
processing	O
units	O
.	O
</s>
<s>
The	O
Bristol	O
Ridge	O
Athlon	B-Architecture
X4	O
lineup	O
was	O
released	O
in	O
2017	O
.	O
</s>
<s>
It	O
had	O
a	O
dual-channel	O
DDR4-2400	O
memory	B-General_Concept
controller	I-General_Concept
with	O
clockspeeds	O
up	O
to	O
4.0GHz	O
.	O
</s>
<s>
The	O
Zen-based	O
Athlon	B-Architecture
with	O
Radeon	B-Device
graphics	I-Device
processors	O
was	O
launched	O
in	O
September	O
2018	O
with	O
the	O
Athlon200GE	O
.	O
</s>
<s>
Based	O
on	O
AMD	O
's	O
Raven	O
Ridge	O
core	O
previously	O
used	O
in	O
variants	O
of	O
the	O
Ryzen3	O
and	O
Ryzen	O
5	O
,	O
the	O
Athlon200GE	O
had	O
half	O
of	O
the	O
cores	O
but	O
left	O
SMT	B-Operating_System
enabled	O
.	O
</s>
<s>
On	O
November	O
19	O
,	O
2019	O
,	O
AMD	O
released	O
the	O
Athlon	B-Architecture
3000G	O
,	O
with	O
a	O
higher	O
3.5GHz	O
core	O
clock	O
and	O
1100MHz	O
graphics	O
clock	O
compared	O
to	O
the	O
Athlon200GE	O
,	O
also	O
with	O
two	O
cores	O
.	O
</s>
<s>
The	O
main	O
functional	O
difference	O
between	O
the	O
200GE	O
was	O
the	O
Athlon	B-Architecture
3000G	O
's	O
unlocked	O
multiplier	O
,	O
allowing	O
the	O
latter	O
to	O
be	O
overclocked	O
on	O
B450	O
and	O
X470	O
motherboards	B-Device
.	O
</s>
<s>
A	O
number	O
of	O
supercomputers	B-Architecture
have	O
been	O
built	O
using	O
Athlon	B-Architecture
chips	O
,	O
largely	O
at	O
universities	O
.	O
</s>
<s>
In	O
2000	O
,	O
several	O
American	O
students	O
claimed	O
to	O
have	O
built	O
the	O
world	O
's	O
least	O
expensive	O
supercomputer	B-Architecture
by	O
clustering	O
64	O
AMD	O
Athlon	B-Architecture
chips	O
together	O
,	O
also	O
marking	O
the	O
first	O
time	O
Athlons	B-Architecture
had	O
been	O
clustered	O
in	O
a	O
supercomputer	B-Architecture
.	O
</s>
<s>
The	O
PRESTO	O
III	O
,	O
a	O
Beowulf	B-Operating_System
cluster	I-Operating_System
of	O
78	O
AMD	O
Athlon	B-Architecture
processors	O
,	O
was	O
built	O
in	O
2001	O
by	O
the	O
Tokyo	O
Institute	O
of	O
Technology	O
.	O
</s>
<s>
That	O
year	O
it	O
ranked	O
439	O
on	O
the	O
TOP500	B-Operating_System
list	B-Operating_System
of	I-Operating_System
supercomputers	I-Operating_System
.	O
</s>
<s>
In	O
2002	O
,	O
a	O
"	O
128-Node	O
256-Processor	O
AMD	O
Athlon	B-Architecture
Supercomputer	B-Architecture
Cluster	O
"	O
was	O
installed	O
at	O
the	O
Ohio	B-Architecture
Supercomputer	I-Architecture
Center	I-Architecture
at	O
the	O
University	O
of	O
Toledo	O
.	O
</s>
<s>
Machine	O
:	O
NOW	O
Cluster	O
—	O
AMD	B-Architecture
Athlon	I-Architecture
.	O
</s>
