<s>
Asynchronous	B-Application
circuit	I-Application
(	O
clockless	B-Application
or	O
self-timed	O
circuit	O
)	O
is	O
a	O
sequential	O
digital	O
logic	O
circuit	O
that	O
does	O
not	O
use	O
a	O
global	O
clock	O
circuit	O
or	O
signal	O
generator	O
to	O
synchronize	O
its	O
components	O
.	O
</s>
<s>
Many	O
synchronous	B-Application
circuits	I-Application
were	O
developed	O
in	O
early	O
1950s	O
as	O
part	O
of	O
bigger	O
asynchronous	B-Application
systems	I-Application
(	O
e.g.	O
</s>
<s>
ORDVAC	B-Device
)	O
.	O
</s>
<s>
Asynchronous	B-Application
circuits	I-Application
and	O
theory	O
surrounding	O
is	O
a	O
part	O
of	O
several	O
steps	O
in	O
integrated	O
circuit	O
design	O
,	O
a	O
field	O
of	O
digital	O
electronics	O
engineering	O
.	O
</s>
<s>
Asynchronous	B-Application
circuits	I-Application
are	O
contrasted	O
with	O
synchronous	B-Application
circuits	I-Application
,	O
in	O
which	O
changes	O
to	O
the	O
signal	O
values	O
in	O
the	O
circuit	O
are	O
triggered	O
by	O
repetitive	O
pulses	O
called	O
a	O
clock	O
signal	O
.	O
</s>
<s>
Most	O
digital	O
devices	O
today	O
use	O
synchronous	B-Application
circuits	I-Application
.	O
</s>
<s>
However	O
asynchronous	B-Application
circuits	I-Application
have	O
a	O
potential	O
to	O
be	O
much	O
faster	O
,	O
have	O
a	O
lower	O
level	O
of	O
power	O
consumption	O
,	O
electromagnetic	O
interference	O
,	O
and	O
better	O
modularity	O
in	O
large	O
systems	O
.	O
</s>
<s>
Asynchronous	B-Application
circuits	I-Application
are	O
an	O
active	O
area	O
of	O
research	O
in	O
digital	O
logic	O
design	O
.	O
</s>
<s>
It	O
was	O
not	O
until	O
the	O
1990s	O
when	O
viability	O
of	O
the	O
asynchronous	B-Application
circuits	I-Application
was	O
shown	O
by	O
real-life	O
commercial	O
products	O
.	O
</s>
<s>
In	O
other	O
words	O
,	O
sequential	O
logic	O
is	O
combinational	O
logic	O
with	O
memory	B-General_Concept
.	O
</s>
<s>
Sequential	O
logic	O
can	O
be	O
divided	O
into	O
two	O
types	O
,	O
synchronous	B-Application
logic	I-Application
and	O
asynchronous	B-Application
logic	I-Application
.	O
</s>
<s>
In	O
synchronous	B-Application
logic	I-Application
circuits	I-Application
,	O
an	O
electronic	O
oscillator	O
generates	O
a	O
repetitive	O
series	O
of	O
equally	O
spaced	O
pulses	O
called	O
the	O
clock	O
signal	O
.	O
</s>
<s>
The	O
output	O
of	O
all	O
memory	B-General_Concept
elements	O
in	O
a	O
circuit	O
is	O
called	O
the	O
state	B-Application
of	O
the	O
circuit	O
.	O
</s>
<s>
The	O
state	B-Application
of	O
a	O
synchronous	B-Application
circuit	I-Application
changes	O
only	O
on	O
the	O
clock	O
pulse	O
.	O
</s>
<s>
Because	O
of	O
this	O
level	O
of	O
complexity	O
,	O
testing	O
and	O
debugging	O
takes	O
over	O
half	O
of	O
development	O
time	O
in	O
all	O
dimensions	O
for	O
synchronous	B-Application
circuits	I-Application
.	O
</s>
<s>
The	O
asynchronous	B-Application
circuits	I-Application
do	O
not	O
need	O
a	O
global	O
clock	O
,	O
and	O
the	O
state	B-Application
of	O
the	O
circuit	O
changes	O
as	O
soon	O
as	O
the	O
inputs	O
change	O
.	O
</s>
<s>
Since	O
asynchronous	B-Application
circuits	I-Application
do	O
not	O
have	O
to	O
wait	O
for	O
a	O
clock	O
pulse	O
to	O
begin	O
processing	O
inputs	O
,	O
they	O
can	O
operate	O
faster	O
.	O
</s>
<s>
However	O
,	O
asynchronous	B-Application
circuits	I-Application
are	O
more	O
difficult	O
to	O
design	O
and	O
subject	O
to	O
problems	O
not	O
found	O
in	O
synchronous	B-Application
circuits	I-Application
.	O
</s>
<s>
This	O
is	O
because	O
the	O
resulting	O
state	B-Application
of	O
an	O
asynchronous	B-Application
circuit	I-Application
can	O
be	O
sensitive	O
to	O
the	O
relative	O
arrival	O
times	O
of	O
inputs	O
at	O
gates	O
.	O
</s>
<s>
If	O
transitions	O
on	O
two	O
inputs	O
arrive	O
at	O
almost	O
the	O
same	O
time	O
,	O
the	O
circuit	O
can	O
go	O
into	O
the	O
wrong	O
state	B-Application
depending	O
on	O
slight	O
differences	O
in	O
the	O
propagation	O
delays	O
of	O
the	O
gates	O
.	O
</s>
<s>
This	O
is	O
called	O
a	O
race	B-Operating_System
condition	I-Operating_System
.	O
</s>
<s>
In	O
synchronous	B-Application
circuits	I-Application
this	O
problem	O
is	O
less	O
severe	O
because	O
race	B-Operating_System
conditions	I-Operating_System
can	O
only	O
occur	O
due	O
to	O
inputs	O
from	O
outside	O
the	O
synchronous	B-Application
system	I-Application
,	O
called	O
asynchronous	O
inputs	O
.	O
</s>
<s>
Although	O
some	O
fully	O
asynchronous	O
digital	O
systems	O
have	O
been	O
built	O
(	O
see	O
below	O
)	O
,	O
today	O
asynchronous	B-Application
circuits	I-Application
are	O
typically	O
used	O
in	O
a	O
few	O
critical	O
parts	O
of	O
otherwise	O
synchronous	B-Application
systems	I-Application
where	O
speed	O
is	O
at	O
a	O
premium	O
,	O
such	O
as	O
signal	O
processing	O
circuits	O
.	O
</s>
<s>
The	O
original	O
theory	O
of	O
asynchronous	B-Application
circuits	I-Application
was	O
created	O
by	O
David	O
E	O
.	O
Muller	O
in	O
mid-1950s	O
.	O
</s>
<s>
The	O
term	O
"	O
asynchronous	B-Application
logic	I-Application
"	O
is	O
used	O
to	O
describe	O
a	O
variety	O
of	O
design	O
styles	O
,	O
which	O
use	O
different	O
assumptions	O
about	O
circuit	O
properties	O
.	O
</s>
<s>
These	O
vary	O
from	O
the	O
bundled	O
delay	O
model	O
–	O
which	O
uses	O
"	O
conventional	O
"	O
data	O
processing	O
elements	O
with	O
completion	O
indicated	O
by	O
a	O
locally	O
generated	O
delay	O
model	O
–	O
to	O
delay-insensitive	B-General_Concept
design	O
–	O
where	O
arbitrary	O
delays	O
through	O
circuit	O
elements	O
can	O
be	O
accommodated	O
.	O
</s>
<s>
Asynchronous	B-Application
logic	I-Application
is	O
the	O
logic	O
required	O
for	O
the	O
design	O
of	O
asynchronous	O
digital	O
systems	O
.	O
</s>
<s>
These	O
function	O
without	O
a	O
clock	O
signal	O
and	O
so	O
individual	O
logic	O
elements	O
cannot	O
be	O
relied	O
upon	O
to	O
have	O
a	O
discrete	O
true/false	O
state	B-Application
at	O
any	O
given	O
time	O
.	O
</s>
<s>
This	O
architecture	O
is	O
important	O
because	O
it	O
is	O
quasi-delay-insensitive	O
.	O
</s>
<s>
Scott	O
Smith	O
and	O
Jia	O
Di	O
developed	O
an	O
ultra-low-power	O
variation	O
of	O
Fant	O
's	O
Null	B-Application
Convention	I-Application
Logic	I-Application
that	O
incorporates	O
multi-threshold	O
CMOS	B-Device
.	O
</s>
<s>
This	O
variation	O
is	O
termed	O
Multi-threshold	O
Null	B-Application
Convention	I-Application
Logic	I-Application
(	O
MTNCL	O
)	O
,	O
or	O
alternatively	O
Sleep	O
Convention	O
Logic	O
(	O
SCL	O
)	O
.	O
</s>
<s>
Petri	B-Operating_System
nets	I-Operating_System
are	O
an	O
attractive	O
and	O
powerful	O
model	O
for	O
reasoning	O
about	O
asynchronous	B-Application
circuits	I-Application
(	O
see	O
Subsequent	O
models	O
of	O
concurrency	O
)	O
.	O
</s>
<s>
A	O
particularly	O
useful	O
type	O
of	O
interpreted	O
Petri	B-Operating_System
nets	I-Operating_System
,	O
called	O
Signal	B-Application
Transition	I-Application
Graphs	I-Application
(	O
STGs	O
)	O
,	O
was	O
proposed	O
independently	O
in	O
1985	O
by	O
Leonid	O
Rosenblum	O
and	O
Alex	O
Yakovlev	O
and	O
Tam-Anh	O
Chu	O
.	O
</s>
<s>
Subsequent	O
to	O
Petri	B-Operating_System
nets	I-Operating_System
other	O
models	O
of	O
concurrency	O
have	O
been	O
developed	O
that	O
can	O
model	O
asynchronous	B-Application
circuits	I-Application
including	O
the	O
Actor	B-Application
model	I-Application
and	O
process	O
calculi	O
.	O
</s>
<s>
A	O
variety	O
of	O
advantages	O
have	O
been	O
demonstrated	O
by	O
asynchronous	B-Application
circuits	I-Application
.	O
</s>
<s>
Both	O
quasi-delay-insensitive	O
(	O
QDI	O
)	O
circuits	O
(	O
generally	O
agreed	O
to	O
be	O
the	O
most	O
"	O
pure	O
"	O
form	O
of	O
asynchronous	B-Application
logic	I-Application
that	O
retains	O
computational	O
universality	O
)	O
and	O
less	O
pure	O
forms	O
of	O
asynchronous	O
circuitry	O
which	O
use	O
timing	O
constraints	O
for	O
higher	O
performance	O
and	O
lower	O
area	O
and	O
power	O
present	O
several	O
advantages	O
.	O
</s>
<s>
as	O
it	O
is	O
in	O
synchronous	B-Application
circuits	I-Application
.	O
</s>
<s>
Examples	O
include	O
speculative	O
completion	O
which	O
has	O
been	O
applied	O
to	O
design	O
parallel	O
prefix	O
adders	O
faster	O
than	O
synchronous	O
ones	O
,	O
and	O
a	O
high-performance	O
double-precision	O
floating	O
point	O
adder	O
which	O
outperforms	O
leading	O
synchronous	B-Application
designs	I-Application
.	O
</s>
<s>
Though	O
given	O
different	O
delay	O
models	O
(	O
predictions	O
of	O
gate/wire	O
delay	O
times	O
)	O
this	O
depends	O
on	O
actual	O
approach	O
of	O
asynchronous	B-Application
circuit	I-Application
implementation	O
.	O
</s>
<s>
Freedom	O
from	O
the	O
ever-worsening	O
difficulties	O
of	O
distributing	O
a	O
high-fan-out	O
,	O
timing-sensitive	O
clock	O
signal	O
.	O
</s>
<s>
In	O
2005	O
Epson	O
has	O
reported	O
70%	O
lower	O
power	O
consumption	O
compared	O
to	O
synchronous	B-Application
design	I-Application
.	O
</s>
<s>
However	O
,	O
when	O
using	O
certain	O
encodings	O
,	O
asynchronous	B-Application
circuits	I-Application
may	O
require	O
more	O
area	O
,	O
adding	O
similar	O
power	O
overhead	O
if	O
the	O
underlying	O
process	O
has	O
poor	O
leakage	O
properties	O
(	O
for	O
example	O
,	O
deep	O
submicrometer	O
processes	O
used	O
prior	O
to	O
the	O
introduction	O
of	O
high-κ	B-Algorithm
dielectrics	I-Algorithm
)	O
.	O
</s>
<s>
Synchronous	B-Application
circuits	I-Application
tend	O
to	O
draw	O
a	O
large	O
amount	O
of	O
current	O
right	O
at	O
the	O
clock	O
edge	O
and	O
shortly	O
thereafter	O
.	O
</s>
<s>
In	O
an	O
asynchronous	B-Application
circuit	I-Application
,	O
the	O
switching	O
times	O
of	O
the	O
nodes	O
does	O
not	O
correlated	O
in	O
this	O
manner	O
,	O
so	O
the	O
current	O
draw	O
tends	O
to	O
be	O
more	O
uniform	O
and	O
less	O
bursty	O
.	O
</s>
<s>
Synchronous	B-Application
circuits	I-Application
create	O
a	O
great	O
deal	O
of	O
EMI	O
in	O
the	O
frequency	O
band	O
at	O
(	O
or	O
very	O
near	O
)	O
their	O
clock	O
frequency	O
and	O
its	O
harmonics	O
;	O
asynchronous	B-Application
circuits	I-Application
generate	O
EMI	O
patterns	O
which	O
are	O
much	O
more	O
evenly	O
spread	O
across	O
the	O
spectrum	O
.	O
</s>
<s>
Asynchronous	B-Application
circuits	I-Application
are	O
more	O
tolerant	O
to	O
process	O
variations	O
and	O
external	O
voltage	O
fluctuations	O
.	O
</s>
<s>
In	O
some	O
cases	O
an	O
asynchronous	B-Application
design	I-Application
may	O
require	O
up	O
to	O
double	O
the	O
resources	O
(	O
area	O
,	O
circuit	O
speed	O
,	O
power	O
consumption	O
)	O
of	O
a	O
synchronous	B-Application
design	I-Application
,	O
due	O
to	O
addition	O
of	O
completion	O
detection	O
and	O
design-for-test	O
circuits	O
.	O
</s>
<s>
Compared	O
to	O
a	O
synchronous	B-Application
design	I-Application
,	O
as	O
of	O
the	O
1990s	O
and	O
early	O
2000s	O
not	O
many	O
people	O
are	O
trained	O
or	O
experienced	O
in	O
the	O
design	O
of	O
asynchronous	B-Application
circuits	I-Application
.	O
</s>
<s>
Synchronous	B-Application
designs	I-Application
are	O
inherently	O
easier	O
to	O
test	O
and	O
debug	O
than	O
asynchronous	B-Application
designs	I-Application
.	O
</s>
<s>
However	O
,	O
this	O
position	O
is	O
disputed	O
by	O
Fant	O
,	O
who	O
claims	O
that	O
the	O
apparent	O
simplicity	O
of	O
synchronous	B-Application
logic	I-Application
is	O
an	O
artifact	O
of	O
the	O
mathematical	O
models	O
used	O
by	O
the	O
common	O
design	O
approaches	O
.	O
</s>
<s>
Clock	O
gating	O
in	O
more	O
conventional	O
synchronous	B-Application
designs	I-Application
is	O
an	O
approximation	O
of	O
the	O
asynchronous	O
ideal	O
,	O
and	O
in	O
some	O
cases	O
,	O
its	O
simplicity	O
may	O
outweigh	O
the	O
advantages	O
of	O
a	O
fully	O
asynchronous	B-Application
design	I-Application
.	O
</s>
<s>
Performance	O
(	O
speed	O
)	O
of	O
asynchronous	B-Application
circuits	I-Application
may	O
be	O
reduced	O
in	O
architectures	O
that	O
require	O
input-completeness	O
(	O
more	O
complex	O
data	O
path	O
)	O
.	O
</s>
<s>
Despite	O
involving	O
more	O
transitions	O
per	O
communication	O
,	O
circuits	O
implementing	O
four-phase	O
protocols	O
are	O
usually	O
faster	O
and	O
simpler	O
than	O
two-phase	O
protocols	O
because	O
the	O
signal	O
lines	O
return	O
to	O
their	O
original	O
state	B-Application
by	O
the	O
end	O
of	O
each	O
communication	O
.	O
</s>
<s>
In	O
two-phase	O
protocols	O
,	O
the	O
circuit	O
implementations	O
would	O
have	O
to	O
store	O
the	O
state	B-Application
of	O
the	O
signal	O
line	O
internally	O
.	O
</s>
<s>
Bundled-data	O
encoding	O
uses	O
one	O
wire	O
per	O
bit	O
of	O
data	O
with	O
a	O
request	O
and	O
an	O
acknowledge	O
signal	O
;	O
this	O
is	O
the	O
same	O
encoding	O
used	O
in	O
synchronous	B-Application
circuits	I-Application
without	O
the	O
restriction	O
that	O
transitions	O
occur	O
on	O
a	O
clock	O
edge	O
.	O
</s>
<s>
This	O
provides	O
the	O
advantage	O
that	O
the	O
data	O
communication	O
is	O
delay-insensitive	B-General_Concept
.	O
</s>
<s>
Dual-rail	O
encoding	O
with	O
a	O
four-phase	O
protocol	O
is	O
the	O
most	O
common	O
and	O
is	O
also	O
called	O
three-state	O
encoding	O
,	O
since	O
it	O
has	O
two	O
valid	O
states	O
(	O
10	O
and	O
01	O
,	O
after	O
a	O
transition	O
)	O
and	O
a	O
reset	O
state	B-Application
(	O
00	O
)	O
.	O
</s>
<s>
Another	O
common	O
encoding	O
,	O
which	O
leads	O
to	O
a	O
simpler	O
implementation	O
than	O
one-hot	O
,	O
two-phase	O
dual-rail	O
is	O
four-state	O
encoding	O
,	O
or	O
level-encoded	O
dual-rail	O
,	O
and	O
uses	O
a	O
data	O
bit	O
and	O
a	O
parity	O
bit	O
to	O
achieve	O
a	O
two-phase	O
protocol	O
.	O
</s>
<s>
Asynchronous	O
CPUs	O
are	O
one	O
of	O
several	O
ideas	O
for	O
radically	O
changing	O
CPU	B-General_Concept
design	I-General_Concept
.	O
</s>
<s>
Unlike	O
a	O
conventional	O
processor	O
,	O
a	O
clockless	B-Application
processor	I-Application
(	O
asynchronous	O
CPU	O
)	O
has	O
no	O
central	O
clock	O
to	O
coordinate	O
the	O
progress	O
of	O
data	O
through	O
the	O
pipeline	O
.	O
</s>
<s>
Asynchronous	B-Application
logic	I-Application
proponents	O
believe	O
these	O
capabilities	O
would	O
have	O
these	O
benefits	O
:	O
</s>
<s>
The	O
biggest	O
disadvantage	O
of	O
the	O
clockless	B-Application
CPU	O
is	O
that	O
most	O
CPU	B-General_Concept
design	I-General_Concept
tools	O
assume	O
a	O
clocked	O
CPU	O
(	O
i.e.	O
,	O
a	O
synchronous	B-Application
circuit	I-Application
)	O
.	O
</s>
<s>
Many	O
tools	O
"	O
enforce	O
synchronous	B-Application
design	I-Application
practices	O
"	O
.	O
</s>
<s>
Making	O
a	O
clockless	B-Application
CPU	O
(	O
designing	O
an	O
asynchronous	B-Application
circuit	I-Application
)	O
involves	O
modifying	O
the	O
design	O
tools	O
to	O
handle	O
clockless	B-Application
logic	I-Application
and	O
doing	O
extra	O
testing	O
to	O
ensure	O
the	O
design	O
avoids	O
metastable	O
problems	O
.	O
</s>
<s>
The	O
ORDVAC	B-Device
of	O
1951	O
was	O
a	O
successor	O
to	O
the	O
ENIAC	B-Device
and	O
the	O
first	O
asynchronous	O
computer	O
ever	O
built	O
.	O
</s>
<s>
The	O
ILLIAC	B-Device
II	I-Device
was	O
the	O
first	O
completely	O
asynchronous	O
,	O
speed	O
independent	O
processor	B-General_Concept
design	I-General_Concept
ever	O
built	O
;	O
it	O
was	O
the	O
most	O
powerful	O
computer	O
at	O
the	O
time	O
.	O
</s>
<s>
DEC	O
PDP-16	B-Device
Register	O
Transfer	O
Modules	O
(	O
ca	O
.	O
</s>
<s>
Since	O
the	O
mid-1980s	O
,	O
Caltech	O
has	O
designed	O
four	O
non-commercial	O
CPUs	O
in	O
attempt	O
to	O
evaluate	O
performance	O
and	O
energy	O
efficiency	O
of	O
the	O
asynchronous	B-Application
circuits	I-Application
.	O
</s>
<s>
In	O
1988	O
the	O
Caltech	O
Asynchronous	O
Microprocessor	O
(	O
CAM	O
)	O
was	O
the	O
first	O
asynchronous	O
,	O
quasi	O
delay-insensitive	B-General_Concept
(	O
QDI	O
)	O
microprocessor	O
made	O
by	O
Caltech	O
.	O
</s>
<s>
The	O
processor	O
had	O
16-bit	O
wide	O
RISC	B-Architecture
ISA	O
and	O
separate	B-Architecture
instruction	I-Architecture
and	I-Architecture
data	I-Architecture
memories	I-Architecture
.	O
</s>
<s>
It	O
was	O
manufactured	O
by	O
MOSIS	B-Architecture
and	O
funded	O
by	O
DARPA	O
.	O
</s>
<s>
In	O
1998	O
the	O
MiniMIPS	O
,	O
an	O
experimental	O
,	O
asynchronous	O
MIPS	B-Device
I-based	O
microcontroller	O
was	O
made	O
.	O
</s>
<s>
Even	O
though	O
its	O
SPICE-predicted	O
performance	O
was	O
around	O
280	O
MIPS	B-Device
at	O
3.3	O
V	O
the	O
implementation	O
suffered	O
from	O
several	O
mistakes	O
in	O
layout	O
(	O
human	O
mistake	O
)	O
and	O
the	O
results	O
turned	O
out	O
be	O
lower	O
by	O
about	O
40%	O
(	O
see	O
table	O
)	O
.	O
</s>
<s>
Made	O
in	O
2003	O
,	O
it	O
was	O
a	O
quasi	O
delay-insensitive	B-General_Concept
asynchronous	O
microcontroller	O
designed	O
for	O
energy	O
efficiency	O
.	O
</s>
<s>
The	O
microcontroller	O
's	O
implementation	O
followed	O
the	O
Harvard	B-Architecture
architecture	I-Architecture
.	O
</s>
<s>
In	O
2014	O
,	O
IBM	O
announced	O
a	O
SyNAPSE-developed	O
chip	O
that	O
runs	O
in	O
an	O
asynchronous	O
manner	O
,	O
with	O
one	O
of	O
the	O
highest	O
transistor	O
counts	O
of	O
any	O
chip	O
ever	O
produced	O
.	O
</s>
<s>
Several	O
versions	O
of	O
the	O
XAP	B-Device
processor	I-Device
experimented	O
with	O
different	O
asynchronous	B-Application
design	I-Application
styles	O
:	O
a	O
bundled	O
data	O
XAP	O
,	O
a	O
1-of-4	O
XAP	O
,	O
and	O
a	O
1-of-2	O
(	O
dual-rail	O
)	O
XAP	O
(	O
2003	O
?	O
)	O
</s>
<s>
ARM-compatible	O
processor	O
(	O
2003	O
?	O
)	O
</s>
