<s>
The	O
asynchronous	B-General_Concept
array	I-General_Concept
of	I-General_Concept
simple	I-General_Concept
processors	I-General_Concept
(	O
AsAP	O
)	O
architecture	O
comprises	O
a	O
2-D	O
array	O
of	O
reduced	O
complexity	O
programmable	O
processors	O
with	O
small	O
scratchpad	B-General_Concept
memories	I-General_Concept
interconnected	O
by	O
a	O
reconfigurable	O
mesh	B-Architecture
network	I-Architecture
.	O
</s>
<s>
The	O
multi-processor	O
architecture	O
efficiently	O
makes	O
use	O
of	O
task-level	O
parallelism	B-Operating_System
in	O
many	O
complex	O
DSP	B-Architecture
applications	O
,	O
and	O
also	O
efficiently	O
computes	O
many	O
large	O
tasks	O
using	O
fine-grained	O
parallelism	B-Operating_System
.	O
</s>
<s>
Chip	O
multi-processor	O
(	O
CMP	O
)	O
architecture	O
designed	O
to	O
achieve	O
high	O
performance	O
and	O
low	O
power	O
for	O
many	O
DSP	B-Architecture
applications	O
.	O
</s>
<s>
The	O
programmable	O
processors	O
can	O
individually	O
and	O
dynamically	O
change	O
their	O
supply	O
voltage	O
and	O
clock	B-General_Concept
frequency	I-General_Concept
.	O
</s>
<s>
This	O
operating	O
point	O
enables	O
1	O
trillion	O
MAC	B-Algorithm
or	O
arithmetic	B-General_Concept
logic	I-General_Concept
unit	I-General_Concept
(	O
ALU	O
)	O
ops/sec	O
with	O
a	O
power	O
dissipation	O
of	O
only	O
9.2	O
watts	O
.	O
</s>
<s>
Due	O
to	O
its	O
MIMD	B-Operating_System
architecture	O
and	O
fine-grain	O
clock	O
oscillator	O
stalling	O
,	O
this	O
energy	O
efficiency	O
per	O
operation	O
is	O
almost	O
perfectly	O
constant	O
across	O
widely	O
varying	O
workloads	O
,	O
which	O
is	O
not	O
the	O
case	O
for	O
many	O
architectures	O
.	O
</s>
<s>
The	O
coding	O
of	O
many	O
DSP	B-Architecture
and	O
general	O
tasks	O
for	O
AsAP	O
has	O
been	O
completed	O
.	O
</s>
<s>
filters	O
,	O
convolutional	B-Error_Name
coders	I-Error_Name
,	O
interleavers	O
,	O
sorting	O
,	O
square	O
root	O
,	O
CORDIC	B-Algorithm
sin/cos/arcsin/arccos	O
,	O
matrix	O
multiplication	O
,	O
pseudo	O
random	O
number	O
generators	O
,	O
fast	O
Fourier	O
transforms	O
(	O
FFTs	O
)	O
of	O
lengths	O
32	O
–	O
1024	O
,	O
a	O
complete	O
k	O
=	O
7	O
Viterbi	O
decoder	O
,	O
a	O
JPEG	O
encoder	O
,	O
a	O
complete	O
fully	O
compliant	O
baseband	O
processor	O
for	O
an	O
IEEE	O
802.11a/g	O
wireless	O
LAN	O
transmitter	O
and	O
receiver	O
,	O
and	O
a	O
complete	O
CAVLC	B-Algorithm
compression	O
block	O
for	O
an	O
H.264	B-Application
encoder	O
.	O
</s>
<s>
Power	O
,	O
throughput	O
,	O
and	O
area	O
results	O
are	O
typically	O
many	O
times	O
better	O
than	O
existing	O
programmable	O
DSP	B-Architecture
processors	O
.	O
</s>
<s>
A	O
recently	O
finished	O
C	B-Language
compiler	O
and	O
automatic	O
mapping	O
tool	O
further	O
simplify	O
programming	O
.	O
</s>
