<s>
In	O
computing	O
,	O
an	O
arithmetic	B-General_Concept
logic	I-General_Concept
unit	I-General_Concept
(	O
ALU	O
)	O
is	O
a	O
combinational	O
digital	O
circuit	O
that	O
performs	O
arithmetic	O
and	O
bitwise	O
operations	O
on	O
integer	O
binary	O
numbers	O
.	O
</s>
<s>
This	O
is	O
in	O
contrast	O
to	O
a	O
floating-point	B-General_Concept
unit	I-General_Concept
(	O
FPU	O
)	O
,	O
which	O
operates	O
on	O
floating	B-Algorithm
point	I-Algorithm
numbers	I-Algorithm
.	O
</s>
<s>
It	O
is	O
a	O
fundamental	O
building	O
block	O
of	O
many	O
types	O
of	O
computing	O
circuits	O
,	O
including	O
the	O
central	B-General_Concept
processing	I-General_Concept
unit	I-General_Concept
(	O
CPU	O
)	O
of	O
computers	O
,	O
FPUs	O
,	O
and	O
graphics	B-Architecture
processing	I-Architecture
units	I-Architecture
(	O
GPUs	B-Architecture
)	O
.	O
</s>
<s>
In	O
many	O
designs	O
,	O
the	O
ALU	O
also	O
has	O
status	O
inputs	O
or	O
outputs	O
,	O
or	O
both	O
,	O
which	O
convey	O
information	O
about	O
a	O
previous	O
operation	O
or	O
the	O
current	O
operation	O
,	O
respectively	O
,	O
between	O
the	O
ALU	O
and	O
external	O
status	B-General_Concept
registers	I-General_Concept
.	O
</s>
<s>
A	O
basic	O
ALU	O
has	O
three	O
parallel	O
data	B-General_Concept
buses	I-General_Concept
consisting	O
of	O
two	O
input	O
operands	O
(	O
A	O
and	O
B	O
)	O
and	O
a	O
result	O
output	O
(	O
Y	O
)	O
.	O
</s>
<s>
Each	O
data	B-General_Concept
bus	I-General_Concept
is	O
a	O
group	O
of	O
signals	O
that	O
conveys	O
one	O
binary	O
integer	O
number	O
.	O
</s>
<s>
The	O
opcode	B-Language
input	O
is	O
a	O
parallel	O
bus	O
that	O
conveys	O
to	O
the	O
ALU	O
an	O
operation	O
selection	O
code	O
,	O
which	O
is	O
an	O
enumerated	B-Language
value	I-Language
that	O
specifies	O
the	O
desired	O
arithmetic	O
or	O
logic	O
operation	O
to	O
be	O
performed	O
by	O
the	O
ALU	O
.	O
</s>
<s>
The	O
opcode	B-Language
size	O
(	O
its	O
bus	O
width	O
)	O
determines	O
the	O
maximum	O
number	O
of	O
distinct	O
operations	O
the	O
ALU	O
can	O
perform	O
;	O
for	O
example	O
,	O
a	O
four-bit	O
opcode	B-Language
can	O
specify	O
up	O
to	O
sixteen	O
different	O
ALU	O
operations	O
.	O
</s>
<s>
Generally	O
,	O
an	O
ALU	O
opcode	B-Language
is	O
not	O
the	O
same	O
as	O
a	O
machine	B-Language
language	I-Language
opcode	I-Language
,	O
though	O
in	O
some	O
cases	O
it	O
may	O
be	O
directly	O
encoded	O
as	O
a	O
bit	O
field	O
within	O
a	O
machine	B-Language
language	I-Language
opcode	I-Language
.	O
</s>
<s>
Carry-out	O
,	O
which	O
conveys	O
the	O
carry	B-Algorithm
resulting	O
from	O
an	O
addition	O
operation	O
,	O
the	O
borrow	O
resulting	O
from	O
a	O
subtraction	O
operation	O
,	O
or	O
the	O
overflow	B-Algorithm
bit	O
resulting	O
from	O
a	O
binary	O
shift	O
operation	O
.	O
</s>
<s>
Overflow	B-Algorithm
,	O
which	O
indicates	O
the	O
result	O
of	O
an	O
arithmetic	O
operation	O
has	O
exceeded	O
the	O
numeric	B-Algorithm
range	O
of	O
Y	O
.	O
</s>
<s>
Parity	B-General_Concept
,	O
which	O
indicates	O
whether	O
an	O
even	O
or	O
odd	O
number	O
of	O
bits	O
in	O
Y	O
are	O
logic	O
one	O
.	O
</s>
<s>
Upon	O
completion	O
of	O
each	O
ALU	O
operation	O
,	O
the	O
status	O
output	O
signals	O
are	O
usually	O
stored	O
in	O
external	O
registers	B-General_Concept
to	O
make	O
them	O
available	O
for	O
future	O
ALU	O
operations	O
(	O
e.g.	O
,	O
to	O
implement	O
multiple-precision	O
arithmetic	O
)	O
or	O
for	O
controlling	O
conditional	B-General_Concept
branching	I-General_Concept
.	O
</s>
<s>
The	O
collection	O
of	O
bit	O
registers	B-General_Concept
that	O
store	O
the	O
status	O
outputs	O
are	O
often	O
treated	O
as	O
a	O
single	O
,	O
multi-bit	O
register	O
,	O
which	O
is	O
referred	O
to	O
as	O
the	O
"	O
status	B-General_Concept
register	I-General_Concept
"	O
or	O
"	O
condition	B-General_Concept
code	I-General_Concept
register	I-General_Concept
"	O
.	O
</s>
<s>
Typically	O
,	O
this	O
is	O
a	O
single	O
"	O
carry-in	O
"	O
bit	O
that	O
is	O
the	O
stored	O
carry-out	O
from	O
a	O
previous	O
ALU	O
operation	O
.	O
</s>
<s>
For	O
example	O
,	O
a	O
CPU	O
begins	O
an	O
ALU	O
addition	O
operation	O
by	O
routing	O
operands	O
from	O
their	O
sources	O
(	O
which	O
are	O
usually	O
registers	B-General_Concept
)	O
to	O
the	O
ALU	O
's	O
operand	O
inputs	O
,	O
while	O
the	O
control	B-General_Concept
unit	I-General_Concept
simultaneously	O
applies	O
a	O
value	O
to	O
the	O
ALU	O
's	O
opcode	B-Language
input	O
,	O
configuring	O
it	O
to	O
perform	O
addition	O
.	O
</s>
<s>
Add	O
:	O
A	O
and	O
B	O
are	O
summed	O
and	O
the	O
sum	O
appears	O
at	O
Y	O
and	O
carry-out	O
.	O
</s>
<s>
Add	O
with	O
carry	B-Algorithm
:	O
A	O
,	O
B	O
and	O
carry-in	O
are	O
summed	O
and	O
the	O
sum	O
appears	O
at	O
Y	O
and	O
carry-out	O
.	O
</s>
<s>
Subtract	O
:	O
B	O
is	O
subtracted	O
from	O
A	O
(	O
or	O
vice	O
versa	O
)	O
and	O
the	O
difference	O
appears	O
at	O
Y	O
and	O
carry-out	O
.	O
</s>
<s>
For	O
this	O
function	O
,	O
carry-out	O
is	O
effectively	O
a	O
"	O
borrow	O
"	O
indicator	O
.	O
</s>
<s>
Subtract	O
with	O
borrow	O
:	O
B	O
is	O
subtracted	O
from	O
A	O
(	O
or	O
vice	O
versa	O
)	O
with	O
borrow	O
(	O
carry-in	O
)	O
and	O
the	O
difference	O
appears	O
at	O
Y	O
and	O
carry-out	O
(	O
borrow	O
out	O
)	O
.	O
</s>
<s>
Two	B-General_Concept
's	I-General_Concept
complement	I-General_Concept
(	O
negate	O
)	O
:	O
A	O
(	O
or	O
B	O
)	O
is	O
subtracted	O
from	O
zero	O
and	O
the	O
difference	O
appears	O
at	O
Y	O
.	O
</s>
<s>
This	O
operation	O
is	O
typically	O
used	O
to	O
determine	O
the	O
parity	B-General_Concept
of	O
the	O
operand	O
or	O
whether	O
it	O
is	O
zero	O
or	O
negative	O
,	O
or	O
to	O
load	O
the	O
operand	O
into	O
a	O
processor	B-General_Concept
register	I-General_Concept
.	O
</s>
<s>
ALU	O
shift	O
operations	O
cause	O
operand	O
A	O
(	O
or	O
B	O
)	O
to	O
shift	O
left	O
or	O
right	O
(	O
depending	O
on	O
the	O
opcode	B-Language
)	O
and	O
the	O
shifted	O
operand	O
appears	O
at	O
Y	O
.	O
</s>
<s>
In	O
all	O
single-bit	O
shift	O
operations	O
,	O
the	O
bit	O
shifted	O
out	O
of	O
the	O
operand	O
appears	O
on	O
carry-out	O
;	O
the	O
value	O
of	O
the	O
bit	O
shifted	O
into	O
the	O
operand	O
depends	O
on	O
the	O
type	O
of	O
shift	O
.	O
</s>
<s>
Arithmetic	O
shift	O
:	O
the	O
operand	O
is	O
treated	O
as	O
a	O
two	B-General_Concept
's	I-General_Concept
complement	I-General_Concept
integer	O
,	O
meaning	O
that	O
the	O
most	O
significant	O
bit	O
is	O
a	O
"	O
sign	O
"	O
bit	O
and	O
is	O
preserved	O
.	O
</s>
<s>
Rotate	O
through	O
carry	B-Algorithm
:	O
the	O
carry	B-Algorithm
bit	O
and	O
operand	O
are	O
collectively	O
treated	O
as	O
a	O
circular	O
buffer	O
of	O
bits	O
.	O
</s>
<s>
In	O
arithmetic	O
operations	O
(	O
e.g.	O
,	O
addition	O
,	O
subtraction	O
)	O
,	O
the	O
algorithm	O
starts	O
by	O
invoking	O
an	O
ALU	O
operation	O
on	O
the	O
operands	O
 '	O
LS	O
fragments	O
,	O
thereby	O
producing	O
both	O
a	O
LS	O
partial	O
and	O
a	O
carry	B-Algorithm
out	O
bit	O
.	O
</s>
<s>
The	O
algorithm	O
writes	O
the	O
partial	O
to	O
designated	O
storage	O
,	O
whereas	O
the	O
processor	O
's	O
state	O
machine	O
typically	O
stores	O
the	O
carry	B-Algorithm
out	O
bit	O
to	O
an	O
ALU	O
status	B-General_Concept
register	I-General_Concept
.	O
</s>
<s>
The	O
algorithm	O
then	O
advances	O
to	O
the	O
next	O
fragment	O
of	O
each	O
operand	O
's	O
collection	O
and	O
invokes	O
an	O
ALU	O
operation	O
on	O
these	O
fragments	O
along	O
with	O
the	O
stored	O
carry	B-Algorithm
bit	O
from	O
the	O
previous	O
ALU	O
operation	O
,	O
thus	O
producing	O
another	O
(	O
more	O
significant	O
)	O
partial	O
and	O
a	O
carry	B-Algorithm
out	O
bit	O
.	O
</s>
<s>
As	O
before	O
,	O
the	O
carry	B-Algorithm
bit	O
is	O
stored	O
to	O
the	O
status	B-General_Concept
register	I-General_Concept
and	O
the	O
partial	O
is	O
written	O
to	O
designated	O
storage	O
.	O
</s>
<s>
In	O
left-shift	O
operations	O
,	O
fragments	O
are	O
processed	O
LS	O
first	O
because	O
the	O
LS	O
bit	O
of	O
each	O
partial	O
—	O
which	O
is	O
conveyed	O
via	O
the	O
stored	O
carry	B-Algorithm
bit	O
—	O
must	O
be	O
obtained	O
from	O
the	O
MS	O
bit	O
of	O
the	O
previously	O
left-shifted	O
,	O
less-significant	O
operand	O
.	O
</s>
<s>
In	O
bitwise	O
logical	O
operations	O
(	O
e.g.	O
,	O
logical	O
AND	O
,	O
logical	O
OR	O
)	O
,	O
the	O
operand	O
fragments	O
may	O
be	O
processed	O
in	O
any	O
arbitrary	O
order	O
because	O
each	O
partial	O
depends	O
only	O
on	O
the	O
corresponding	O
operand	O
fragments	O
(	O
the	O
stored	O
carry	B-Algorithm
bit	O
from	O
the	O
previous	O
ALU	O
operation	O
is	O
ignored	O
)	O
.	O
</s>
<s>
Calculation	B-General_Concept
pipeline	I-General_Concept
:	O
a	O
group	O
of	O
simple	O
ALUs	O
that	O
calculates	O
a	O
square	O
root	O
in	O
stages	O
,	O
with	O
intermediate	O
results	O
passing	O
through	O
ALUs	O
arranged	O
like	O
a	O
factory	O
production	O
line	O
.	O
</s>
<s>
For	O
more	O
information	O
,	O
see	O
the	O
article	O
on	O
instruction	B-General_Concept
pipelining	I-General_Concept
.	O
</s>
<s>
Iterative	O
calculation	O
:	O
a	O
simple	O
ALU	O
that	O
calculates	O
the	O
square	O
root	O
through	O
several	O
steps	O
under	O
the	O
direction	O
of	O
a	O
control	B-General_Concept
unit	I-General_Concept
.	O
</s>
<s>
In	O
the	O
latter	O
case	O
,	O
an	O
ALU	O
is	O
typically	O
instantiated	O
by	O
synthesizing	O
it	O
from	O
a	O
description	O
written	O
in	O
VHDL	B-Language
,	O
Verilog	B-Language
or	O
some	O
other	O
hardware	O
description	O
language	O
.	O
</s>
<s>
For	O
example	O
,	O
the	O
following	O
VHDL	B-Language
code	O
describes	O
a	O
very	O
simple	O
8-bit	O
ALU	O
:	O
</s>
<s>
Mathematician	O
John	O
von	O
Neumann	O
proposed	O
the	O
ALU	O
concept	O
in	O
1945	O
in	O
a	O
report	O
on	O
the	O
foundations	O
for	O
a	O
new	O
computer	O
called	O
the	O
EDVAC	B-Device
.	O
</s>
<s>
Consequently	O
,	O
all	O
serial	B-Device
computers	I-Device
and	O
many	O
early	O
computers	O
,	O
such	O
as	O
the	O
PDP-8	B-Device
,	O
had	O
a	O
simple	O
ALU	O
that	O
operated	O
on	O
one	O
data	O
bit	O
at	O
a	O
time	O
,	O
although	O
they	O
often	O
presented	O
a	O
wider	O
word	O
size	O
to	O
programmers	O
.	O
</s>
<s>
Other	O
integrated-circuit	O
ALUs	O
soon	O
emerged	O
,	O
including	O
four-bit	O
ALUs	O
such	O
as	O
the	O
Am2901	B-General_Concept
and	O
74181	O
.	O
</s>
<s>
These	O
devices	O
were	O
typically	O
"	O
bit	B-General_Concept
slice	I-General_Concept
"	O
capable	O
,	O
meaning	O
they	O
had	O
"	O
carry	B-Algorithm
look	O
ahead	O
"	O
signals	O
that	O
facilitated	O
the	O
use	O
of	O
multiple	O
interconnected	O
ALU	O
chips	O
to	O
create	O
an	O
ALU	O
with	O
a	O
wider	O
word	O
size	O
.	O
</s>
<s>
These	O
devices	O
quickly	O
became	O
popular	O
and	O
were	O
widely	O
used	O
in	O
bit-slice	B-General_Concept
minicomputers	O
.	O
</s>
<s>
Examples	O
of	O
this	O
includes	O
the	O
popular	O
Zilog	B-General_Concept
Z80	I-General_Concept
,	O
which	O
performed	O
eight-bit	O
additions	O
with	O
a	O
four-bit	O
ALU	O
.	O
</s>
<s>
ALUs	O
can	O
be	O
realized	O
as	O
mechanical	B-Device
,	O
electro-mechanical	O
or	O
electronic	O
circuits	O
and	O
,	O
in	O
recent	O
years	O
,	O
research	O
into	O
biological	O
ALUs	O
has	O
been	O
carried	O
out	O
(	O
e.g.	O
,	O
actin-based	O
)	O
.	O
</s>
