<s>
An	O
application-specific	B-General_Concept
instruction	I-General_Concept
set	I-General_Concept
processor	I-General_Concept
(	O
ASIP	O
)	O
is	O
a	O
component	O
used	O
in	O
system	B-Architecture
on	I-Architecture
a	I-Architecture
chip	I-Architecture
design	O
.	O
</s>
<s>
The	O
instruction	B-General_Concept
set	I-General_Concept
architecture	I-General_Concept
of	O
an	O
ASIP	O
is	O
tailored	O
to	O
benefit	O
a	O
specific	O
application	O
.	O
</s>
<s>
This	O
specialization	O
of	O
the	O
core	O
provides	O
a	O
tradeoff	O
between	O
the	O
flexibility	O
of	O
a	O
general	O
purpose	O
central	B-General_Concept
processing	I-General_Concept
unit	I-General_Concept
(	O
CPU	O
)	O
and	O
the	O
performance	O
of	O
an	O
application-specific	O
integrated	O
circuit	O
(	O
ASIC	O
)	O
.	O
</s>
<s>
Some	O
ASIPs	O
have	O
a	O
configurable	O
instruction	B-General_Concept
set	I-General_Concept
.	O
</s>
<s>
The	O
configurable	O
logic	O
can	O
be	O
programmed	O
either	O
in	O
the	O
field	O
in	O
a	O
similar	O
fashion	O
to	O
a	O
field-programmable	B-Architecture
gate	I-Architecture
array	I-Architecture
(	O
FPGA	B-Architecture
)	O
or	O
during	O
the	O
chip	O
synthesis	O
.	O
</s>
<s>
It	O
is	O
very	O
difficult	O
to	O
reuse	O
the	O
hardware	O
datapath	O
with	O
handwritten	O
finite-state	B-Architecture
machines	I-Architecture
(	O
FSM	O
)	O
.	O
</s>
<s>
RISC-V	B-Device
Instruction	I-Device
Set	I-Device
Architecture	I-Device
(	O
ISA	O
)	O
provides	O
minimum	O
base	O
instruction	B-General_Concept
sets	I-General_Concept
that	O
can	O
be	O
extended	O
with	O
additional	O
application-specific	O
instructions	O
.	O
</s>
<s>
The	O
base	O
instruction	B-General_Concept
sets	I-General_Concept
provide	O
simplified	O
control	O
flow	O
,	O
memory	O
and	O
arithmetic	O
operations	O
on	O
registers	O
.	O
</s>
