<s>
The	O
Apple	B-Device
M2	I-Device
is	O
a	O
series	O
of	O
ARM-based	O
system	B-Architecture
on	I-Architecture
a	I-Architecture
chip	I-Architecture
(	O
SoC	O
)	O
designed	B-Device
by	I-Device
Apple	I-Device
Inc	I-Device
.	I-Device
as	O
a	O
central	B-General_Concept
processing	I-General_Concept
unit	I-General_Concept
(	O
CPU	O
)	O
and	O
graphics	B-Architecture
processing	I-Architecture
unit	I-Architecture
(	O
GPU	B-Architecture
)	O
for	O
its	O
Mac	B-Device
desktops	B-Device
and	O
notebooks	B-Device
,	O
and	O
the	O
iPad	B-Device
Pro	I-Device
tablet	B-Device
.	O
</s>
<s>
An	O
SoC	O
is	O
a	O
single	O
chip	O
that	O
integrates	O
multiple	O
components	O
of	O
a	O
computer	O
or	O
electronic	O
device	O
,	O
such	O
as	O
the	O
CPU	O
,	O
GPU	B-Architecture
,	O
memory	O
,	O
and	O
input/output	O
interfaces	O
,	O
in	O
a	O
single	O
package	B-Algorithm
.	O
</s>
<s>
It	O
is	O
the	O
second	O
generation	O
of	O
ARM	B-Architecture
architecture	I-Architecture
intended	O
for	O
Apple	O
's	O
Mac	B-Device
computers	I-Device
after	O
switching	B-Device
from	I-Device
Intel	I-Device
Core	I-Device
to	I-Device
Apple	I-Device
silicon	I-Device
,	O
succeeding	O
the	O
M1	B-Device
.	O
</s>
<s>
Apple	O
announced	O
the	O
M2	O
on	O
June	O
6	O
,	O
2022	O
,	O
at	O
WWDC	O
,	O
along	O
with	O
models	O
of	O
the	O
MacBook	B-Device
Air	O
and	O
the	O
13-inch	O
MacBook	B-Device
Pro	I-Device
using	O
the	O
M2	O
.	O
</s>
<s>
The	O
M2	O
is	O
made	O
with	O
TSMC	O
's	O
"	O
Enhanced	O
5-nanometer	O
technology	O
"	O
N5P	O
process	O
and	O
contains	O
20	O
billion	O
transistors	O
,	O
a	O
25%	O
increase	O
from	O
the	O
M1	B-Device
.	O
</s>
<s>
Apple	O
claims	O
CPU	O
improvements	O
up	O
to	O
18%	O
and	O
GPU	B-Architecture
improvements	O
up	O
to	O
35%	O
compared	O
to	O
the	O
M1	B-Device
.	O
</s>
<s>
The	O
M2	O
Max	O
is	O
a	O
higher-powered	O
version	O
of	O
the	O
M2	O
Pro	O
,	O
with	O
more	O
GPU	B-Architecture
cores	B-Architecture
and	O
memory	B-General_Concept
bandwidth	I-General_Concept
,	O
and	O
a	O
larger	O
die	O
size	O
.	O
</s>
<s>
The	O
M2	O
has	O
four	O
high-performance	O
"	O
Avalanche	O
"	O
and	O
four	O
energy-efficient	O
"	O
Blizzard	O
"	O
cores	B-Architecture
,	O
first	O
seen	O
in	O
the	O
A15	B-Device
Bionic	I-Device
,	O
providing	O
a	O
hybrid	O
configuration	O
similar	O
to	O
ARM	B-Architecture
DynamIQ	O
,	O
as	O
well	O
as	O
Intel	O
's	O
Alder	B-Device
Lake	I-Device
and	O
Raptor	B-Device
Lake	I-Device
processors	O
.	O
</s>
<s>
The	O
high-performance	O
cores	B-Architecture
have	O
192KB	O
of	O
L1	O
instruction	B-General_Concept
cache	I-General_Concept
and	O
128KB	O
of	O
L1	O
data	B-General_Concept
cache	I-General_Concept
and	O
share	O
a	O
16MB	O
L2	O
cache	O
;	O
the	O
energy-efficient	O
cores	B-Architecture
have	O
a	O
128KB	O
L1	O
instruction	B-General_Concept
cache	I-General_Concept
,	O
64KB	O
L1	O
data	B-General_Concept
cache	I-General_Concept
,	O
and	O
a	O
shared	O
4MB	O
L2	O
cache	O
.	O
</s>
<s>
It	O
also	O
has	O
an	O
8MB	O
system	O
level	O
cache	O
shared	O
by	O
the	O
GPU	B-Architecture
.	O
</s>
<s>
The	O
M2	O
Pro	O
has	O
10	O
or	O
12	O
CPU	B-Architecture
cores	I-Architecture
,	O
and	O
the	O
M2	O
Max	O
has	O
12	O
.	O
</s>
<s>
The	O
M2	O
integrates	O
an	O
Apple	O
designed	O
ten-core	O
(	O
or	O
eight-core	O
)	O
graphics	B-Architecture
processing	I-Architecture
unit	I-Architecture
(	O
GPU	B-Architecture
)	O
.	O
</s>
<s>
Each	O
GPU	B-Architecture
core	O
is	O
split	O
into	O
32	O
execution	B-General_Concept
units	I-General_Concept
,	O
which	O
each	O
contain	O
eight	O
arithmetic	B-General_Concept
logic	I-General_Concept
units	I-General_Concept
(	O
ALUs	O
)	O
.	O
</s>
<s>
In	O
total	O
,	O
the	O
M2	O
GPU	B-Architecture
contains	O
up	O
to	O
320	O
execution	B-General_Concept
units	I-General_Concept
or	O
2,560	O
ALUs	O
,	O
which	O
have	O
a	O
maximum	O
floating	O
point	O
(	O
FP32	O
)	O
performance	O
of	O
3.6	O
TFLOPs	O
.	O
</s>
<s>
The	O
M2	O
Pro	O
has	O
16	O
or	O
19	O
GPU	B-Architecture
cores	B-Architecture
,	O
and	O
the	O
M2	O
Max	O
has	O
30	O
or	O
38	O
.	O
</s>
<s>
The	O
SoC	O
and	O
RAM	O
chips	O
are	O
mounted	O
together	O
in	O
a	O
system-in-a-package	B-Algorithm
design	O
.	O
</s>
<s>
It	O
has	O
a	O
128-bit	O
memory	O
bus	O
with	O
bandwidth	O
,	O
a	O
little	O
bit	O
more	O
than	O
the	O
M1	B-Device
(	O
)	O
,	O
and	O
the	O
M2	O
Pro	O
and	O
M2	O
Max	O
continue	O
the	O
performance	O
from	O
the	O
last	O
generation	O
,	O
with	O
approximately	O
and	O
respectively	O
.	O
</s>
<s>
The	O
M2	O
contains	O
dedicated	O
neural	B-General_Concept
network	I-General_Concept
hardware	I-General_Concept
in	O
a	O
16-core	O
Neural	O
Engine	O
capable	O
of	O
executing	O
15.8	O
trillion	O
operations	O
per	O
second	O
.	O
</s>
<s>
Other	O
components	O
include	O
an	O
image	B-General_Concept
signal	I-General_Concept
processor	I-General_Concept
,	O
a	O
PCIe	O
storage	O
controller	O
,	O
a	O
Secure	O
Enclave	O
,	O
and	O
a	O
USB4	O
controller	O
that	O
includes	O
Thunderbolt	O
3	O
(	O
Thunderbolt	O
4	O
on	O
Mac	B-Device
mini	I-Device
)	O
support	O
.	O
</s>
<s>
Supported	O
codecs	B-General_Concept
on	O
the	O
M2	O
include	O
8K	O
H.264	B-Application
,	O
8K	O
H.265	B-Algorithm
(	O
8/10bit	O
,	O
up	O
to	O
4:4:4	O
)	O
,	O
8K	O
Apple	B-Algorithm
ProRes	I-Algorithm
,	O
VP9	B-Algorithm
,	O
and	O
JPEG	O
.	O
</s>
