<s>
Apollo	B-Device
VP3	I-Device
(	O
alias	O
ETEQ	B-Device
6628	I-Device
)	O
is	O
a	O
x86	B-Operating_System
based	I-Operating_System
Socket	B-General_Concept
7	I-General_Concept
chipset	B-Device
which	O
was	O
manufactured	O
by	O
VIA	O
Technologies	O
and	O
was	O
launched	O
in	O
1997	O
.	O
</s>
<s>
On	O
its	O
time	O
Apollo	B-Device
VP3	I-Device
was	O
a	O
high	O
performance	O
,	O
cost	O
effective	O
,	O
and	O
energy	O
efficient	O
chipset	B-Device
.	O
</s>
<s>
It	O
offered	O
AGP	B-Architecture
support	O
for	O
Socket	B-General_Concept
7	I-General_Concept
processors	O
which	O
was	O
not	O
supported	O
at	O
that	O
moment	O
by	O
Intel	O
,	O
SiS	O
and	O
ALi	O
chipsets	B-Device
.	O
</s>
<s>
In	O
November	O
1997	O
FIC	O
released	O
motherboard	B-Device
PA-2012	O
,	O
which	O
uses	O
Apollo	B-Device
VP3	I-Device
and	O
has	O
AGP	B-Architecture
bus	B-General_Concept
.	O
</s>
<s>
This	O
was	O
the	O
first	O
Socket	B-General_Concept
7	I-General_Concept
motherboard	B-Device
supporting	O
AGP	B-Architecture
.	O
</s>
<s>
Apollo	B-Device
VP3	I-Device
supports	O
32	O
bits	O
Socket	B-General_Concept
7	I-General_Concept
CPU-s	O
,	O
like	O
Pentium	B-General_Concept
,	O
Pentium	B-General_Concept
MMX	O
,	O
AMD	O
K5	O
,	O
AMD	B-Architecture
K6	I-Architecture
,	O
Cyrix	B-General_Concept
6x86	I-General_Concept
,	O
WinChip	B-Device
C2	O
and	O
C6	O
CPU-s	O
.	O
</s>
<s>
It	O
uses	O
VT82C597	O
(	O
or	O
VT82C597AT	O
for	O
Baby	O
AT	O
and	O
ATX	O
motherboards	B-Device
)	O
northbridge	B-Device
controller	O
chip	O
and	O
AC97	O
compliant	O
VT82C586B	O
southbridge	B-Device
chip	O
with	O
ACPI	B-Device
power	O
management	O
system	O
.	O
</s>
<s>
VP3	O
has	O
64	O
bits	O
memory	O
bus	B-General_Concept
;	O
32	O
bits	O
33	O
MHz	O
PCI	B-Protocol
;	O
32	O
bits	O
66MHz	O
AGP	B-Architecture
2X	O
with	O
sideband	B-Architecture
addressing	I-Architecture
,	O
133MHz	O
signalling	O
and	O
up	O
to	O
533	O
MB/s	O
transfer	O
capability	O
interfaces	O
.	O
</s>
<s>
It	O
uses	O
an	O
integrated	O
10-bits	O
TAG	B-Data_Structure
comparator	O
and	O
supports	O
up	O
to	O
2	O
MB	O
pipelined	O
burst	O
synchronous	O
SRAM	B-Architecture
(	O
cache	B-General_Concept
memory	I-General_Concept
)	O
and	O
up	O
to	O
1	O
GB	O
ECC	B-General_Concept
cachable	O
RAM	B-Architecture
memory	I-Architecture
.	O
</s>
<s>
Memory	B-General_Concept
controller	I-General_Concept
supports	O
up	O
to	O
8	O
memory	B-General_Concept
pages	I-General_Concept
(	O
banks	O
)	O
interleaving	B-General_Concept
mode	O
,	O
flexible	O
row	O
and	O
column	O
addresses	O
,	O
concurrent	O
DRAM	O
writeback	O
,	O
read	O
around	O
write	O
capability	O
,	O
burst	O
read	O
and	O
write	O
operations	O
,	O
etc	O
.	O
</s>
<s>
Officially	O
,	O
the	O
supported	O
speeds	O
of	O
the	O
memory	O
bus	B-General_Concept
are	O
50	O
,	O
60	O
and	O
66MHz	O
,	O
but	O
the	O
numerous	O
implemented	O
motherboards	B-Device
with	O
VP3	O
have	O
also	O
75	O
and	O
even	O
83MHz	O
bus	B-General_Concept
speed	O
capability	O
.	O
</s>
<s>
VT82C597	O
Northbridge	B-Device
supports	O
up	O
to	O
six	O
memory	B-General_Concept
banks	I-General_Concept
of	O
DRAM-s	O
or	O
DIMM-s	O
up	O
to	O
1GB	O
in	O
total	O
size	O
.	O
</s>
<s>
Memory	B-General_Concept
controller	I-General_Concept
supports	O
standard	O
fast	O
page	O
mode	O
(	O
FPM	O
)	O
DRAM	O
,	O
EDO-DRAM	O
,	O
Synchronous	O
DRAM	O
(	O
SDRAM	O
)	O
,	O
and	O
also	O
SDRAM-II	O
with	O
Double	O
Data	O
Rate	O
(	O
DDR	O
)	O
in	O
a	O
flexible	O
,	O
mixed	O
configuration	O
.	O
</s>
<s>
The	O
six	O
memory	B-General_Concept
banks	I-General_Concept
of	O
DRAM	O
can	O
be	O
used	O
in	O
arbitrary	O
mixture	O
of	O
1MB	O
/	O
2MB	O
/	O
4MB	O
/	O
8MB	O
/	O
16MBxN	O
DRAM	O
or	O
DIMM	B-General_Concept
modules	O
.	O
</s>
<s>
Memory	B-General_Concept
controller	I-General_Concept
has	O
3	O
,	O
3	O
V	O
(	O
5	O
V	O
tolerant	O
)	O
interface	O
.	O
</s>
<s>
VT82C586B	O
includes	O
UDMA-33	O
EIDE	O
,	O
USB	B-Protocol
,	O
Keyboard/PS2	O
-Mouse	O
interfaces	O
and	O
on	O
chip	O
RTC	O
plus	O
256	O
KB	O
CMOS	B-Device
.	O
</s>
<s>
Anandtech	O
described	O
Apollo	B-Device
VP3	I-Device
being	O
a	O
combination	O
of	O
the	O
VIA	O
Apollo	O
VP2	O
and	O
the	O
Intel	O
440LX	O
chipsets	B-Device
.	O
</s>
<s>
Apollo	B-Device
VP3	I-Device
was	O
quite	O
shortly	O
replaced	O
with	O
VIA	O
Apollo	O
MVP3	O
chipset	B-Device
,	O
which	O
offers	O
faster	O
,	O
100MHz	O
memory	O
bus	B-General_Concept
capability	O
and	O
asynchronous	O
memory	O
bus	B-General_Concept
,	O
but	O
supports	O
somewhat	O
less	O
amount	O
of	O
the	O
cachable	O
memory	O
area	O
and	O
system	O
DRAM	O
(	O
only	O
four	O
memory	B-General_Concept
banks	I-General_Concept
)	O
.	O
</s>
<s>
Lack	O
of	O
the	O
100MHz	B-General_Concept
bus	I-General_Concept
support	O
,	O
which	O
was	O
needed	O
for	O
a	O
newer	O
AMD	O
,	O
Cyrix	O
,	O
etc.	O
,	O
Super	O
Socket	B-General_Concept
7	I-General_Concept
processors	O
pushed	O
VIA	O
to	O
drop	O
VP3	O
from	O
production	O
.	O
</s>
<s>
Majority	O
of	O
motherboards	B-Device
on	O
the	O
basis	O
of	O
Apollo	B-Device
VP3	I-Device
chipset	B-Device
were	O
implemented	O
with	O
512	O
KB	O
L2	O
cache	B-General_Concept
memory	I-General_Concept
,	O
with	O
single	O
32KB	O
TAG-ram	O
chip	O
,	O
and	O
2	O
(	O
rarely	O
3	O
)	O
168-pin	O
DIMM	B-General_Concept
slots	O
plus	O
2	O
(	O
rarely	O
4	O
)	O
72-pin	O
SIMM	O
slots	O
,	O
with	O
AGP	B-Architecture
slot	I-Architecture
,	O
2-4	O
PCI	B-Protocol
slots	I-Protocol
,	O
2-3	O
ISA	B-General_Concept
slots	O
.	O
</s>
<s>
Some	O
extremes	O
are	O
FIC	O
PA-2012	O
and	O
Shuttle	O
HOT-595	O
which	O
have	O
1024	O
KB	O
(	O
some	O
have	O
512	O
KB	O
)	O
L2	O
cache	B-General_Concept
memory	I-General_Concept
and	O
have	O
three	O
168-pin	O
DIMM	B-General_Concept
slots	O
(	O
1	O
AGP	B-Architecture
,	O
4	O
PCI	B-Protocol
,	O
2	O
ISA	B-General_Concept
)	O
.	O
</s>
<s>
Tyan	O
Trinity	O
ATX	O
S1592S	O
has	O
three	O
168-pin	O
DIMM	B-General_Concept
slots	O
plus	O
four	O
72-pin	O
SO-DIMM	O
slots	O
(	O
1	O
AGP	B-Architecture
,	O
4	O
PCI	B-Protocol
,	O
3	O
ISA	B-General_Concept
)	O
.	O
</s>
<s>
Apollo	B-Device
VP3	I-Device
chipset	B-Device
was	O
sold	O
by	O
Soyo	O
also	O
under	O
name	O
ETEQ	B-Device
6628	I-Device
chipset	I-Device
.	O
</s>
