<s>
Released	O
as	O
the	O
expansion	O
bus	O
of	O
the	O
Commodore	O
Amiga	B-Device
3000	I-Device
in	O
1990	O
,	O
the	O
Zorro	B-Device
III	I-Device
computer	B-General_Concept
bus	I-General_Concept
was	O
used	O
to	O
attach	O
peripheral	B-Device
devices	I-Device
to	O
an	O
Amiga	O
motherboard	B-Device
.	O
</s>
<s>
Designed	O
by	O
Commodore	O
International	O
lead	O
engineer	O
Dave	O
Haynie	O
,	O
the	O
32-bit	O
Zorro	B-Device
III	I-Device
replaced	O
the	O
16-bit	B-Device
Zorro	B-Device
II	I-Device
bus	O
used	O
in	O
the	O
Amiga	B-Device
2000	I-Device
.	O
</s>
<s>
As	O
with	O
the	O
Zorro	B-Device
II	I-Device
bus	O
,	O
Zorro	B-Device
III	I-Device
allowed	O
for	O
true	O
Plug	O
and	O
Play	O
autodetection	O
(	O
similar	O
to	O
,	O
and	O
prior	O
to	O
,	O
the	O
PC	O
's	O
PCI	B-Protocol
bus	I-Protocol
)	O
wherein	O
devices	O
were	O
dynamically	O
allocated	O
the	O
resources	O
they	O
needed	O
on	O
boot	O
.	O
</s>
<s>
Zorro	B-Device
III	I-Device
continued	O
Zorro	B-Device
II	I-Device
's	O
direct	O
memory-mapped	O
address	O
design	O
(	O
unlike	O
80x86	O
processors	O
,	O
the	O
MC68K	O
family	O
used	O
in	O
the	O
Amiga	O
did	O
not	O
have	O
a	O
separate	O
I/O	O
address	O
mechanism	O
)	O
.	O
</s>
<s>
Just	O
as	O
with	O
Zorro	B-Device
II	I-Device
on	O
24-bit	O
systems	O
,	O
Zorro	B-Device
III	I-Device
reserved	O
a	O
large	O
chunk	O
of	O
32-bit	O
real	O
memory	O
address	O
space	O
for	O
large	O
memory	O
mapped	O
cards	O
,	O
a	O
smaller	O
chunk	O
with	O
smaller	O
allocation	O
granularity	O
for	O
"	O
I/O	O
"	O
type	O
board	O
.	O
</s>
<s>
Zorro	B-Device
III	I-Device
was	O
never	O
supported	O
on	O
24-bit	O
address	O
or	O
16-bit	B-Device
data	O
devices	O
—	O
it	O
required	O
a	O
full	O
32-bit	O
CPU	O
.	O
</s>
<s>
The	O
CPU	O
could	O
directly	O
address	O
any	O
Zorro	B-Device
III	I-Device
device	O
as	O
memory	O
,	O
so	O
Zorro	O
memory	O
expansions	O
could	O
be	O
made	O
(	O
and	O
were	O
made	O
)	O
as	O
well	O
as	O
it	O
being	O
possible	O
to	O
use	O
video	O
memory	O
on	O
a	O
video	O
card	O
to	O
be	O
as	O
system	O
RAM	B-Architecture
.	O
</s>
<s>
As	O
an	O
asynchronous	B-General_Concept
bus	I-General_Concept
,	O
Zorro	B-Device
III	I-Device
specified	O
bus	O
cycles	O
of	O
set	O
lengths	O
during	O
which	O
a	O
transaction	O
conforming	O
to	O
the	O
specifications	O
of	O
the	O
bus	O
could	O
be	O
carried	O
out	O
.	O
</s>
<s>
The	O
initial	O
implementation	O
of	O
Zorro	B-Device
III	I-Device
was	O
in	O
Commodore	O
's	O
"	O
Fat	O
"	O
Buster	O
(	O
BUS	O
conTrollER	O
)	O
gate	O
array	O
,	O
assisted	O
by	O
a	O
very	O
high	O
speed	O
PAL	O
and	O
numerous	O
TTL	O
buffer	O
chips	O
for	O
bus	O
buffering	O
,	O
isolation	O
,	O
and	O
multiplexing	O
.	O
</s>
<s>
The	O
Buster	O
chip	O
provided	O
bus	O
arbitration	O
,	O
translation	O
between	O
the	O
MC68030	O
bus	O
protocols	O
and	O
either	O
Zorro	B-Device
II	I-Device
or	O
Zorro	B-Device
III	I-Device
bus	O
cycles	O
(	O
geographically	O
mapped	O
based	O
on	O
the	O
Zorro	O
bus	O
address	O
)	O
,	O
and	O
a	O
vectored	O
interrupt	O
mechanism	O
,	O
generally	O
not	O
used	O
.	O
</s>
<s>
Zorro	B-Device
II	I-Device
bus	O
masters	O
were	O
legal	O
bus	O
hogs	O
,	O
but	O
Zorro	B-Device
III	I-Device
devices	O
were	O
fairly	O
arbitrated	O
and	O
had	O
controller-limited	O
bus	O
tenure	O
.	O
</s>
<s>
Despite	O
being	O
a	O
32-bit	O
bus	O
,	O
Zorro	B-Device
III	I-Device
used	O
the	O
same	O
100	O
way	O
slot	O
and	O
edge	O
connector	O
as	O
Zorro	B-Device
II	I-Device
.	O
</s>
<s>
However	O
,	O
the	O
bus	O
was	O
not	O
fully	O
multiplexed	O
;	O
the	O
lower	O
8-bits	O
of	O
address	O
were	O
available	O
during	O
data	O
cycles	O
,	O
which	O
allowed	O
Zorro	B-Device
III	I-Device
to	O
support	O
a	O
fast	O
burst	O
cycle	O
in	O
page-mode	O
.	O
</s>
<s>
Properly	O
designed	O
Zorro	B-Device
II	I-Device
expansion	O
cards	O
could	O
coexist	O
with	O
Zorro	B-Device
III	I-Device
cards	O
;	O
it	O
was	O
not	O
a	O
requirement	O
of	O
a	O
Zorro	B-Device
III	I-Device
bus	O
master	O
to	O
support	O
DMA	O
access	O
to	O
Zorro	B-Device
II	I-Device
bus	O
targets	O
.	O
</s>
<s>
Cards	O
could	O
detect	O
a	O
Zorro	B-Device
III	I-Device
vs.	O
Zorro	B-Device
II	I-Device
backplane	O
,	O
allowing	O
certain	O
Zorro	B-Device
III	I-Device
cards	O
to	O
function	O
when	O
connected	O
to	O
the	O
older	O
Zorro	B-Device
II	I-Device
bus	O
,	O
though	O
at	O
Zorro	B-Device
II	I-Device
's	O
reduced	O
data	O
rates	O
.	O
</s>
<s>
The	O
Zorro	B-Device
III	I-Device
bus	O
has	O
a	O
theoretical	O
bandwidth	O
of	O
150MByte/s	O
,	O
based	O
on	O
an	O
ideal	O
Zorro	B-Device
III	I-Device
master	O
and	O
slave	O
device	O
running	O
with	O
minimum	O
setup	O
and	O
hold	O
times	O
.	O
</s>
<s>
The	O
real	O
transfer	O
speed	O
between	O
the	O
Amiga	O
3000/4000	O
implementation	O
of	O
Zorro	B-Device
III	I-Device
and	O
a	O
Zorro	B-Device
III	I-Device
card	O
is	O
somewhere	O
around	O
13.5MByte/s	O
due	O
to	O
the	O
limitations	O
of	O
the	O
Buster	O
chip	O
.	O
</s>
<s>
This	O
was	O
comparable	O
to	O
Intel	O
's	O
first	O
PCI	B-Protocol
implementation	O
,	O
which	O
peaked	O
at	O
25MByte/s	O
.	O
</s>
<s>
Zorro	B-Device
III	I-Device
was	O
optimized	O
for	O
future	O
single-chip	O
implementations	O
of	O
the	O
protocol	O
,	O
but	O
the	O
resources	O
available	O
at	O
Commodore	O
in	O
1990	O
limited	O
the	O
initial	O
implementation	O
.	O
</s>
<s>
This	O
is	O
also	O
the	O
limiting	O
factor	O
with	O
3rd	O
party	O
Amiga	O
PCI	B-Protocol
expansion	O
boards	O
like	O
e.g.	O
</s>
<s>
Elbox	O
Mediator	O
PCI	B-Protocol
or	O
the	O
Matay	O
Prometheus	O
PCI	B-Protocol
(	O
about	O
12MByte/s	O
PCI	B-Protocol
to	O
68k-system	O
)	O
.	O
</s>
<s>
DMA	O
transfers	O
between	O
two	O
Zorro	B-Device
III	I-Device
cards	O
(	O
or	O
PCI	B-Protocol
cards	I-Protocol
on	O
an	O
PCI	B-Protocol
expansion	O
board	O
)	O
can	O
be	O
much	O
faster	O
.	O
</s>
