<s>
Chip	B-Device
RAM	I-Device
is	O
a	O
commonly	O
used	O
term	O
for	O
the	O
integrated	O
RAM	B-Architecture
used	O
in	O
Commodore	O
's	O
line	O
of	O
Amiga	B-Device
computers	I-Device
.	O
</s>
<s>
Chip	B-Device
RAM	I-Device
is	O
shared	O
between	O
the	O
central	B-General_Concept
processing	I-General_Concept
unit	I-General_Concept
(	O
CPU	O
)	O
and	O
the	O
Amiga	B-Device
's	O
dedicated	O
chipset	B-Device
(	O
hence	O
the	O
name	O
)	O
.	O
</s>
<s>
It	O
was	O
also	O
,	O
rather	O
misleadingly	O
,	O
known	O
as	O
"	O
graphics	O
RAM	B-Architecture
"	O
.	O
</s>
<s>
Under	O
the	O
Amiga	B-Device
architecture	O
,	O
the	O
direct	B-General_Concept
memory	I-General_Concept
access	I-General_Concept
(	O
DMA	O
)	O
controller	O
is	O
integrated	O
into	O
the	O
Agnus	B-Device
(	O
Alice	O
on	O
AGA	B-Device
models	O
)	O
chip	O
.	O
</s>
<s>
Both	O
the	O
CPU	O
and	O
other	O
members	O
of	O
the	O
chipset	B-Device
have	O
to	O
arbitrate	O
for	O
access	O
to	O
shared	O
RAM	B-Architecture
via	O
Agnus	B-Device
.	O
</s>
<s>
As	O
the	O
68000	B-Device
processor	O
used	O
in	O
early	O
Amiga	B-Device
systems	O
usually	O
only	O
accesses	O
memory	O
on	O
every	O
second	O
memory	O
cycle	O
,	O
Agnus	B-Device
operates	O
a	O
system	O
where	O
the	O
"	O
odd	O
"	O
clock	O
cycle	O
is	O
allocated	O
to	O
time-critical	O
custom	O
chip	O
access	O
and	O
the	O
"	O
even	O
"	O
cycle	O
is	O
allocated	O
to	O
the	O
CPU	O
:	O
thus	O
,	O
for	O
average	O
DMA	O
demand	O
,	O
the	O
CPU	O
is	O
not	O
typically	O
blocked	O
from	O
memory	O
access	O
and	O
may	O
run	O
without	O
interruption	O
.	O
</s>
<s>
However	O
,	O
certain	O
chipset	B-Device
DMA	O
,	O
such	O
as	O
high-resolution	O
graphics	O
with	O
a	O
larger	O
color	O
palette	O
,	O
Copper	O
,	O
or	O
blitter	B-General_Concept
operations	O
,	O
can	O
use	O
any	O
spare	O
cycles	O
,	O
effectively	O
blocking	O
cycles	O
from	O
the	O
CPU	O
.	O
</s>
<s>
In	O
such	O
situations	O
CPU	O
cycles	O
are	O
only	O
blocked	O
while	O
accessing	O
shared	O
RAM	B-Architecture
,	O
but	O
never	O
when	O
accessing	O
Fast	O
(	O
CPU-only	O
)	O
RAM	B-Architecture
(	O
when	O
present	O
)	O
or	O
ROM	O
.	O
</s>
<s>
Most	O
stock	O
Amiga	B-Device
systems	O
were	O
equipped	O
with	O
Chip	B-Device
RAM	I-Device
only	O
and	O
shipped	O
with	O
between	O
256kiB	O
and	O
2MiB	O
.	O
</s>
<s>
The	O
shared	O
RAM	B-Architecture
data	O
bus	O
is	O
16-bit	O
on	O
OCS	B-Device
and	O
ECS	B-Device
systems	O
.	O
</s>
<s>
The	O
later	O
AGA	B-Device
systems	O
use	O
a	O
32-bit	O
data	O
bus	O
controlled	O
by	O
the	O
Alice	O
coprocessor	O
(	O
replacing	O
Agnus	B-Device
)	O
and	O
32-bit	O
RAM	B-Architecture
.	O
</s>
<s>
The	O
memory	O
clock	O
runs	O
at	O
double	O
the	O
rate	O
on	O
AGA	B-Device
systems	O
.	O
</s>
<s>
As	O
a	O
result	O
,	O
chipset	B-Device
RAM	B-Architecture
bandwidth	B-General_Concept
is	O
increased	O
fourfold	O
compared	O
to	O
the	O
earlier	O
16-bit	O
design	O
.	O
</s>
<s>
The	O
ECS-based	O
A3000	O
also	O
has	O
32-bit	O
Chip	B-Device
RAM	I-Device
,	O
but	O
access	O
is	O
only	O
32-bit	O
for	O
CPU	O
operations	O
;	O
the	O
chipset	B-Device
remained	O
16-bit	O
.	O
</s>
<s>
The	O
maximum	O
amount	O
of	O
Chip	B-Device
RAM	I-Device
is	O
dependent	O
on	O
the	O
Agnus/Alice	O
version	O
.	O
</s>
<s>
The	O
original	O
Agnus	B-Device
chip	O
fitted	O
to	O
the	O
A1000	O
and	O
early	O
A2000	O
systems	O
is	O
a	O
48-pin	O
DIP	O
package	O
able	O
to	O
address	O
512KiB	O
of	O
Chip	B-Device
RAM	I-Device
.	O
</s>
<s>
Subsequent	O
versions	O
of	O
the	O
Agnus	B-Device
are	O
in	O
an	O
84-pin	O
PLCC	O
package	O
(	O
either	O
socketed	O
or	O
surface-mounted	O
)	O
.	O
</s>
<s>
All	O
models	O
except	O
the	O
A1000	O
are	O
upgradable	O
to	O
2MiB	O
of	O
Chip	B-Device
RAM	I-Device
.	O
</s>
<s>
The	O
A500	O
and	O
the	O
early	O
A2000B	O
can	O
accommodate	O
1MiB	O
by	O
installing	O
a	O
later	O
revision	O
Agnus	B-Device
chip	O
(	O
8732A	O
)	O
with	O
minimal	O
hardware	O
modifications	O
;	O
late-production	O
machines	O
usually	O
already	O
contained	O
that	O
chip	O
,	O
so	O
that	O
only	O
jumper	B-Device
modifications	O
were	O
necessary	O
.	O
</s>
<s>
Likewise	O
,	O
2MB	O
can	O
be	O
installed	O
by	O
fitting	O
an	O
8372B	O
Agnus	B-Device
and	O
extra	O
memory	O
.	O
</s>
<s>
The	O
maximum	O
amount	O
of	O
Chip	B-Device
RAM	I-Device
in	O
any	O
model	O
is	O
2MiB	O
.	O
</s>
<s>
The	O
Amiga	B-Device
4000	I-Device
motherboard	O
includes	O
a	O
non-functional	O
jumper	B-Device
that	O
anticipated	O
later	O
chips	O
and	O
is	O
labeled	O
for	O
8MiB	O
of	O
Chip	O
RAMregardless	O
of	O
its	O
position	O
,	O
the	O
system	O
only	O
recognizes	O
2MiB	O
due	O
to	O
the	O
limitations	O
of	O
the	O
Alice	O
chip	O
.	O
</s>
<s>
However	O
,	O
the	O
software	O
emulator	O
UAE	B-Device
can	O
emulate	O
an	O
Amiga	B-Device
system	O
with	O
the	O
design	O
limit	O
of	O
up	O
to	O
8MiB	O
of	O
Chip	B-Device
RAM	I-Device
.	O
</s>
<s>
Amiga	B-Device
systems	O
can	O
also	O
be	O
expanded	O
with	O
Fast	B-Device
RAM	I-Device
,	O
which	O
is	O
only	O
accessible	O
to	O
the	O
CPU	O
.	O
</s>
<s>
This	O
improves	O
execution	O
speed	O
,	O
as	O
CPU	O
cycles	O
are	O
never	O
blocked	O
even	O
when	O
the	O
custom	O
chipset	B-Device
is	O
simultaneously	O
accessing	O
Chip	B-Device
RAM	I-Device
.	O
</s>
<s>
Adding	O
Fast	B-Device
RAM	I-Device
to	O
systems	O
with	O
32-bit	O
CPUs	O
roughly	O
doubles	O
the	O
instruction	O
speed	O
,	O
as	O
the	O
more	O
advanced	O
68020	O
,	O
'	O
030	O
,	O
and	O
'	O
040	O
CPUs	O
can	O
utilize	O
more	O
memory	O
cycles	O
than	O
the	O
earlier	O
68000	B-Device
.	O
</s>
<s>
Confusingly	O
,	O
a	O
system	O
may	O
have	O
several	O
different	O
kinds	O
and	O
speeds	O
of	O
Fast	B-Device
RAM	I-Device
.	O
</s>
<s>
For	O
example	O
,	O
an	O
Amiga	B-Device
3000	I-Device
may	O
contain	O
16-bit	O
Zorro	B-Device
II	I-Device
expansion	O
RAM	B-Architecture
,	O
32-bit	O
Zorro	B-Device
III	I-Device
expansion	O
RAM	B-Architecture
,	O
32-bit	O
motherboard	O
RAM	B-Architecture
,	O
and	O
32-bit	O
CPU	O
card	O
RAM	B-Architecture
simultaneously	O
(	O
in	O
increasing	O
speed	O
order	O
)	O
.	O
</s>
<s>
Automatically	O
configured	O
RAM	B-Architecture
is	O
prioritized	O
by	O
the	O
system	O
,	O
so	O
the	O
fastest	O
memory	O
is	O
used	O
first	O
.	O
</s>
<s>
Early	O
versions	O
of	O
the	O
Amiga	B-Device
2000B	O
,	O
and	O
the	O
most	O
common	O
"	O
trapdoor	O
memory	O
expanded	O
"	O
configuration	O
of	O
the	O
Amiga	B-Device
500	I-Device
,	O
contain	O
512KiB	O
pseudo-fast	O
RAM	B-Architecture
(	O
"	O
slow	O
RAM	B-Architecture
"	O
)	O
controlled	O
by	O
Agnus	B-Device
with	O
the	O
same	O
limitations	O
as	O
Chip	B-Device
RAM	I-Device
,	O
yet	O
unusable	O
as	O
such	O
due	O
to	O
register	O
limitations	O
.	O
</s>
<s>
Numerous	O
budget	O
trapdoor	O
expansions	O
for	O
the	O
500	O
extended	O
this	O
"	O
controllerless	O
"	O
concept	O
to	O
up	O
to	O
1.8MB	O
slow	O
RAM	B-Architecture
(	O
requiring	O
a	O
Gary	O
adapter	O
for	O
addressing	O
)	O
.	O
</s>
