<s>
The	O
Amber	B-Device
processor	O
core	O
is	O
an	O
ARM	O
architecture-compatible	O
32-bit	O
reduced	B-Architecture
instruction	I-Architecture
set	I-Architecture
computing	I-Architecture
(	O
RISC	B-Architecture
)	O
processor	O
.	O
</s>
<s>
It	O
is	O
open	B-Application
source	I-Application
,	O
hosted	O
on	O
the	O
OpenCores	O
website	O
,	O
and	O
is	O
part	O
of	O
a	O
movement	O
to	O
develop	O
a	O
library	O
of	O
open	B-Application
source	I-Application
hardware	O
projects	O
.	O
</s>
<s>
The	O
Amber	B-Device
core	O
is	O
fully	O
compatible	O
with	O
the	O
ARMv2a	O
instruction	B-General_Concept
set	I-General_Concept
and	O
is	O
thus	O
supported	O
by	O
the	O
GNU	B-Application
toolchain	I-Application
.	O
</s>
<s>
This	O
older	O
version	O
of	O
the	O
ARM	B-Architecture
instruction	I-Architecture
set	I-Architecture
is	O
supported	O
because	O
it	O
is	O
not	O
covered	O
by	O
patents	O
,	O
and	O
so	O
can	O
be	O
implemented	O
with	O
no	O
license	O
from	O
ARM	O
Holdings	O
,	O
unlike	O
some	O
prior	O
open	B-Application
source	I-Application
projects	O
(	O
e.g.	O
,	O
)	O
.	O
</s>
<s>
The	O
cores	O
were	O
developed	O
in	O
Verilog	B-Language
2001	I-Language
and	O
are	O
optimized	O
for	O
field-programmable	B-Architecture
gate	I-Architecture
array	I-Architecture
(	O
FPGA	B-Architecture
)	O
synthesis	O
.	O
</s>
<s>
For	O
example	O
,	O
there	O
is	O
no	O
reset	O
logic	O
:	O
all	O
registers	O
are	O
reset	O
as	O
part	O
of	O
FPGA	B-Architecture
initialization	O
.	O
</s>
<s>
The	O
Amber	B-Device
project	O
provides	O
a	O
complete	O
embedded	O
field-programmable	B-Architecture
gate	I-Architecture
array	I-Architecture
(	O
FPGA	B-Architecture
)	O
system	O
incorporating	O
the	O
Amber	B-Device
core	O
and	O
several	O
peripherals	O
,	O
including	O
universal	O
asynchronous	O
receiver/transmitters	O
(	O
UARTs	O
)	O
,	O
timers	O
,	O
and	O
an	O
Ethernet	O
MAC	O
.	O
</s>
<s>
The	O
Amber	B-Device
project	O
provides	O
two	O
versions	O
of	O
the	O
core	O
.	O
</s>
<s>
Both	O
cores	O
implement	O
the	O
same	O
instruction	B-General_Concept
set	I-General_Concept
architecture	I-General_Concept
(	O
ISA	O
)	O
and	O
are	O
fully	O
software	O
compatible	O
.	O
</s>
<s>
The	O
Amber	B-Device
23	O
has	O
a	O
3-stage	O
pipeline	O
,	O
a	O
unified	O
instruction	O
and	O
data	O
cache	O
,	O
a	O
Wishbone	B-Architecture
interface	O
,	O
and	O
is	O
capable	O
of	O
0.75	O
DMIPS	O
(	O
Dhrystone	O
)	O
per	O
MHz	O
.	O
</s>
<s>
The	O
Amber	B-Device
23	O
core	O
is	O
a	O
very	O
small	O
32-bit	O
core	O
that	O
performs	O
well	O
.	O
</s>
<s>
Load	B-General_Concept
and	I-General_Concept
store	I-General_Concept
instructions	I-General_Concept
require	O
three	O
cycles	O
.	O
</s>
<s>
The	O
core	O
's	O
pipeline	O
is	O
stalled	O
either	O
when	O
a	O
cache	O
miss	O
occurs	O
,	O
or	O
when	O
the	O
core	O
performs	O
a	O
Wishbone	B-Architecture
access	O
.	O
</s>
<s>
The	O
Amber	B-Device
25	O
has	O
a	O
5-stage	O
pipeline	O
,	O
separate	O
data	O
and	O
instruction	O
caches	O
,	O
a	O
Wishbone	B-Architecture
interface	O
,	O
and	O
is	O
capable	O
of	O
1.0	O
DMIPS	O
per	O
MHz	O
.	O
</s>
<s>
The	O
Amber	B-Device
25	O
core	O
provides	O
30	O
to	O
40%	O
better	O
performance	O
than	O
the	O
Amber	B-Device
23	O
core	O
and	O
is	O
30	O
to	O
40%	O
larger	O
.	O
</s>
<s>
Load	B-General_Concept
and	I-General_Concept
store	I-General_Concept
instructions	I-General_Concept
also	O
execute	O
in	O
one	O
cycle	O
unless	O
there	O
is	O
a	O
register	O
conflict	O
with	O
a	O
following	O
instruction	O
.	O
</s>
<s>
The	O
core	O
's	O
pipeline	O
is	O
stalled	O
when	O
a	O
cache	O
miss	O
occurs	O
in	O
either	O
cache	O
,	O
when	O
an	O
instruction	O
conflict	O
is	O
detected	O
,	O
when	O
a	O
complex	O
shift	O
is	O
executed	O
,	O
or	O
when	O
the	O
core	O
performs	O
a	O
Wishbone	B-Architecture
access	O
.	O
</s>
<s>
Both	O
cores	O
have	O
been	O
verified	O
by	O
booting	O
a	O
Linux	B-Operating_System
2.4	I-Operating_System
kernel	B-Operating_System
.	O
</s>
<s>
Versions	O
of	O
the	O
Linux	B-Operating_System
kernel	I-Operating_System
from	O
the	O
2.4	O
branch	O
and	O
earlier	O
contain	O
configurations	O
for	O
the	O
supported	O
ISA	O
.	O
</s>
<s>
Versions	O
of	O
the	O
Linux	B-Operating_System
kernel	I-Operating_System
2.6	I-Operating_System
and	O
later	O
do	O
not	O
explicitly	O
support	O
the	O
ARM	O
v2a	O
ISA	O
and	O
so	O
need	O
more	O
modifications	O
to	O
run	O
.	O
</s>
<s>
The	O
cores	O
do	O
not	O
contain	O
a	O
memory	B-General_Concept
management	I-General_Concept
unit	I-General_Concept
(	O
MMU	O
)	O
so	O
they	O
can	O
only	O
run	O
a	O
non-virtual	O
memory	O
variant	O
of	O
Linux	B-Operating_System
,	O
such	O
as	O
μClinux	B-Application
.	O
</s>
