<s>
The	O
Alternate	B-Device
Instruction	I-Device
Set	I-Device
(	O
AIS	O
)	O
is	O
a	O
second	O
32-bit	O
instruction	B-General_Concept
set	I-General_Concept
architecture	I-General_Concept
found	O
in	O
some	O
x86	O
CPUs	O
made	O
by	O
VIA	O
Technologies	O
.	O
</s>
<s>
On	O
these	O
VIA	B-Device
C3	I-Device
processors	O
,	O
the	O
second	O
hidden	O
processor	O
mode	O
is	O
accessed	O
by	O
executing	O
the	O
x86	O
instruction	O
ALTINST	B-Device
(	O
)	O
.	O
</s>
<s>
If	O
AIS	O
mode	O
has	O
been	O
enabled	O
,	O
the	O
processor	O
will	O
perform	O
a	O
JMP	B-Device
EAX	I-Device
and	O
begin	O
executing	O
AIS	O
instructions	O
at	O
the	O
address	O
of	O
the	O
EAX	O
register	O
.	O
</s>
<s>
Using	O
AIS	O
allows	O
native	O
access	O
to	O
the	O
Centaur	O
Technology-designed	O
RISC	B-Architecture
core	O
inside	O
the	O
processor	O
.	O
</s>
<s>
The	O
manufacturer	O
describes	O
the	O
Alternate	B-Device
Instruction	I-Device
Set	I-Device
as	O
"	O
an	O
extended	O
set	O
of	O
integer	O
,	O
MMX	B-Architecture
,	O
floating-point	O
,	O
and	O
3DNow	B-General_Concept
!	I-General_Concept
</s>
<s>
A	O
proposal	O
made	O
in	O
2002	O
to	O
add	O
AIS	O
support	O
to	O
the	O
Netwide	B-Application
Assembler	I-Application
(	O
NASM	B-Application
)	O
was	O
partially	O
declined	O
in	O
2005	O
,	O
on	O
the	O
basis	O
that	O
NASM	B-Application
was	O
an	O
x86	O
assembler	O
,	O
and	O
AIS	O
is	O
a	O
separate	O
instruction	B-General_Concept
set	I-General_Concept
.	O
</s>
<s>
The	O
Centaur	O
Technologies	O
verification	O
team	O
,	O
in	O
a	O
2014	O
paper	O
about	O
the	O
VIA	B-Device
Nano	I-Device
,	O
included	O
some	O
short	O
lists	O
of	O
micro-instructions	O
including	O
ADDIG	O
,	O
JLINK	O
,	O
JMP_ALL	O
,	O
MVIG	O
,	O
NLOOPE	O
,	O
STORE_PRAM	O
,	O
plus	O
micro-operations	O
XADD	O
and	O
XSUB	O
.	O
</s>
<s>
From	O
x86	O
mode	O
,	O
the	O
availability	O
of	O
the	O
Alternate	B-Device
Instruction	I-Device
Set	I-Device
can	O
be	O
detected	O
by	O
executing	O
a	O
CPUID	B-Architecture
with	O
the	O
EAX	O
register	O
set	O
to	O
0xc0000001	O
and	O
then	O
examining	O
the	O
EDX	O
register	O
.	O
</s>
<s>
If	O
AIS	O
is	O
supported	O
by	O
the	O
CPU	O
,	O
then	O
its	O
status	O
can	O
be	O
checked	O
and	O
altered	O
through	O
the	O
Model-specific	B-General_Concept
registers	I-General_Concept
,	O
by	O
checking	O
and	O
setting	O
the	O
Feature	O
Control	O
Register	O
(	O
FCR	O
,	O
register	O
0x1107	O
)	O
.	O
</s>
<s>
If	O
(	O
"	O
ALTINST	B-Device
"	O
)	O
is	O
set	O
to	O
1	O
,	O
then	O
AIS	O
is	O
enabled	O
.	O
</s>
<s>
If	O
the	O
x86	O
ALTINST	B-Device
jump	O
instruction	O
is	O
executed	O
when	O
AIS	O
mode	O
is	O
disabled	O
,	O
then	O
the	O
processor	O
will	O
generate	O
an	O
Invalid	O
Instruction	O
exception	O
.	O
</s>
<s>
Setting	O
the	O
AIS-enabled	O
bit	O
requires	O
privileged	O
access	O
,	O
and	O
should	O
be	O
set	O
using	O
a	O
read-modify-write	B-Operating_System
sequence	O
.	O
</s>
<s>
In	O
2018	O
Christopher	O
Domas	O
discovered	O
that	O
some	O
Samuel	O
2	O
processors	O
came	O
with	O
the	O
Alternate	B-Device
Instruction	I-Device
Set	I-Device
enabled	O
by	O
default	O
and	O
that	O
by	O
executing	O
AIS	O
instructions	O
from	O
user	B-Operating_System
space	I-Operating_System
,	O
it	O
was	O
possible	O
to	O
gain	O
privilege	O
escalation	O
from	O
Ring	O
3	O
to	O
Ring	O
0	O
.	O
</s>
<s>
Domas	O
had	O
partially	O
reverse	O
engineered	O
the	O
AIS	O
instruction	B-General_Concept
set	I-General_Concept
using	O
automated	O
fuzzing	O
against	O
a	O
cluster	O
of	O
seven	O
thin	B-Device
clients	I-Device
.	O
</s>
<s>
Domas	O
used	O
the	O
terms	O
"	O
deeply	O
embedded	O
core	O
"	O
(	O
DEC	O
)	O
plus	O
"	O
deeply	B-Device
embedded	I-Device
instruction	I-Device
set	I-Device
"	O
(	O
DEIS	O
)	O
for	O
the	O
RISC	B-Architecture
instruction	I-Architecture
set	I-Architecture
,	O
"	O
launch	O
instruction	O
"	O
for	O
ALTINST	B-Device
,	O
"	O
bridge	O
instruction	O
"	O
for	O
the	O
x86	O
prefix	O
wrapper	O
,	O
"	O
global	O
configuration	O
register	O
"	O
for	O
the	O
Feature	O
Control	O
Register	O
(	O
FCR	O
)	O
,	O
and	O
documented	O
the	O
privilege	O
escalation	O
with	O
the	O
name	O
"	O
Rosenbridge	O
"	O
.	O
</s>
