<s>
The	O
Alpha	B-General_Concept
21464	I-General_Concept
is	O
an	O
unfinished	O
microprocessor	B-Architecture
that	O
implements	O
the	O
Alpha	B-Device
instruction	B-General_Concept
set	I-General_Concept
architecture	I-General_Concept
(	O
ISA	O
)	O
developed	O
by	O
Digital	O
Equipment	O
Corporation	O
and	O
later	O
by	O
Compaq	O
after	O
it	O
acquired	O
Digital	O
.	O
</s>
<s>
The	O
microprocessor	B-Architecture
was	O
also	O
known	O
as	O
EV8	O
(	O
codenamed	O
Araña	O
)	O
.	O
</s>
<s>
Slated	O
for	O
a	O
2004	O
release	O
,	O
it	O
was	O
canceled	O
on	O
25	O
June	O
2001	O
when	O
Compaq	O
announced	O
that	O
Alpha	B-Device
would	O
be	O
phased	O
out	O
in	O
favor	O
of	O
Itanium	B-General_Concept
by	O
2004	O
.	O
</s>
<s>
When	O
it	O
was	O
canceled	O
,	O
the	O
Alpha	B-General_Concept
21464	I-General_Concept
was	O
at	O
a	O
late	O
stage	O
of	O
development	O
but	O
had	O
not	O
been	O
taped	O
out	O
.	O
</s>
<s>
The	O
21464	O
's	O
origins	O
began	O
in	O
the	O
mid-1990s	O
when	O
computer	O
scientist	O
Joel	O
Emer	O
was	O
inspired	O
by	O
Dean	O
Tullsen	O
's	O
research	O
into	O
simultaneous	B-Operating_System
multithreading	I-Operating_System
(	O
SMT	O
)	O
at	O
the	O
University	O
of	O
Washington	O
.	O
</s>
<s>
Compaq	O
made	O
the	O
announcement	O
that	O
the	O
next	O
Alpha	B-Device
microprocessor	B-Architecture
would	O
use	O
SMT	O
in	O
October	O
1999	O
at	O
Microprocessor	B-Architecture
Forum	O
1999	O
.	O
</s>
<s>
At	O
that	O
time	O
,	O
it	O
was	O
expected	O
that	O
systems	O
using	O
the	O
Alpha	B-General_Concept
21464	I-General_Concept
would	O
ship	O
in	O
2003	O
.	O
</s>
<s>
The	O
microprocessor	B-Architecture
was	O
an	O
eight-issue	O
superscalar	B-General_Concept
design	O
with	O
out-of-order	B-General_Concept
execution	I-General_Concept
,	O
four-way	O
SMT	O
and	O
a	O
deep	O
pipeline	O
.	O
</s>
<s>
It	O
fetches	O
16	O
instructions	O
from	O
a	O
64KB	O
two-way	O
set-associative	B-General_Concept
instruction	O
cache	O
.	O
</s>
<s>
The	O
branch	B-General_Concept
predictor	I-General_Concept
then	O
selected	O
the	O
"	O
good	O
"	O
instructions	O
and	O
entered	O
them	O
into	O
a	O
collapsing	O
buffer	O
.	O
</s>
<s>
The	O
front-end	O
had	O
significantly	O
more	O
stages	O
than	O
previous	O
Alpha	B-Device
implementation	O
and	O
as	O
a	O
result	O
,	O
the	O
21464	O
had	O
a	O
significant	O
minimum	O
branch	B-General_Concept
misprediction	I-General_Concept
penalty	O
of	O
14	O
cycles	O
.	O
</s>
<s>
The	O
microprocessor	B-Architecture
used	O
an	O
advanced	O
branch	B-General_Concept
prediction	I-General_Concept
algorithm	O
to	O
minimize	O
these	O
costly	O
penalties	O
.	O
</s>
<s>
Implementing	O
SMT	O
required	O
the	O
replication	O
of	O
certain	O
resources	O
such	O
as	O
the	O
program	B-General_Concept
counter	I-General_Concept
.	O
</s>
<s>
Instead	O
of	O
one	O
program	B-General_Concept
counter	I-General_Concept
,	O
there	O
were	O
four	O
program	B-General_Concept
counters	I-General_Concept
,	O
one	O
for	O
each	O
thread	O
.	O
</s>
<s>
This	O
was	O
backed	O
by	O
an	O
on-die	O
3MB	O
,	O
six-way	O
set-associative	B-General_Concept
unified	O
secondary	O
cache	O
(	O
Scache	O
)	O
.	O
</s>
<s>
The	O
system	O
interface	O
was	O
similar	O
to	O
that	O
of	O
the	O
Alpha	B-General_Concept
21364	I-General_Concept
.	O
</s>
<s>
There	O
were	O
integrated	B-General_Concept
memory	I-General_Concept
controllers	I-General_Concept
that	O
provided	O
ten	O
RDRAM	O
channels	O
.	O
</s>
<s>
Multiprocessing	B-Operating_System
was	O
facilitated	O
by	O
a	O
router	B-Protocol
that	O
provided	O
links	O
to	O
other	O
21464s	O
,	O
and	O
it	O
architecturally	O
supported	O
512-way	O
multiprocessing	B-Operating_System
without	O
glue	O
logic	O
.	O
</s>
<s>
It	O
was	O
to	O
be	O
implemented	O
in	O
a	O
0.125μm	O
(	O
sometimes	O
referred	O
to	O
as	O
0.13μm	O
)	O
complementary	B-Device
metal	I-Device
–	I-Device
oxide	I-Device
–	I-Device
semiconductor	I-Device
(	O
CMOS	B-Device
)	O
process	O
with	O
seven	O
layers	O
of	O
copper	O
interconnect	O
,	O
partially	O
depleted	O
silicon-on-insulator	B-Algorithm
(	O
PD-SOI	O
)	O
,	O
and	O
low-K	B-Algorithm
dielectric	I-Algorithm
.	O
</s>
<s>
Tarantula	O
was	O
the	O
code-name	O
for	O
an	O
extension	O
of	O
the	O
Alpha	B-Device
architecture	O
under	O
consideration	O
and	O
a	O
derivative	O
of	O
the	O
Alpha	B-General_Concept
21464	I-General_Concept
that	O
implemented	O
the	O
aforementioned	O
extension	O
.	O
</s>
<s>
The	O
extension	O
was	O
to	O
provide	O
Alpha	B-Device
with	O
a	O
vector	O
processing	O
capability	O
.	O
</s>
<s>
Other	O
EV8	O
follow-up	O
candidates	O
included	O
a	O
multicore	B-Architecture
design	O
with	O
two	O
EV8	O
cores	O
and	O
a	O
4.0GHz	O
operating	O
frequency	O
.	O
</s>
